KR0152944B1 - Semiconductor package and method for manufacturing the same - Google Patents
Semiconductor package and method for manufacturing the sameInfo
- Publication number
- KR0152944B1 KR0152944B1 KR1019950022834A KR19950022834A KR0152944B1 KR 0152944 B1 KR0152944 B1 KR 0152944B1 KR 1019950022834 A KR1019950022834 A KR 1019950022834A KR 19950022834 A KR19950022834 A KR 19950022834A KR 0152944 B1 KR0152944 B1 KR 0152944B1
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- South Korea
- Prior art keywords
- substrate
- package
- wire
- semiconductor package
- semiconductor chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로, 종래의 비지에이(BGA) 패키지는 기판의 상부에 이엠시(EPOXY MOLDING COMPUND)가 몰딩되어 있는 구조로 기판과 이엠시의 계면박리 현상 및 패키지의 휨이 발생하고, 몰딩시 와이어의 상부에서 이엠시가 주입이 되어 와이어의 휨이 발생하는 등의 패키지의 신뢰성이 저하되는 문제점이 있었던 바, 본 발명의 반도체 패키지는 기판(10)의 상,하부를 감싸도록 이엠시(16)가 일체로 몰딩이 되어 기판(10)과 이엠시(16)의 계면박리 현상 및 종래 패키지의 상,하부 비대칭 구조에서 발생하는 패키지의 휨을 방지하는 효과가 있으며, 또한 몰딩기계의 진행시 기판의 상,하부에서 이엠시(16)가 주입이 되도록 함으로써 와이어(14)의 휨을 방지하는 효과가 있는 등, 패키지 전체의 신뢰성을 향상시키는 효과가 있는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same. In the conventional BGA package, an EPOXY MOLDING COMPUND is molded on an upper surface of the substrate, and the interface peeling phenomenon between the substrate and the EMSC and the There was a problem that warpage occurred, and the reliability of the package such as the warpage of the wire is caused by the injection of the emshi in the upper portion of the wire during molding, the semiconductor package of the present invention is the upper and lower parts of the substrate 10 Since the EMS 16 is integrally molded so as to enclose the substrate 10, the EMS 10 may be prevented from interfacing with the substrate 10 and the EMS 16 and the warpage of the package occurring in the upper and lower asymmetric structures of the conventional package. When the molding machine is in progress, the EMS 16 is injected into the upper and lower portions of the substrate, thereby preventing the warpage of the wires 14, thereby improving the reliability of the entire package.
Description
제1도는 종래 플라스틱 비지에이(BGA) 패키지의 구성을 보인 종단면도.1 is a longitudinal cross-sectional view showing the configuration of a conventional plastic BGA package.
제2도는 종래 플라스틱 비지에이(BGA) 패키지의 기판을 보인 평면도.2 is a plan view showing a substrate of a conventional plastic BGA package.
제3도는 본 발명 비지에이(BGA) 패키지의 구성을 보인 종단면도.Figure 3 is a longitudinal cross-sectional view showing the configuration of the present invention BGA package.
제4도는 본 발명 비지에이(BGA) 패키지의 기판을 보인 평면도.4 is a plan view showing a substrate of the present invention BGA package.
제5도는 본 발명 비지에이(BGA) 패키지가 몰딩되는 상태를 보인 종단면도.Figure 5 is a longitudinal cross-sectional view showing a state in which the present invention BGA package is molded.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 기판 10a,10b : 관통홀10: substrate 10a, 10b: through hole
10c : 단차홈 11 : 상부 도체패턴10c: step groove 11: upper conductor pattern
12 : 하부 도체패턴 13 : 반도체 칩12: lower conductor pattern 13: semiconductor chip
14 : 와이어 15 : 솔더볼14 wire 15 solder ball
16 : 이엠시 18 : 하부 금형16: EMSI 18: lower mold
18a : 돌부 18b : 에어홀18a: protrusion 18b: air hole
본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로, 특히 기판(SUBSTRATE)의 상,하부를 감싸도록 몰딩하여 와이어의 휨 등을 방지함으로써 패키지의 신뢰성을 향상시킨 반도체 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package and a method of manufacturing the same, which improve the reliability of the package by molding the upper and lower parts of the substrate to prevent bending of the wire.
최근 다(多)핀 패키지의 하나로써 각광을 받고있는 플라스틱(PLASTIC) 비지에이(BGA:BALL GRID ARRAYS) 패키지는 큐에프피(QFP:QUAD FLAT PACKAGES)보다 통상 3배나 넓은 리드 피치(PITCH)로 2배 이상의 핀(PIN)을 낼 수 있으므로 널리 사용되고 있다.The plastic BGA (BALL GRID ARRAYS) package, which has been in the spotlight as one of the multi-pin packages, has a lead pitch of three times wider than QFP (QUAD FLAT PACKAGES). It is widely used because it can produce more than twice the pins.
상기 큐에프피(QFP)는 다핀화(HIGH-PIN化)로 되면서 아웃리드가 미세 피치화(FINE-PITCH化)되게 되므로 리드의 휨(BENT)이 발생되고, 피시비(PCB:PRINTED CIRCUIT BOARD)에 표면실장할때 정렬(ALIGNMENT) 및 솔더(SOLDER)의 양의 조절이 어려운 단점이 내재하지만, 상기 비지에이(BGA)는 아웃리드가 없고 그대신 솔더볼이 상기 아웃리드의 역할을 하게 되므로 상기 큐에프피(QFP)의 단점을 해소할 수 있다. 또한, 상기 비지에이(BGA)는 큐에프피(QFP)에 비하여 반도체 칩으로 부터 솔더볼까지의 전기적 경로(ELECTRICAL PATH)가 짧기 때문에 전기적 저항이 작아지게 되어 전기적 특성도 우수하다.The QFP is multi-pinned (HIGH-PINized) and the outlead is fine pitched (FINE-PITCHized) so that the bending of the lead (BENT) occurs, the PCB (PRINTED CIRCUIT BOARD) The disadvantage is that it is difficult to control the amount of alignment and solder when surface-mounting on the substrate. However, the BGA does not have an outlead and instead the solder ball plays the role of the outlead. The shortcomings of QFP can be eliminated. In addition, since the BGA has a shorter electrical path from the semiconductor chip to the solder ball than the QFP, the electrical resistance is reduced, and thus the electrical characteristics are excellent.
이제, 종래에 일반적으로 사용되고 있는 플라스틱 비지에이 패키지에 대한 구조 및 제조공정을 제1도 및 제2도를 참조로하여 개략적으로 살펴보면 다음과 같다.Now, a structure and a manufacturing process of a plastic busy package generally used in the related art will be described with reference to FIGS. 1 and 2 as follows.
도시된 바와 같이, 종래의 비지에이 패키지는 기판(SUBSTRATE)(1)의 중앙에 반도체 칩(2)이 패드(3)에 의해 부착되어 있다. 그리고, 상기 기판(1)의 소정부위는 관통되어 있어 상,하부가 도체패턴(4)(5)으로 연결되어 있으며, 그 상부 도체패턴(4)의 일단에는 상기 반도체 칩(2)과 전기적인 연결을 위해 와이어(6)가 연결되고, 상기 하부 도체패턴(5)의 소정부위에는 복수개의 솔더볼(7)이 부착되어 있으며, 상기 반도체 칩(2)과 와이어(6)를 포함하는 기판(1)의 상부 일정면적이 이엠시(EMC:EPOXY MOLDING COMPUND)(8)로 몰딩된 구조로 되어 있다.As shown in the drawing, in the conventional business package, the semiconductor chip 2 is attached to the center of the substrate SUBSTRATE 1 by the pad 3. A predetermined portion of the substrate 1 is penetrated, and upper and lower portions thereof are connected to the conductive patterns 4 and 5, and one end of the upper conductive pattern 4 is electrically connected to the semiconductor chip 2. A wire 6 is connected for connection, a plurality of solder balls 7 are attached to a predetermined portion of the lower conductor pattern 5, and a substrate 1 including the semiconductor chip 2 and the wire 6. ), The upper constant area is molded in EMC (EPOXY MOLDING COMPUND) (8).
이와 같은 종래의 반도체 패키지는 기판(1)에 설치되어 있는 패드(3)의 상부에 반도체 칩(2)을 고정 부착하고, 그 반도체 칩(2)과 상기 기판(1)에 형성되어 있는 상부 도체패턴(4)을 와이어(6)로 연결하는 와이어 본딩을 실시하며, 상기 반도체 칩(2)과 와이어(6)를 포함하는 일정면적을 이엠시(8)로 몰딩하는 순서로 제조한다. 그리고, 마지막으로 솔더볼(7)을 하부 도체패턴(5)에 부착하는 리플로우(REFLOW)공정을 진행하여 외부로의 연결단자를 이루도록 함으로써 비지에이(BGA) 패키지가 완성되는 것이다.In such a conventional semiconductor package, the semiconductor chip 2 is fixedly attached to an upper portion of the pad 3 provided on the substrate 1, and the semiconductor chip 2 and the upper conductor formed on the substrate 1 are fixed. Wire bonding connecting the pattern 4 to the wires 6 is performed, and a predetermined area including the semiconductor chip 2 and the wires 6 is manufactured in the order of molding with the EMS8. Finally, the BGA package is completed by performing a reflow process of attaching the solder ball 7 to the lower conductor pattern 5 to form a connection terminal to the outside.
그러나, 상기와 같은 반도체 패키지는 기판(1)의 상부에 이엠시(8)가 몰딩되어 있는 구조로 기판(1)과 이엠시(8) 사이의 계면박리 현상이 발생하고, 기판(1)의 상,하부가 비대칭 구조로 패키지의 휨이 발생하며, 몰딩공정시 와이어(6)의 상부에서 이엠시(8)를 주입하는 방법으로 와이어(6)의 휨 등이 발생하여 전체적인 패키지의 신뢰성이 떨어지는 문제점이 있었다.However, the semiconductor package as described above has a structure in which the EMSM 8 is molded on the substrate 1, so that an interfacial peeling phenomenon occurs between the substrate 1 and the EMSM 8. The upper and lower parts are asymmetrical in structure to warp the package, and in the molding process, the method of injecting the EMS 8 from the upper part of the wire 6 causes the warp of the wire 6 to decrease overall reliability of the package. There was a problem.
따라서, 본 발명의 목적은 기판의 상,하부가 이엠시로 연결이 되도록 몰딩을 하여 기판과 이엠시 사이의 계면박리 현상을 방지하고, 패키지의 휨을 방지할 수 있는 반도체 패키지를 제공함에 있다.Accordingly, an object of the present invention is to provide a semiconductor package that can be molded so that the upper and lower portions of the substrate are connected to the EMS, to prevent the interface peeling between the substrate and the EMS, and to prevent the package from warping.
본 발명의 다른 목적은 몰딩시 기판의 상,하부에서 이엠시가 주입이 되도록 하여 와이어의 휨이 발생하는 것을 방지하는데 적합한 반도체 패키지 및 그 제조방법을 제공함에 있다.Another object of the present invention is to provide a semiconductor package suitable for preventing the occurrence of warpage of the wire by injecting the EMM in the upper and lower portions of the substrate during molding and a method of manufacturing the same.
상기와 같은 본 발명의 목적을 달성하기 위하여 기판의 중앙에 반도체 칩이 부착되어 상부 도체패턴과 와이어로 연결되어 있고, 기판의 하부 도체패턴에는 솔더볼이 부착되어 있으며, 상기 반도체 칩과 와이어를 포함하는 일정면적이 이엠시로 몰딩되어 있는 반도체 패키지에 있어서, 상기 이엠시는 솔더볼을 제외한 기판의 상,하부를 감싸도록 몰딩되어 있는 것을 특징으로 하는 반도체 패키지가 제공된다.In order to achieve the object of the present invention as described above, a semiconductor chip is attached to the center of the substrate and connected to the upper conductor pattern and the wire. A solder ball is attached to the lower conductor pattern of the substrate. A semiconductor package in which a predetermined area is molded by an EMS, wherein the EMS is molded to surround upper and lower portions of the substrate excluding solder balls.
또한, 상기 목적을 달성하기 위한 본 발명의 반도체 패키지 제조방법은, 기판의 중앙에 반도체 칩을 부착하는 단계와, 그 반도체 칩과 상부 도체패턴을 와이어로 와이어 본딩하는 단계와, 상기 반도체 칩과 와이어를 포함하는 기판의 상,하부를 감싸도록 몰딩하는 단계와, 상기 기판의 하부에 형성되어 있는 하부 도체패턴에 솔더볼을 부착하는 단계로 이루어지는 반도체 패키지 제조공정에 있어서, 상기 몰딩단계에서 와이어의 휨을 방지하기 위해 기판의 상,하부로 이엠시가 주입이 되도록 하는 것을 특징으로 하는 것이다.In addition, the semiconductor package manufacturing method of the present invention for achieving the above object, the step of attaching a semiconductor chip in the center of the substrate, the step of wire bonding the semiconductor chip and the upper conductor pattern with a wire, the semiconductor chip and the wire In the semiconductor package manufacturing process consisting of molding to cover the upper, lower portions of the substrate including a; and attaching a solder ball to the lower conductor pattern formed on the lower portion of the substrate, preventing bending of the wire in the molding step To this end, the imsi is injected into the upper and lower portions of the substrate.
이하, 첨부된 도면을 참고로 하여 본 발명의 실시례를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제3도는 본 발명 비지에이(BGA) 패키지의 구성을 보인 종단면도이고, 제4도는 본 발명 비지에이(BGA) 패키지의 기판을 보인 평면도이며, 제5도는 본 발명 비지에이(BGA) 패키지의 몰딩되는 상태를 보인 종단면도이다.3 is a longitudinal cross-sectional view showing the configuration of the present invention BGA package, Figure 4 is a plan view showing a substrate of the present invention BGA package, Figure 5 is a molding of the present invention BGA package It is a longitudinal cross-sectional view which shows the state to become.
도시된 바와 같이, 본 발명의 실시례에 따른 비지에이 패키지는 기판(10)의 소정부위가 관통되어 상,하부 도체패턴(11)(12)이 연결 형성되어 있고, 상기 기판(10)의 중앙에는 반도체 칩(13)이 부착되어 있으며, 그 반도체 칩(13)과 상기 상부 도체패턴(11)은 와이어(14)로 연결되어 있는 것이다. 그리고, 하부 도체패턴(12)에는 솔더볼(15)이 부착되어 있고, 상기 솔더볼(15)이 외부와 연결되는 하면을 제외한 반도체 칩(13) 및 와이어(14)를 포함하는 기판(10)의 상,하부를 감싸도록 이엠시(16)로 몰딩되어 있는 것이다.As shown, the BI package according to an embodiment of the present invention is a predetermined portion of the substrate 10 is penetrated through the upper and lower conductor patterns (11, 12) is formed, the center of the substrate 10 The semiconductor chip 13 is attached to the semiconductor chip 13, and the semiconductor chip 13 and the upper conductor pattern 11 are connected by a wire 14. The lower conductive pattern 12 has a solder ball 15 attached thereto, and the upper surface of the substrate 10 including the semiconductor chip 13 and the wire 14 except for a lower surface to which the solder ball 15 is connected to the outside. , It is molded with the EMS 16 to wrap the lower part.
또한, 상기 기판(10)의 소정부위에는 몰딩시 기판(10)을 중심으로 상,하부의 이엠시(16)가 일체로 연결이 되도록 수개의 관통홀(10a)(10b)이 형성되어 있고, 상기 기판(10)의 중앙에는 그 기판(10)에 부착되는 반도체 칩(13)의 높이를 낮춤으로써 패키지의 전체 높이를 낮추기 위하여 사각형의 단차홈(10c)이 형성되어 있는 것을 특징으로 한다.In addition, a plurality of through holes 10a and 10b are formed in a predetermined portion of the substrate 10 so that the upper and lower emsi 16 may be integrally connected to the substrate 10 during molding. A rectangular stepped groove 10c is formed in the center of the substrate 10 so as to lower the height of the package by lowering the height of the semiconductor chip 13 attached to the substrate 10.
도면중 미설명부호 17은 상부 금형, 18은 하부 금형, 18a는 하부 금형(18)에 형성되어 있는 돌부, 18b는 몰딩시 에어를 흡입하는 에어홀이다.In the drawings, reference numeral 17 is an upper mold, 18 is a lower mold, 18a is a protrusion formed in the lower mold 18, and 18b is an air hole that sucks air during molding.
이와 같이 구성되어 있는 본 발명의 제조방법을 설명하면 다음과 같다.Referring to the manufacturing method of the present invention configured as described above is as follows.
기판(10)의 중앙에 반도체 칩(13)을 부착하는 단계와, 상기 반도체 칩(13)과 기판(10)의 상면에 형성되어 있는 상부 도체패턴(11)을 와이어(14)로 연결하는 와이어 본딩 단계와, 하부 도체패턴(12)을 제외한 반도체 칩(13)과 와이어(14)를 포함하는 기판(10)의 상,하부를 감싸도록 이엠시(16)로 몰딩하는 단계와, 하부 도체패턴(12) 각각의 솔더볼(15)을 부착하는 단계의 순서로 진행하는 비지에이 패키지 제조순서는 일반적인 제조순서와 동일하다.Attaching the semiconductor chip 13 to the center of the substrate 10 and a wire connecting the semiconductor chip 13 and the upper conductor pattern 11 formed on the upper surface of the substrate 10 with a wire 14. Bonding to, forming the top and bottom portions of the substrate 10 including the semiconductor chip 13 and the wire 14 except for the lower conductor pattern 12 and molding the EMS 16 to cover the lower conductor pattern, and (12) The manufacturing process of the BIGEEE package which proceeds in the order of attaching each solder ball 15 is the same as the general manufacturing order.
여기서, 본 발명은 몰딩단계 진행시 기판(10)의 상,하부에서 이엠시(15)를 주입하여 와이어(14)의 휨이 방지되도록 하였다.Here, the present invention is to prevent the warpage of the wire 14 by injecting the EM 15 in the upper and lower portions of the substrate 10 during the molding step.
또한, 상기 몰딩단계의 진행시 제5도에 도시된 바와 같이, 하부 도체패턴(12)에 이엠시(16)가 유입되는 것을 방지하기 위하여, 하부 금형(18)에 설치한 돌부(18a)의 중심에는 에어홀(18b)이 형성되어 있어, 몰딩시 에어홀(18b)을 통하여 공기를 흡입함으로써 돌부(18a)와 하부 도체패턴(12)의 접촉력을 극대화 시키는 것이다.In addition, as shown in FIG. 5 at the time of the molding step, in order to prevent the emsi 16 from flowing into the lower conductor pattern 12, the protrusions 18a of the lower mold 18 are disposed. An air hole 18b is formed at the center to maximize the contact force between the protrusion 18a and the lower conductor pattern 12 by sucking air through the air hole 18b during molding.
이상에서 상세히 설명한 바와 같이, 본 발명의 반도체 패키지는 기판의 상,하부를 감싸도록 이엠시가 일체로 몰딩이 되어 기판과 이엠시의 계면박리 현상 및 종래 패키지의 상,하부 비대칭 구조에서 발생하는 패키지의 휨을 방지하는 효과가 있으며, 또한 몰딩단계의 진행시 기판의 상,하부에서 이엠시가 주입이 되도록 함으로써 와이어의 휨을 방지하는 효과가 있는 등, 패키지 전체의 신뢰성을 향상시키는 효과가 있는 것이다.As described in detail above, the semiconductor package of the present invention is a package that is formed in the surface of the emem is integrally molded so as to surround the upper and lower parts of the substrate and the emsi and the upper and lower asymmetric structure of the conventional package There is an effect of preventing the warpage of, and also by the emsi is injected into the upper and lower portions of the substrate during the molding step, there is an effect of preventing the warpage of the wire, such as to improve the reliability of the entire package.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950022834A KR0152944B1 (en) | 1995-07-28 | 1995-07-28 | Semiconductor package and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950022834A KR0152944B1 (en) | 1995-07-28 | 1995-07-28 | Semiconductor package and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970008532A KR970008532A (en) | 1997-02-24 |
| KR0152944B1 true KR0152944B1 (en) | 1998-10-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950022834A KR0152944B1 (en) | 1995-07-28 | 1995-07-28 | Semiconductor package and method for manufacturing the same |
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| Country | Link |
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| KR (1) | KR0152944B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100520443B1 (en) * | 1997-09-13 | 2006-03-14 | 삼성전자주식회사 | Chip scale package and its manufacturing method |
-
1995
- 1995-07-28 KR KR1019950022834A patent/KR0152944B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR970008532A (en) | 1997-02-24 |
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