KR0152920B1 - Semiconductor thin film manufacturing method - Google Patents
Semiconductor thin film manufacturing method Download PDFInfo
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- KR0152920B1 KR0152920B1 KR1019950007981A KR19950007981A KR0152920B1 KR 0152920 B1 KR0152920 B1 KR 0152920B1 KR 1019950007981 A KR1019950007981 A KR 1019950007981A KR 19950007981 A KR19950007981 A KR 19950007981A KR 0152920 B1 KR0152920 B1 KR 0152920B1
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- etching
- contact surface
- insulating film
- photoresist
- semiconductor film
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- 239000004065 semiconductor Substances 0.000 title abstract description 12
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 239000010409 thin film Substances 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000001312 dry etching Methods 0.000 claims abstract description 16
- 238000001039 wet etching Methods 0.000 claims abstract description 12
- 238000001723 curing Methods 0.000 claims abstract description 5
- 238000000016 photochemical curing Methods 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 239000003795 chemical substances by application Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 8
- 229920000642 polymer Polymers 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 239000007789 gas Substances 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체막 제조방법에 관한 것으로, 건식 및 습식식각법으로 절연막내의 접촉면을 형성하는 반도체막 제조방법에 있어서, 감광제 경화굽기를 170℃로 실시하고, 부피비 1:14를 갖는 CHF3+CF4가스를 이용하여 건식식각한 후 습식식각하므로써 1) 상기 공정 진행시 빈번히 야기되던 건식식각후의 폴리머의 다량발생 및 식각면의 거칠음 현상을 제거할 수 있으며, 2) 이로 인해 기존 습식식각시 유발되던 과소식각 및 접촉면의 불균일을 제거할 수 있고, 3) 상기 접촉면에 금속막 증착시 발생되던 접촉면의 저항 특성저하를 방지할 수 있는 고신뢰성의 반도체막을 실현할 수 있게 된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor film, wherein the method for manufacturing a semiconductor film in which dry and wet etching forms a contact surface in an insulating film, wherein the photocuring curing burner is performed at 170 ° C. and has a volume ratio of 1:14, CHF 3 + CF. By wet etching after using 4 gases, 1) it is possible to remove a large amount of polymer and the roughness of the etching surface after the dry etching, which is frequently caused during the process, and 2) due to the conventional wet etching Under-etching and nonuniformity of the contact surface can be eliminated, and 3) a highly reliable semiconductor film capable of preventing the resistance characteristics of the contact surface generated when the metal film is deposited on the contact surface can be realized.
Description
제1(a)도 내지 제1(e)도는 종래 기술에 따른 반도체막 제조공정을 도시한 공정수순도.1 (a) to 1 (e) are process flowcharts showing a semiconductor film manufacturing process according to the prior art.
제2(a)도 내지 제2(e)도는 본 발명에 따른 반도체막 제조공정을 도시한 공정수순도.2 (a) to 2 (e) are process flowcharts showing a semiconductor film manufacturing process according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 실리콘 기판 12 : 절연막10 silicon substrate 12 insulating film
14 : 감광제14 photosensitive agent
본 발명은 반도체막 제조방법에 관한 것으로, 특히 건식식각 및 습식식각에 의한 절연막내의 접촉면(contact) 형성시 야기되는 폴리머(polymer) 발생 및 식각면의 거칠음(roughness) 현상을 제거할 수 있는 반도체막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor film. In particular, a semiconductor film capable of eliminating polymers and roughness of an etching surface caused by formation of contacts in an insulating film by dry etching and wet etching. It relates to a manufacturing method.
종래, 일반적으로 사용되어 오던 건식 및 습식식각에 의한 절연막 내 접촉면 형성방법은 제1(a)도 내지 제1(e)도에 도시된 바와 같이 먼저 절연막(12)이 형성된 실리콘기판(10) 상에 원하는 패턴을 얻기 위하여 감광제(photoresist)(14)를 도포한 후 이를 사진식각공정(photolithography)으로 식각처리하여 제1(a)도에 도시된 바와 같이 상기 감광제(14)를 패터닝한다.Conventionally, a method of forming a contact surface in an insulating layer by dry and wet etching, which has been generally used, is performed on the silicon substrate 10 on which the insulating layer 12 is first formed, as shown in FIGS. 1 (a) to 1 (e). After the photoresist 14 is applied to obtain a desired pattern, the photoresist 14 is etched by photolithography to pattern the photoresist 14 as shown in FIG.
그후 제1(b)도에 도시된 바와 같이 상기 패터닝된 감광제(14)를 견고히하기 위하여 135℃에서 감광제 경화굽기를 실시하고, 이어서 상기 공정을 거친 실리콘 기판(10)을 건식식각하여 제1(c)도에 도시된 바와 같이 패터닝한다.Thereafter, as shown in FIG. 1 (b), to harden the patterned photoresist 14, a photosensitive curing hardening process is performed at 135 ° C., followed by dry etching of the silicon substrate 10 subjected to the above process. c) Patterning as shown in FIG.
그 다음 건식식각에 의해 패터닝된 상기 절연막 상의 잔존물(혹은 찌꺼기)을 제거하기 위하여 데스큠(descum) 공정을 실시하고, 이어서 습식식각을 실시하여 제1(e)도에 도시된 바와 같은 등방성 패턴을 형성한다.A descum process is then performed to remove residues (or debris) on the insulating film patterned by dry etching, followed by wet etching to obtain an isotropic pattern as shown in FIG. 1 (e). Form.
이후 제1(e)도에 도시된 바와 같이 상기 절연막(12) 상에 형성된 감광제 패턴(14)을 제거하여 절연막 형성 공정을 완료한다.Thereafter, as illustrated in FIG. 1E, the photoresist pattern 14 formed on the insulating film 12 is removed to complete the insulating film forming process.
그러나 상기와 같은 공정 및 제어조건을 이용하여 절연막을 형성할 경우에는 제1(c)도의 (A)부분에 도시된 바와 같이 건식식각후 다량의 폴리머 발생 및 식각면의 거칠음 현상이 발생하여 후속 공정인 습식식각 공정 진행시 과소식각 등과 같은 식각불량 현상이 발생할 뿐 아니라 이로 인해 접촉면의 불균일화가 유발되어 상기 패턴 상에 알루미늄 등과 같은 금속막을 증착할 경우, 접촉면의 저항(resistance) 특성이 저하되는 단점을 가지게 된다.However, when the insulating film is formed using the above-described process and control conditions, as shown in part (A) of FIG. 1 (c), a large amount of polymer is generated after the dry etching and roughness of the etching surface occurs. When the wet etching process is performed, not only an etching phenomena such as underetching, but also cause unevenness of the contact surface, and when a metal film such as aluminum is deposited on the pattern, the resistance property of the contact surface is degraded. Have.
이에 본 발명은 상기와 같은 단점을 개선하기 위하여 이루어진 것으로 감광제 경화굽기를 170℃에서 실시한 후 CHF3+CF4가스를 이용하여 건식식각하므로써 절연막내의 접촉면 형성시 발생되는 폴리머와 식각면의 거칠음 현상을 제거할 수 있도록 한 반도체막 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention was made to improve the above disadvantages, and after performing the photocuring curing burner at 170 ° C, dry etching was performed using CHF 3 + CF 4 gas to reduce the roughness of the polymer and the etching surface generated when forming the contact surface in the insulating film. It is an object of the present invention to provide a method for manufacturing a semiconductor film which can be removed.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체막 제조 방법은 절연막이 증착된 실리콘기판 상에 감광제를 도포한 후 사진식각 공정으로 원하는 감광제 패턴을 형성하는 단계와, 상기 감광제 패턴을 170℃에서 경화굽기 처리하는 단계와, 경화굽기 처리된 상기 감광제를 마스크로 CHF3+CF4가스를 이용하여 건식식각을 실시하는 단계와, 건식식각후 패터닝된 상기 절연막 상에 잔존하는 잔여물(혹은 찌꺼기)를 제거하기 위하여 데스큠 공정을 실시하는 단계와, 상기 패턴 상에 습식식각을 실시하는 단계 및, 상기 절연막 상에 패터닝된 감광제를 제거하는 단계로 이루어짐을 특징으로 한다.The semiconductor film manufacturing method according to the present invention for achieving the above object is the step of forming a desired photoresist pattern by a photolithography process after applying a photoresist on the silicon substrate on which the insulating film is deposited, the photoresist pattern at 170 ℃ Performing a hard burn process, performing dry etching using CHF 3 + CF 4 gas as a mask using the hard burn process, and residues (or residues) remaining on the patterned insulating layer after dry etching. And removing the patterned photoresist on the insulating film, performing a death process on the pattern, performing wet etching on the pattern, and removing the patterned photoresist on the insulating film.
상기 제조공정 결과, 건식식각후 야기되는 폴리머의 다량발생 및 식각면의 거칠음 현상을 방지할 수 있게 된다.As a result of the manufacturing process, it is possible to prevent the occurrence of a large amount of polymer and the roughness of the etching surface caused after dry etching.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2(a)도 내지 제2(e)도에는 본 발명에 따른 반도체막 제조공정을 도시한 공정수순도가 도시되어 있다.2 (a) to 2 (e) show a process flowchart showing a semiconductor film manufacturing process according to the present invention.
상기 도면에서 알수 있듯이 본 발명에 따른 반도체막 형성공정은 먼저, 제2(a)도에 도시된 바와 같이 종래와 동일한 방법으로 실리콘기판(10) 상에 원하는 패턴을 얻기 위하여 감광제(photoresist)(14)를 도포한 후 이를 사진식각공정(photolithography)으로 식각처리하여 제2(a)도에 도시된 바와 같이 상기 감광제(14)를 패터닝한다.As can be seen from the figure, the process of forming a semiconductor film according to the present invention is first performed by a photoresist 14 to obtain a desired pattern on the silicon substrate 10 in the same manner as in the prior art as shown in FIG. ) Is then etched by photolithography to pattern the photoresist 14 as shown in FIG.
그후 제2(b)도에 도시된 바와 같이 패터닝된 상기 감광제(14)를 견고히하기 위하여 170℃에서 오븐 베이크(oven bake) 또는 핫 플레이트(hot plate)를 이용하여 감광제 경화굽기를 실시하고, 이어서 상기 공정을 거친 실리콘 기판(10)을 부피비 1:14를 갖는 CHF3+CF4가스로 건식식각하여 제2(c)도에 도시된 바와 같이 패터닝한다.Thereafter, curing of the photoresist is performed using an oven bake or a hot plate at 170 ° C. to solidify the patterned photoresist 14 as shown in FIG. 2 (b). The silicon substrate 10 subjected to the above process is dry etched with CHF 3 + CF 4 gas having a volume ratio of 1:14 and patterned as shown in FIG. 2 (c).
그 다음 건식식각에 의해 패터닝된 상기 절연막 상의 잔존물(혹은 찌꺼기)을 제거하기 위하여 데스큠(descum) 공정을 실시하고, 이어서 습식식각을 실시하여 제2(d)도에 도시된 바와 같은 패턴을 형성한다.A descum process is then performed to remove residues (or debris) on the insulating film patterned by dry etching, followed by wet etching to form a pattern as shown in FIG. 2 (d). do.
이후 제2(e)도에 도시된 바와 같이 상기 절연막(12) 상에 형성된 감광제 패턴(14)을 제거하여 절연막 형성 공정을 완료한다.Thereafter, as illustrated in FIG. 2E, the photoresist pattern 14 formed on the insulating film 12 is removed to complete the insulating film forming process.
상술한 바와 같이 본 발명에 의하면, 1) 건식 및 습식식각으로 절연막내의 접촉면을 형성하는 공정 진행시 빈번히 야기되던 건식식각후의 폴리머의 다량발생 및 식각면의 거칠음 현상을 제거할 수 있으며, 2) 이로 인해 기존 습식식각시 유발되던 과소식각 및 접촉면의 불균일을 제거할 수 있고, 3) 상기 접촉면에 금속막 증착시 발생되던 접촉면의 저항 특성저하를 방지할 수 있게 된다.As described above, according to the present invention, 1) it is possible to eliminate a large amount of polymer after dry etching and roughness of the etching surface, which are frequently caused during the process of forming the contact surface in the insulating film by dry and wet etching. Due to this, it is possible to eliminate underetching and nonuniformity of the contact surface caused by conventional wet etching, and 3) to prevent a decrease in resistance characteristics of the contact surface generated when the metal film is deposited on the contact surface.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950007981A KR0152920B1 (en) | 1995-04-06 | 1995-04-06 | Semiconductor thin film manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950007981A KR0152920B1 (en) | 1995-04-06 | 1995-04-06 | Semiconductor thin film manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| KR960039164A KR960039164A (en) | 1996-11-21 |
| KR0152920B1 true KR0152920B1 (en) | 1998-12-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950007981A KR0152920B1 (en) | 1995-04-06 | 1995-04-06 | Semiconductor thin film manufacturing method |
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| US20160064239A1 (en) * | 2014-08-28 | 2016-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for Integrated Circuit Patterning |
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1995
- 1995-04-06 KR KR1019950007981A patent/KR0152920B1/en not_active IP Right Cessation
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| KR960039164A (en) | 1996-11-21 |
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