KR0152845B1 - Cordward distinguishing apparatus of digital vcr - Google Patents

Abstract

The present invention relates to an apparatus for determining a codeword of a digital VLC. The present invention relates to a codeword discrimination apparatus of a digital VLC. The present invention relates to a codeword coder for determining the length of a codeword at an output of an error correction decoder. The present invention is configured to decode the original data by obtaining a word and its code length. The present invention provides an overhead of hardware by simply implementing hardware for detecting a code word and determining the length of the code word using characteristics of the codeword. (over-head) can be reduced, and in particular, the data before compression can be easily obtained by obtaining and decoding the original codeword and the code length from the data of the compressed bit stream.

Description

Digital VLC's Codeword Discrimination Device

1 is a block diagram of a typical data compression decompression device.

2 is a block diagram of a codeword discrimination apparatus of the present invention.

3 is an exemplary view showing a variable length code table.

FIG. 4 is an exemplary table showing upper bits of codeword lengths in FIG.

5 is a signal flow diagram for codeword length determination of the present invention.

* Explanation of symbols for main parts of the drawings

101 variable length encoder 102 formatter

103: error correction encoder 104: modulator

106: demodulator 107: error correction decoder

108: codeword detector 109: formatter

110 variable length decoder 201 first-in first-out memory (FIFO)

202: bit stream storage unit 203: multiplexer (MUX)

204: word length discrimination unit 205: codeword storage unit

206: length data storage unit 207: start bit determination unit

208: start bit storage unit

The present invention relates to the compression and decompression of data of a digital VRL. In particular, in a variable length code decoding, a digital VLC code for reproducing original data by determining a codeword and a code length using characteristics of a codeword. It relates to a word discrimination apparatus.

A typical digital data compression stretching device is constructed as shown in FIG.

In the data compression and decompression apparatus, when the image data is to be recorded in a table, the variable length encoder 101 converts each input code into the same length code by entropy encoding and encodes the encoded data. Will be output to the formatter 102.

In this case, when the frequency of the target signal is not uniform, the entropy coding is applied to a variable length coding scheme to assign a short length code to a code having a high frequency and a long length code to a code with a low frequency. By assigning all codes to the same length.

At this time, the formatter 102 converts the encoded data output from the variable length protector 101 into a predetermined form suitable for the system recording method, and the error correction encoder 103 receiving the predetermined type of data receives the predetermined form. Code for error correction is added during reproduction of the data.

As a result, the modulator 104 modulates the coded data output from the error correction coder 103 so as to conform to the recording characteristics and records it on the tape 105.

In contrast, in the case of reproducing the recording data of the tape, when the recording data is detected by the tape 105, the demodulator 106 demodulates the original signal from the modulated high frequency band signal and receives the demodulated data. ) Extracts an error correction code added by the error correction encoder 103 at the time of recording to correct an error occurring in the reproduction process.

At this time, the codeword detector 108 detects the codeword and the length data of the codeword from the compressed data of the bit stream output from the error correction decoder 107, and the formatter 109 is the codeword detector 108 Logical operation of the coding data of is converted into the original coding data of a certain format.

Accordingly, when the formatter 109 outputs the original data of a certain format as a bit stream, the variable length decoder 110 decodes the corresponding code word according to the length data of the codeword to reproduce the image data.

SUMMARY OF THE INVENTION An object of the present invention is to provide a codeword discrimination apparatus of a digital VRL configured to reproduce the original data by obtaining the codeword and its code length from a compressed bit stream by configuring the codeword detector with simple hardware. .

In order to achieve the above object, the present invention provides a first-in first-out memory means for sequentially storing compressed data in a predetermined length, bit stream storage means for loading and storing data of the first-in first-out memory means in predetermined length units, and this bit. A multiplexer means for selecting data loaded in the stream storage means by a predetermined bit pointer by a start bit pointer, a start bit storage means for outputting a start bit pointer to the multiplexer means, and a bit data selected by the multiplexer means Word length discriminating means for discriminating the length of the corresponding codeword in comparison with data, and start bits for summing up the code length data of the word length discriminating means and the start bit pointer of the start bit storing means and outputting them to the start bit storing means. Determining means and code length of said codeword discriminating means Length data storage means for loading and outputting the codeword when outputting the corresponding codeword, codeword storage means for temporarily storing the codeword selected by the multiplexer means, timing for calculating the synchronization signal and the start pointer data to control the respective means. It consists of control means.

Hereinafter, the present invention will be described in detail with reference to the drawings.

2 is a block diagram of the codeword discrimination apparatus of the present invention, as shown in FIG. 1, which sequentially stores compressed data by a predetermined length by the write clock WCLK and outputs the data stored by the read clock RCLK. A bit stream storage unit 202 for loading and storing the first-in-first-out memory 201, the data in the first-in-first-out memory 201 by a predetermined length unit, and a start bit pointer for the data loaded in the bit stream storage unit 202. A multiplexer 203 for selecting predetermined bits by means of a word, a word length determination unit 204 for determining the length of a corresponding codeword by comparing the upper predetermined bits of the bit data selected by the multiplexer 203 with the stored bit data; The length data storage unit 206 for temporarily storing the length data of the word length determination unit 204 and the length data of the word length determination unit 204 are outputted to the multiplexer 203. The start bit determiner 207 determines the start bit pointer for the selection of the next bit data by summing with the start bit pointer, and the multiplexer 203 after temporarily storing the start bit pointer of the start bit determiner 207. The start bit storage unit 208 for outputting the data stream), the code word storage unit 205 for temporarily storing the bit data selected by the multiplexer 203 and outputting the code data as a codeword, the synchronization signal SYNC and the start bit pointer. (SP) logical operation to output a write clock (WCLk) read clock (RCLK) to the first-in first-out memory 201, the bit stream storage unit 202, codeword storage unit 205, length data storage unit ( 206 and a timing control unit 209 for outputting a load signal LOAD to the start bit storage unit 208.

The bit stream storage unit 202 is composed of 8-bit registers REG1 to REG3 to store 24-bit data. The reason why the bit stream storage unit 202 is 24 bits is that the maximum size of the codeword is 16 bits. .

The start bit determiner 207 is configured with an adder.

Referring to the operation and effect of the present invention configured as described above are as follows.

First, when the compressed data whose error is corrected by the error correction tree 107 is input to the codeword detector 108 by the reproduction operation of the recording data, the timing controller 209 causes the synchronization signal SYNC and the start bit pointer SP. ), The write clock WCLK, the read clock RCLK, and the load signal LOAD are outputted.

At this time, the first-in first-out memory 201 stores compressed data, which is a bit stream, in units of one word (= 8 bits) according to the write clock (WCLK) of the timing controller 202, and stores the stored data in accordance with the read clock (RCLK). It will output word by word.

Accordingly, the bit stream storage unit 202 stores data output from the first-in first-out memory 201 in units of 8 bits in accordance with the load signal LOAD of the timing controller 209 in the registers REG1 to REG3, respectively. It will store bits of data.

The reason why the bit stream storage unit 202 is configured to be 24 bits is that the maximum length of the codeword is 16 bits.

Thereafter, when the start bit storage unit 208 outputs a start bit pointer SP indicating a start bit to be read among 24 bits of data stored in the bit stream storage unit 202, the multiplexer 203 outputs the start bit pointer ( According to SP), the bit stream storage unit 202 selects and outputs 16 bits of data from the start bit.

At this time, when the multiplexer 203 outputs 16 bits of data selected from the bit stream storage unit 202, the word length determination unit 204 uses a fourth diagram for determining the length of the prestored codeword. The length of the current codeword is determined by comparing with the same bit data.

Here, the word length determining unit 204 extracts a code having a common length for each codeword having a different length from variable-length code data as shown in FIG. 3 and uses the common code to determine the length data of the corresponding code. As shown in FIG. 4, the comparison word is created and stored, and the length of the codeword is determined by comparing the upper 8 bits of the 16 bits selected by the multiplexer 203 with the comparison bits and the exclusive oaring.

For example, if a bit having a '1101 0000' is input, the word length determining unit 204 outputs a '1000' value by determining that the code length is 8 bits by comparing the data of the table shown in FIG.

Accordingly, when the word length determination unit 204 determines the length data for the codeword selected by the multiplexer 203, the length data storage unit 206 stores the start length determination unit 207. After the 4-bit length data of 204 is added to the start bit pointer SP of the start bit storage unit 208, the start bit pointer SP for determining the start position of the next data is calculated. Output to 208.

The codeword storage unit 205 stores data selected and output by the multiplexer 203 by the start bit pointer SP of the start bit storage unit 208 and then outputs the codeword.

Thereafter, when the multiplexer 203 selects 16 bits among the storage bits of the bit stream storage unit 202 by the start bit pointer SP of the start bit storage unit 208, the word length determination unit 204 determines the corresponding code. The length of the word is determined and the start bit determination unit 207 repeats the operation of determining the start position for selecting the next codeword based on the determined length data.

At this time, the timing controller 209 detects the output SP of the start bit storage unit 208 and determines whether to load the stored data of the first-in-first-out memory 201 into the bit stream storage unit 202. .

Accordingly, when the timing controller 209 outputs the read clock RCLK and the load signal LOAD by determining that the word data should be loaded into the bit stream storage unit 202, the data output from the first-in-first-out memory 201 is output. 8 bits are stored in the registers REG1 to REG3 of the bit stream storage unit 202.

Accordingly, when the codeword and the length data of the codeword are output from the codeword detector 108 by repeating the above operation, the deformatter 109 restores the data of a predetermined format through a logical operation and performs variable length decoding. By outputting to the device 110, the video is reproduced by decoding the corresponding code word.

On the other hand, the above operation is performed by a signal flow diagram as shown in FIG.

That is, the timing controller 209 detecting the start bit pointer SP of the start bit storage unit 208 determines whether to load the codeword into the bit stream storage unit 202. When 202 stores the output data of the first-in-first-out memory 202, the multiplexer 203 causes the multiplexer 203 to use 16 bits of the storage bits of the bit stream storage unit 202 by the start bit pointer SP of the start bit storage unit 208. Will be selected.

At this time, the word length determination unit 204 that detects the upper 8 bits of the output of the multiplexer 203 determines the length of the corresponding codeword in comparison with the table created as shown in FIG. 4 and starts the bit determination unit that detects the length data. 207 adds up to the output SP of the start bit storage unit 208 to determine the start position of the next code word.

Accordingly, the start position storage unit 208 stores the output of the start position determination unit 207 and outputs the output to the multiplexer 203 at the time of input of the next codeword, and the codeword storage unit 205 outputs the multiplexer 203. The length data storage unit 206 stores the output data of the word length determination unit 204 and outputs the length data of the corresponding codeword when storing the 16-bit data selected in " .

As described in detail above, the present invention can reduce hardware overhead by simply implementing hardware for detecting a code word and determining the length of the code word using characteristics of the code word. It works.

In particular, the present invention has an effect of easily obtaining the data before compression by obtaining the original codeword and the code length from the data of the compressed bit stream and decoding them.

Claims (4)

In a digital VLC decoded by an error correcting decoder and corrected by an error correcting decoder, and then decoded by a variable length decoder, compressed data is stored by a predetermined length by a write clock (WCLK) for reading. First-in first-out memory means for sequentially outputting by the clock RCLK, bit stream storage means for storing the output bits of the first-in first-out memory means by the load signal LOAD, and the bit by the start bit pointer SP. A multiplexer means for selecting bits of a predetermined length among the storage bits of the stream storage means, a codeword storage means for storing the output bits of the multiplexer means by a load signal LOAD and outputting them as a codeword, starting at the multiplexer means A start bit storage means for outputting a bit pointer SP, and a smallest value from the higher of the output bits of the multiplexer means; Word length determination means for determining the length of the codeword by selecting a bit of the length and comparing it with a previously stored table, length data storage means for storing the length data of the word length determination means by a load signal LOAD; Determining the start position of the next codeword by adding the length data of the word length determining means to the start bit pointer SP of the start bit storage means and determining the start bit for outputting the start bit data to the start bit storage means. Means for generating a write clock WCLK and a read clock RCLK in the first-in first-out memory means in accordance with a synchronization signal SYNC, and in accordance with the start bit pointer SP of the start bit storage means. Number of timing controls for generating a load signal LOAD to the codeword storage means, the length data storage means, and the start bit storage means. A digital word code discrimination apparatus characterized by comprising a stage. The apparatus of claim 1, wherein the bit stream storing means comprises three registers (REG1 to REG3) for loading the output bits of the first-in first-out memory means by a predetermined bit. The digital word codeword of claim 1, wherein the word length discriminating means determines the length of the corresponding code by exclusively arranging bits of a predetermined length from the most significant of the outputs of the multiplexer means with the prestored bit data. Discrimination device. 2. The apparatus of claim 1, wherein the start bit determining means is an adder.