JPH04137823A - Variable length encoder and decoder - Google Patents

Abstract

PURPOSE:To improve the compression efficiency due to variable length coding and to reduce the redundancy of a data by providing a coding compression circuit applying variable length coding to a data after a periodic signal is inserted to the data and a coding expansion circuit decoding the compressed data. CONSTITUTION:The code compression circuit 3 inserts a periodic signal to a data just before variable length coding for compression is applied to the data. A coding expansion circuit 9 uses an error flag from an error correction decoder 8 and a data checking circuit 25 discriminates that the data from a decoder 24 is not adequate, the decoded data is replaced and subjected to variable length coding and the result is fed to the decoder 24. Then the operation of discriminating the adequacy of the data is repeated till the data is discriminated adequate. Thus, the deterioration in the compression efficiency due to variable length coding is prevented and the reduction in the redundancy of data is attained.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a variable length encoding and decoding device, and is capable of correcting errors even when decoding a variable length code containing an error to ensure reliable operation. The present invention relates to a variable length encoding and decoding device capable of decoding data.

(Prior art) Coded signals such as image data obtained by quantizing and sampling audio signals and video signals in televisions, facsimiles, etc. have redundancy, and as a measure to improve this, a data compression method using variable length coding is used. It will be done.

When variable-length encoding a code signal, if there is an error in the data during recording or playback, it cannot be decoded as it is, so a header with a fixed period (hereinafter referred to as a periodic signal) is added to the data after variable-length encoding. Was. At the time of decoding, the start position of variable length data was determined based on the periodic signal information and decoded.

In such conventional technology, if a periodic signal is added after variable-length encoding, the compression efficiency due to the variable-length code will deteriorate, and if only a periodic signal is added to the data,
You can recover after an error, but you cannot restore the data that had the error. In response to this, even if an error correction circuit is provided before decoding, the errors missed by the error correction circuit will be decoded as-is, resulting in the erroneous data being used as is, making it difficult to recover quickly from there. In order to achieve this, it is necessary to shorten the insertion period of the periodic signal. This increases data redundancy.

(Problems to be Solved by the Invention) In the conventional technology described above, adding a periodic signal after encoding causes deterioration of compression efficiency due to variable length codes. Furthermore, it is not possible to restore data with errors by simply adding a periodic signal to the data; in order to quickly recover from an error, it is necessary to shorten the period of the periodic signal. data redundancy increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a variable length encoding and decoding device that can eliminate the above problems, improve compression efficiency using variable length codes, and reduce data redundancy.

[Refinement of the invention] (Means for solving the problem) The present invention performs data compression by inserting a periodic signal into original data and then variable-length encoding the data, and outputting the data as variable-length encoded data. an encoding compression circuit, a decoder for decoding the variable length encoded data, and determining the validity of the data decoded by the decoder based on the periodic signal;
A data check circuit that directly outputs the decoded data when the data is determined to be valid, and a data check circuit that directly outputs the decoded data when the data is determined to be invalid, replaces the decoded data, and encodes the data using variable length encoding. and circuit means for supplying the decoder.

(Operation) According to such refinement, since a periodic signal is added before variable length encoding, it is possible to improve the compression efficiency by variable length encoding. Furthermore, when the data check circuit determines that the decoded data from the decoder is not valid, the data is replaced, variable-length encoded, and supplied to the decoder, and the validity of the data is determined again. The operation is repeated until the decoded data is determined to be valid, resulting in accurate data. Therefore, the period of the periodic signal can be set long, and the redundancy of variable length encoded data can be reduced.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a variable length encoding and decoding device according to the present invention. This embodiment is applied to a digital video tape recorder (hereinafter referred to as digital VTR).

A video signal is input to an input signal processing circuit 2 from an input terminal 1. This input video signal is processed directly in the case of a digital signal, or after A/D conversion in the case of an analog signal, and is processed as a digital video signal in one frame in the input signal processing circuit 2. is stored in the buffer memory of The signal stored in this buffer memory is divided into blocks for compression and input to the encoding and compression circuit 3. In such block division, for example, when one frame of data is converted into 768×488 pieces of digital data, 8×8 blocks are generated.

The encoding and compression circuit 3 performs encoding to efficiently remove redundant components of the input block. At this time, the encoding method may be, for example, discrete cosine transform,
A compression method is used in which the results of coding such as Hadamard transform and Huffman coding are output in variable length. moreover,
The encoding compression circuit 3 inserts a periodic signal immediately before variable length encoding for compression. Here, after discrete cosine transformation for each block, a periodic signal is inserted every 64 blocks. It also performs processing to arrange the data into a matrix for error correction.

As a result of being arranged in a matrix, the variable length encoded data has a fixed length and is output from the encoding compression circuit 3, and is input to the error correction encoder 4. The error correction encoder 4 adds an error check code to the data from the encoding compression circuit N3. The data to which the error check code has been added is modulated in the recording/reproducing circuit 5 to match the characteristics of the recording/reproducing system, and is recorded onto the magnetic tape 7 by the recording/reproducing head 6.

Data recorded on the magnetic tape 7 is read out by a recording/reproducing head 6, demodulated by a recording/reproducing circuit 5, and then input to an error correction decoder 8.

The error correction decoder 8 performs error correction or error detection on the demodulated data using the error check code. The result of error detection is set as an error flag.
The signal is input to the encoding/expanding circuit 9.

The encoding/expanding circuit 9 performs error correction, which will be described later, using the error flag from the error correction decoder 8, restores the compressed data, and outputs it as a digital signal. The digital signal from the encoding/expansion circuit 9 is sent to the output signal processing circuit 1.
0, and output terminal 1 as a video signal.
Output from 1.

In addition, when outputting the video signal as a digital signal,
This D/A conversion process is not necessary.

FIG. 2 is a block diagram showing the configuration of the encoding/expanding circuit 9 of FIG. 1.

Data from the error correction decoder 8 is input to the buffer memory from the input terminal 21 and written therein.

Further, the error flag from the error correction decoder 8 is inputted to the buffer memory 23 from the input terminal 22 and written therein.

The data written in the buffer memory 23 is read from the frame sync position, decoded by the decoder 24, and the data is checked! Supplied to @25.

On the other hand, the error flag written in the buffer memory 23 is read out at a timing corresponding to the data from the buffer memory 23 and is supplied to the data check circuit 25.

The data check circuit 25 checks whether the data in the buffer memory 23 contains specific data that matches the original signal, and also checks whether an error flag is attached. As a result of checking, if the specific data is not located at the original position or if an error flag is attached from the error correction decoder 8, the data modification circuit 26 modifies the variable length code data. Various error correction methods can be considered at this time, but in this case, for example, when one byte of data has an error flag attached, it is changed to 256 different data, and the variable length code data after the change is sent to the decoder 2.
4, the data is decoded and variable-length coded, and the data check circuit 25
Adopt one that displays specific data in the correct position. Variable length code data in which specific data appears in the correct position is supplied to the buffer memory 27 and written therein. The buffer memory 27 outputs the written variable-length code data to an output terminal 28 while aligning the time axis. The output terminal 28 is connected to the output signal processing circuit 10 shown in FIG.
0.

The operation of such an embodiment will be explained with reference to FIGS. 3 and 4.

FIG. 3 is an explanatory diagram showing the state of encoding in the encoding and compression circuit 3 of FIG. 1, and FIG. ) shows periodic signal additional data, and FIG. 3(c) shows variable length encoded data.

In FIG. 3, the original data shown in FIG. 3(a) is fixed length PCM data. In this data string of original data, periodic signals are inserted every 64 times as shown in FIG. 3(b). After this, the data into which the periodic signal has been inserted contains the third
As shown in Figure (c), variable length encoding is performed.

FIG. 4 is an explanatory diagram showing an example of output data from the error correction decoder 8 in FIG. 1. FIG. 4(a) shows a frame sync signal, FIG. Figure 4 (
c) shows an error flag.

In Figure 4, the sink shown in Figure 4(a) is 1 of the image.
This is a frame sync signal that is entered at the beginning of the frame, and the data written in the buffer memory 23 (see FIG. 2) starts reading out the variable length code data shown in FIG. 4(b) by the frame sync signal. . The error flag shown in FIG. 4(c) is attached to each byte and is supplied to the data check circuit 25.

In such an embodiment, since a periodic signal is added to data before variable length encoding, deterioration of compression efficiency due to variable length encoding can be prevented. Data check circuit 25
When the data from the decoder 24 is determined to be invalid, the decoded data is replaced, variable-length encoded, and supplied to the decoder 24, and the operation of determining the validity of the data again is performed. It is repeated until it is determined to be valid, so accurate data can be obtained. Therefore, the period of the periodic signal can be set long, and data redundancy can be reduced.

Incidentally, the variable length encoding and decoding device of the present invention is applicable to digital V
Recording and reproducing equipment for not only TR but also audio signals.

It may also be applied to another device such as a facsimile.

[Effects of the Invention] As described above, according to the present invention, deterioration in compression efficiency due to variable length encoding can be prevented, and data redundancy can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the variable length encoding and decoding device according to the present invention, FIG. 2 is a block diagram showing the configuration of the encoding/decompression circuit shown in FIG. 1, and FIG. 3 is the block diagram shown in FIG. 1. FIG. 4 is an explanatory diagram showing an example of output data from the error correction decoder of FIG. 1. FIG. 2... Input signal processing circuit, 3... Encoding compression circuit, 4
. . . error correction encoding circuit, 8 . . . error correction decoder, 9 . . . encoding expansion circuit, 1
0... Output signal processing circuit, 24... Decoder, 25...
- Data check circuit, 26... data correction circuit.

Claims (1)

[Claims] An encoding compression circuit that performs data compression by inserting a periodic signal into original data and subjecting it to variable length encoding and outputting it as variable length encoded data; a decoder for decoding, a data check circuit that determines the validity of the data decoded by the decoder based on the periodic signal, and directly outputs the decoded data when it is determined to be valid; and the data check circuit. A variable length encoding and decoding device comprising: a data modification circuit that replaces the decoded data when it is determined to be invalid, encodes the data in variable length, and supplies the encoded data to the decoder.