JPH0738893A - Digital television picture transmission or storage device, video recorder and memory medium - Google Patents

Abstract

PURPOSE: To transmit a digital TV image with high reliability and also to decode the image by means of a simple receiver by storing the start address of the extra data on a channel block of a format pre-stage at a prescribed position of the block. CONSTITUTION: The analog image signals are sampled by an A/D converter 21 with sampling frequency (fs) and applied to a DCT 22 to obtain the coefficient blocks. The series of the obtained coefficients are applied to a quantization circuit 23 and then to a VLC circuit 24 to perform the variable length coding of the coefficient blocks to convert them into the variable length code words. The code words of the coefficient blocks construct a data block which is applied to a format circuit 25. The circuit 25 having a buffer memory and two other memories stores the extra data on data blocks DB in other channel blocks CB, stores the code word of the EDB obtained by filling the deficient parts of the data stored in the blocks CB with the extra data on other blocks DB in the corresponding block CB of fixed length, and also stores the start address of the extra data stored in the block CB at a prescribed position of the CB.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for transmitting or storing digital television images and a device for receiving digital television images. The invention also relates to a storage medium on which the digital image is stored.

[0002]

2. Description of the Prior Art Two-dimensional block image transformations, for example 8 × 8 pixels, are commonly used for the digital transmission and storage of television images. A block of coefficients is obtained by a transform, such as the Discrete Cosine Transform (DCT), the number of which is equal to the number of pixels in each block. The DC coefficient, which is one of these coefficients, represents the average luminance or color tone of the block. The other coefficient is the AC coefficient. Each of them represents the area in which a given image detail is represented.

The amount of bits per image is not reduced by the conversion. Therefore, the digital image signal is compressed before transmission or storage. This compression is obtained by quantizing the coefficients after scanning (serializing) the signals and subjecting them to variable length coding. Quantization causes many coefficients to have the value zero. In variable length coding, this set of zero coefficients is efficiently coded. The coding of a series of zero coefficients at the end of a block can even be unnecessary. The end of the block is the end of block (E
This is because it is marked by the OB) code.

In this way, each block of pixels is converted into a block of codewords. Such a block with a variable number of variable length codewords is hereinafter defined as a data block. Transmission of variable length codewords instead of pixels or coefficients offers the potential for significant bitrate reduction. This is offset by the fact that the transmission of codewords is sensitive to transmission errors.
Transmission errors generally result in loss of synchronization at the receiving end.
The subsequent codeword as well as that codeword are no longer recognized.

In order to reduce the loss of synchronization, US Pat.
No. 4,907,101 describes a device comprising formatting means for accommodating codewords of data blocks in corresponding channel blocks of fixed length. Such channel blocks can be searched in case of transmission errors. Because it is transmitted at a known point in time or it is stored in a fixed position on the storage medium (magnetic tape, disk). Further, the channel block can be properly protected by the synchronization word, the identification word and the protection bit.

The known device accommodates as many codewords of each data block as the corresponding channel block. The surplus data is accommodated in another channel block until the space of the channel block is filled.
If space remains, the channel block also contains the surplus data of other data blocks. The boundary between the data of the corresponding data block and the surplus data of another data block is constituted by the above-mentioned EOB code.

As described in the above mentioned patent specifications, the receiver comprises two decoders. The first decoder is configured to receive the channel block and recognize the presence of its EOB code. The decoder separates the received data stream into corresponding data blocks and surplus data. The second decoder receives the data blocks and ensures their complete decoding. If the size of the channel block exceeds the limit during the decoding of the data block, the data block is succinct with the separation surplus data until the EOB code is recognized.

The known device has the drawback that the first decoder described above has a complex structure and requires a large chip surface. In fact, detection of the EOB code requires at least knowledge of the length of the preceding codeword. The complexity of such an EOB detector is comparable to that of the second decoder, the full variable length decoder. The known device therefore requires two complex decoders.

Another drawback of the known device is the fact that a corresponding channel block is formed for each individual data block. The desired protection and identification of a channel block with synchronization words, identification words and guard bits requires a significant bit overhead.

[0010]

SUMMARY OF THE INVENTION It is an object of the invention to provide a device for transmitting or storing television images so that the images can be reliably transmitted and decoded by a relatively simple receiver.

[0011]

To this end, in the device according to the invention, the formatting means are arranged so that the starting address of the surplus data in a channel block is accommodated in a predetermined position of said channel block. It is characterized by that. The boundary between the data of the corresponding data block and the surplus data of the other data block is now obtained at the receiver end by a simple downcount of bits. Variable length codeword length decoding and EOB detection can be eliminated. The reliability of the separation is not affected by the bit error of the variable length codeword, since the starting address is contained in a predetermined position of the channel block.

Another specific example of the apparatus is that the formatting means does not transmit the start address when there is no surplus data in the channel block, and there is no surplus data in another predetermined position of the channel block. Is configured to accommodate a status code representing. The transmission of the status code requires extra space (in principle one bit per channel block), but in practical experiments this often happens (multi-bit)
It has been proven to be well offset by the redundancy of the starting address. If the channel block does not have any extra data, the space occupied by the starting address is used for transmitting codewords.

The starting address is preferably represented by an integer fixed word length, eg 8 bits. The starting address then occupies only a few bits, which also simplifies the required circuitry for separating the data stream into corresponding and redundant data. The possible space between the corresponding data block and the surplus data is filled with dummy bit sequences. The start of a variable length codeword longer than the above space can be used for this purpose, and no separate definition of the dummy bit sequence is required.

Another embodiment of the apparatus is arranged in which the formatting means are further arranged to accommodate selected codewords of at least two data blocks in corresponding consecutive sections of one channel block. . On the one hand, this results in a reduction of overhead information (sync words, identifiers and guard bits). This is because a channel block is now formed for every group of at least two data blocks. It further ensures that each channel block contains at least a selected codeword of the corresponding data block, eg the codeword of each data block representing the DC coefficient and the most significant AC coefficient.

When a group of data blocks does not fit perfectly into a channel block and therefore some of the codewords are accommodated in other channel blocks in the form of extra data,
This extra data is always related to the less significant AC coefficients. The selected codeword of each data block can be recovered by simple down-counting of bits without variable length decoding and thus in a reliable manner. Even in the trick mode of a video recorder where the head scan is only a portion of the track, the predetermined minimum image quality of the constellation of blocks can be reconstructed for each channel block read.

It should be noted that the accommodation of selected codewords of data blocks in the block section is also proposed in the non-published European patent application EP-A 0 578 308. In the device described in this application, each channel block comprises redundant data, even if the group of data blocks fit perfectly in the channel block. The start address of the surplus data is not transmitted separately but is formed by the end of the last block section of the channel block.

The formatting means are preferably arranged to accommodate a length code in a predetermined position of the channel block of each channel block section, the length code indicating the length of this block section. This gives the possibility of determining for each individual data block the number of selected codewords required for the lowest image quality. The length of the block section of the channel block is adapted to it. The exact length of each block section is easily transmitted. However, in a device where data blocks are classified for image energy content,
Preferably, the length code is composed of classes of data blocks.

In any case, since the class is sent,
The transmission of the length code does not require any extra transmission space or storage space. The length code preferably represents an integer fixed word length, for example 8 bits. The possible space in the final block section of the channel block can be filled with dummy bit strings, preferably by the beginning of a variable length codeword that is longer than the space.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Overall Structure] The present invention will be described in detail with reference to the video recorder shown in FIG. In this figure, the device for transmitting or storing television signals is constituted by the coding mechanism 2 and the device for receiving television signals is constituted by the decoding mechanism 8. The encoding mechanism operates from the image signal source 1 to the analog image signal x (
t), and through the modulation circuit 3 the write head 4
To provide a serial channel bitstream z _j which is recorded on the magnetic tape 5. A read head 6 is present for restoring the original image signal, which converts the information on the magnetic tape into an electrical signal, which after demodulation in a demodulation circuit 7 is applied to the input of a decoding mechanism 8. resulting in channel bit stream z _'j being. The output of the decoding mechanism supplies the analog image signal x '(t) applied to the monitor 9.

[Coding Mechanism] In the coding mechanism 2, the analog image signal x (t) is sampled by the A / D converter 21 at an appropriate sampling frequency fs. The sampling frequency is, for example, 13.5 MHz for the luminance signal Y and 6.75 MHz for the color difference signals U and V. The sampling operation yields an 8-bit image signal sample s (n) for each pixel. These image signal samples are subsequently applied to a forward two-dimensional discrete cosine transformer (DCT) 22. A large number of examples of such converters are described in the literature, for example in European Patent Application EP 0 286 184, and in this respect are therefore shown in FIG. 2A for each sub-image of 8 × 8 pixels. It suffices to note that the transformed coefficient blocks are supplied by the transformer.

The coefficients of such a block are denoted by y _{i, k} , where i, k = 0,1,2, ... 7. The coefficient y _0,0 represents the DC coefficient and it is a measure of the average luminance Y or chromaticity U, V of the sub-image. The other coefficients y _{i, k with} i, k ≠ 0 are AC coefficients. This coefficient is read continuously by the DC coefficient y _0,0 . The sequence is indicated by the arrow in FIG. 2A and for this purpose the address word AD (
i, k) and a control circuit for applying it to the converter 22
Determined by 26.

The coefficient sequence thus obtained is applied to the quantization circuit 23. This circuit performs a quantization operation on the coefficients y _{i, k} , so that the quantized coefficients ^ y _{i, k} (^ is above the letter in the figure, the same below) are obtained for each coefficient y _{i, k} . To be In general, quantization depends on the position of the coefficient in the coefficient block. For this purpose, the quantizer circuit 23 not only receives the coefficients, but also the corresponding address word AD (
i, k) is also received. Since many AC coefficients have small values, many quantized coefficients ^ y _{i, k} have the value zero. In this regard, it is common practice to define these coefficients as zero and non-zero coefficients. Quantization coefficient ^
The columns of y _{i, k} are shown in FIG. 2B.

The usual goal is to make the quantization dependent on the extent to which the sub-image contains image detail. The amount of image detail is determined by the values of the AC coefficients and the spatial frequencies they represent. An example of a quantizer circuit 23, the quantisation of which depends on the extent of image detail, is described in US Pat. No. 4,398,217. Here, the AC coefficients of the coefficient block are compared to corresponding coefficients of a number of predetermined reference blocks, each of which represents an image detail class.

The reference block corresponding to the maximum determines which image detail class is assigned to that coefficient block. The AC coefficients of the block are quantized depending on the class thus determined. The image detail class is sent to the decoding mechanism in the form of a classification code C. 8x8
C has a large value because there are many image details in the corresponding sub-image of the pixel. C is assumed to be a 2-bit number in the future, where C = 0 corresponds to the smallest image detail and C = 3 corresponds to the largest image detail.

The quantized coefficients ^ y _{i, k} are subsequently applied to a variable length coding (VLC) circuit 24 which produces a variable length code for each coefficient block of 64 quantized coefficients ^ y _{i, k.} And convert them into a series of variable length codewords. In addition, the VLC coding circuit provides a length LEN for each codeword. A possible embodiment of the VLC coding circuit 24 is described in EP 0 260 748. In this embodiment, the unambiguous codeword produces each non-zero coefficient with the immediately following or preceding zero coefficient. The VLC coding circuit also receives the classification code C from the quantization circuit 23 and sends this code as a codeword to the decoding mechanism.

In order to distinguish one coefficient block from another, each coefficient block is end-of-block (EO).
B) Terminated by code. This EOB code is sent by the VLC encoding circuit of the control circuit 26 to the final address word AD
It is provided as soon as it receives (7,7). It should be noted that it is advantageous to code the DC coefficients fixed length rather than variable length. The classification code C has a fixed length.

The codewords of the coefficient blocks make up the data blocks. In this example, VLC coding circuit 24 supplies the code words bit in series, thus the bit stream ^ z _j is obtained. The bitstream corresponding to the data block is shown in FIG. 2C. As is apparent from this drawing, the data block is, for example, 2
Classification code C having a fixed length of bits, for example, DC coefficient having a fixed length of 9 bits, variable length codewords V1, V
It continuously contains an EOB code having a variable number of 2, ... Vn and a fixed length of, for example, 5 bits.

The operations described above are used for the luminance signal Y and the chromaticity signals U and V. When the sampling frequency of the chromaticity signal in the horizontal and vertical directions is half the sampling frequency of the luminance signal, one chromaticity block U and one chromaticity block V are obtained for every four luminance blocks Y. In this regard, it is common practice to speak of macroblocks. Such a macroblock is shown symbolically in FIG.

The codewords of the group of data blocks and their respective lengths LEN are subsequently applied to a formatting circuit 25 which forms the channel bitstream z _j . The format circuit will be described in detail later.

[Format Circuit] FIG. 4 schematically shows an embodiment of the format circuit 25. The circuit includes a buffer memory 251, a distribution switch 252, a first memory 253,
It comprises a second memory 254 and a multiplex switch 255.
After that, the first memory 253 is the MID memory (Most Important
Data memory). After that, the second memory 254 is OV
It is called an F memory (overflow memory). First control circuit 2
56 is associated with the buffer 251, controls the distribution switch 252, and supplies the write address to the MID memory. The second control circuit 257 controls the multiplex switch 255 and supplies a read address to the MID memory.

The first control circuit 256 stores the code words of the group of data blocks stored in the buffer 251 as the memory 253.
Configured to dispense during 254. Suppose now that a group of 12 data blocks is processed each time. These twelve data blocks are defined as DB ₁ , ..., DB ₁₂ and correspond to double macroblocks containing two adjacent macroblocks (see FIG. 3).

The MID memory has an arrangement as shown in FIG. 5A. It is 128 bytes long and has a first byte STA that stores status information and a section F that has a length of 24 bytes that stores a fixed length codeword.
L, a section LAC storing variable length codewords representing low frequency AC coefficients, and a remaining section HAC storing other variable length codewords. The size of the LAC section is the control circuit for each double macroblock.
It is determined by 256.

More specifically, each data block DB _i
The LAC section of the includes a memory section having a length L _i that depends on the classification code C of the data block DB _i . As already mentioned above, C takes on the values 0 ... 3 depending on the extent of the image details of the corresponding sub-image. In the control circuit, the length L is fixed for each value of C. In this example, the length for C = 0 is 2 bytes,
3 bytes for C = 1, 4 for C = 2
Bytes, and 6 bytes for C = 3.

The operation of the control circuit 256 will be described with reference to the flow chart shown in FIG. In step 60, the operation of processing double macroblocks is initialized. In this initialization step, the control circuit is
The classification code C of 12 data blocks from 251 is read and the corresponding lengths L _i are added together. The sum thus obtained constitutes a LAC section of length N _LAC of the MID memory. In addition, the control circuit fixes the remaining length N _HAC of the HAC section.

Subsequently, the circuit initializes two memory addresses n _L and n _H , which respectively represent the bit positions in the LAC section and HAC section of the MID memory. Both addresses have an initial value of 0. Furthermore, the logical value 0 is assigned to one bit of the status byte STA (see FIG. 5A). The meaning of this status bit will be described in more detail.

After this initialization, the data block DB _i
Consecutive codewords (see FIG. 2C) of buffer memory 25
Transferred from 1 to one of the memory MID or OVF. In step 61, the control circuit causes the MID memory F
The first two codewords (fixed length classification code C and DC coefficient) are stored at predetermined fixed locations in the L section.
In process 62, the multiple variable length codewords of data block DB _i are subsequently stored in the LAC section of the MID memory. This is realized as follows. Codeword V is read (step 621),
In step 622 it is stored in the LAC section from bit position n _L. Subsequently, bit position n _L
Is incremented by the length LEN of the stored codeword.

In step 623 it is subsequently checked whether the stored codeword is an EOB code or whether the end of the memory section has exceeded the limit due to the storage of the codeword. The end of the memory section is the data block D processed so far
It is determined by the sum of the lengths L _i corresponding to the classification code C of B ₁ .... DB _i . If the end of the memory section does not exceed the limit and the stored codeword is not an EOB code, the circuit returns to step 621 to store the next codeword in the memory section.

In this way, the LAC with length L _i is
Each memory section of the section has a variable length codeword V1, V2, etc. of the corresponding data block DB _i (see FIG. 2).
As much as possible by C). These codewords represent the most significant AC coefficients of this block.

As is apparent from the above, the codeword last stored in a memory section exceeds the end of this memory section (represented by an integer byte). However, there is one exception. Final data block D
Codeword B ₁₂ must not exceed the length of the LAC section. This is accomplished by ascertaining for each codeword of the final data block DB ₁₂ (step 624) whether this codeword is completely stored in the LAC section (step 625). If the codeword does not match, the LAC section proceeds to step 62.
Filled with dummy bits at 6.

After the most important variable length codeword of the data block DB _i is stored in the corresponding memory section of the LAC section, the other codewords of this data block are stored. This operation occurs in process 63. In step 631 of this process, data block D
The subsequent codeword V of B _i is read. In step 632 it is ascertained whether the status bit STA has a logical value of zero. With this value, the status bit indicates that the codeword is stored in the HAC section of the MID memory. Distributor switch 252 is in the position shown in FIG. The status bits still have the value 0.

In step 633 it is subsequently checked whether the codeword V fits in the HAC section of the MID memory. If so, the codeword is stored in this section from bit position n _{H in} step 634. Subsequently, the bit position n _H is advanced by the length LEN of the stored codeword. At step 635 it is ascertained whether the stored codeword is an EOB code. If not, the subsequent codeword is read (step 631). If it is an EOB code and not all data blocks have been processed (step 636), the control circuit returns to step 61 to process subsequent data blocks.

In this way, all other codewords of the data block are successively stored in the HAC section of the MID memory, until in step 633 the codeword no longer completely fits in the HAC section. Done. If so, step
637 is executed. At this step, the codeword is stored in the HAC section as long as it fits in this section. This matching portion is designated by V _{L in} FIG.

Subsequently, the control circuit causes the distribution switch 252.
(See Figure 4) in another position. Therefore, the other bits of the code word (V _R) is stored in the OVF memory. Further, the logical value 1 is assigned to the status bit STA. As a result, all subsequent codewords of the data block are stored in OVF memory at step 638.
This OVF memory thus constitutes a buffer for data which no longer fits in the MID memory. This data is defined as surplus data.

The steps 627 and 636 of FIG. 6 will be described. In these steps it is ascertained whether the EOB code of the final data block DB ₁₂ has been processed. In that case, the distribution of the codeword between the two memories MID and OVF ends. Control circuit has status bit ST
It is checked in step 64 whether A has maintained a logical 0. The 12 data blocks are completely stored in the MID memory and no storage of extra data in the OVF memory occurs. In that case, the starting address of the still remaining space of the MID memory is calculated based on the bit position n _H in step 65. This starting address, rounded up to an integer number of bytes, gives the pointer P to the last memory location
Memorized in the form of. The remaining space between the last codeword and the rounded start address is filled with dummy bits.

FIG. 5B shows a double macro block in the MID memory.
The 1st example of distribution of a lock codeword is shown.
DC code of classification code C and 12 data blocks is FL
It is in a fixed position in the section. First of the LAC section
Memory section (length L₁Has) is DB₁Variable length of
Contains codewords V1, V2 and V3, where V3
Is the length L₁Is over. Second memory section is EO
DB including B code ₂Accommodates all codewords in
It looks like I've done it. Therefore, the third data block DB₃
The first codeword V1 of the
You can start. Final data block DB₁₂V1 .... V4
Are stored in the LAC section.

Codeword V5 is beyond this section. The shaded area indicates that the LAC section is filled with dummy bits. It should be noted once again that, for the sake of completeness, the length L _i of each memory section is directly concatenated to the value of the corresponding classification code C of the FL section. HAC section is DB
Filled with V4 ... VN of ₁ and other codewords starting from EOB. The 12 data blocks appear to have a total length in which all codewords do not fit in the MID memory. This is indicated by the status bit STA having a logical value of 1. The surplus data is stored in the OVF memory adjacent to the surplus data of the preceding double macroblock.

FIG. 5C shows a second example of codeword distribution of double macroblocks in the MID memory.
In this example, all codewords of 12 data blocks are stored in memory. The status bit therefore has the value 0, and the pointer P points to the start address of the still empty space of the HAC section of memory. The shaded area indicates that the space between the final codeword and the byte limit determined by P is filled with dummy bits.

Returning to FIG. 4, the data stored in the memories MID and OVF appear under the control of the second control circuit 257 to be combined by the multiplex switch 255 into the channel bitstream z _j to be transmitted. . The operation of the second control circuit will be described with reference to the flowchart shown in FIG.

In step 71, the control circuit reads the status bit STA into the MID memory. Step 72
At, it is ascertained whether the status bit STA has a logical one. If yes, the MID memory is completely filled with double macroblock data. In step 73, 128 bytes of MID memory are applied to the output through the multiplex switch. If the status bit has a logical 0, the circuit writes the value P to the MID memory at step 74. Subsequently, in step 75, the circuit applies to the output the first P bytes from the MID memory, 127-P bytes from the OVF memory and one byte of the value of P itself.

In this way, a 128-byte channel block is transmitted to each double macroblock. The division of such channel blocks is apparent from FIGS. 5B and 5C and need not be described separately. It should be noted that the "empty" space shown in FIG. 5C is only filled by the extra data transmissions that typically occur from other double macroblocks. Anyway, each channel block has 2
It should be emphasized that it contains a codeword representing a predetermined range of image details of one corresponding macroblock. As is clear from FIGS. 5B and 5C, the pointer P
Occupies only the transmission space when really needed. If there is no excess data in the channel block,
The byte can be used for transmitting the codeword.

[Decoding Mechanism] Decoding mechanism 8 (see FIG. 1)
At the receiving channel bit stream z ′ _j ,
83, the inverse DCT circuit 84, and the D / A converter 85 are sequentially advanced. The reformatting circuit 81 will be described in more detail. Other circuits are generally known and will not be described further.

[Deformatting Circuit] The reformatting circuit 81 shown schematically in FIG.
(See FIG. 4). This circuit comprises a channel block buffer 811, a distribution switch 812, a first memory 813, a second memory 814 and a multiplexing switch 815. The two memories 813 and 814 are hereafter defined as MID memory and OVF memory, respectively. First control circuit
816 is associated with the channel block buffer 811 to control the distribution switch 812 and supply the write address to the MID memory. The second control circuit 817 supplies the read address to the MID memory and controls the multiplex switch 815. It is also connected to the variable length decoder 82 (see FIG. 1).

The first control circuit 816 controls the memory MID and OVF.
It is applied to the distribution of data of each channel block between. This distribution operation will be described with reference to the flow chart shown in FIG. In step 91 the status bit STA is read and in step 92 it is ascertained whether the status bit has a logical value of one.
If YES, the complete channel block is step 93
Is stored in the MID memory via the distribution switch. If the status bit has a logical 0, the circuit reads the value P in step 94.

Subsequently, the circuit writes P bytes to the MID memory and other data to the OVF memory. After this distribution operation, the MID memory contains the codeword of the corresponding double macroblock. The manner in which these codewords are stored is entirely consistent with FIG. 5B or FIG. 5C. Thus, the MID memory has a 24-byte FL section, a LAC section with 12 memory sections of length L _i , and the remaining HAC section. The data in the OVF memory is the surplus data of another macro block.

After the channel blocks have been separated in this way, a recombination of the codewords of the double macroblock and its variable length decoding follows. This is the second control circuit 817.
Executed under the control of. The operation of the second control circuit 817 will be described with reference to the flowchart shown in FIG.
The consecutive codewords are first read from the MID memory via the multiplex switch 815 (see FIG. 8) and applied to the variable length decoding circuit 82. As is apparent from FIGS. 5B and 5C, the classification code C and the DC coefficients of the 12 data blocks are related first. In step 101, they are stored in the corresponding coefficient block by the variable length decoding circuit. During the reading of the classification code C, the control circuit
The length L _i of the C memory section, the total length N _{LAC of the LAC} section and the remaining length N _HAC of the HAC section are also determined.

Subsequently, the continuous codeword V is read from the LAC section in process 102. This process is further illustrated in FIG. In step 1021, the data block counter i and the bit position counter n are initialized. Each codeword is subsequently read and applied to the variable length decoder (step 102).
2). In step 1023 it is checked if the end of the LAC section has been reached. If you haven't arrived yet: The read codeword V represents one or more AC coefficients.

In step 1024, these coefficients ^ y
i, k are decoded by the variable length decoder and stored in the corresponding coefficient block. Then in step 1025,
Whether the current LAC memory section limit ΣL _i has been exceeded or whether the decoded codeword is EOB
You can see if it was code. If yes, the data block counter i is incremented by 1 to indicate that the subsequent codeword originated from the subsequent data block DB _i (step 1026).

The next codeword is subsequently read. Process 102 exits as soon as it is determined in step 1023 that all codewords have been written to the LAC section. This is the case when the bit position counter n exceeds the length N _LAC during the reading of the codeword before it is decoded by the variable length decoder.

The circuit continues the process 103 (see FIG. 10) where another codeword is read from the HAC section. This process is further illustrated in FIG. Step
At 1031, the data block counter i and the bit position counter n are reinitialized. At this time, the bit position counter indicates the position of the HAC section of the MID memory. Furthermore, a logical value of 0 is assigned to the routing bit R in this step. This routing bit controls the position of the multiplex switch 815 (see Figure 8).

MID memory is selected for R = 0,
And the OVF memory is selected for R = 1. In step 1032, the codeword is read from the selected memory. It is still a MID memory here. In step 1033 it is ascertained whether the limit of the HAC section has been reached. If NO, HA
The C section supplies the complete codeword V. YE
For S, it is a codeword that is no longer completely contained in the MID memory.

In step 1034, the routing bit gets the value 1, so the multiplex switch is placed in another position. The rest of the codewords as well as any subsequent codewords are read from the OVF memory. The codeword V thus read is decoded by the variable length decoder in step 1035 and stored in the corresponding coefficient block as the coefficient ^ yi, k.

In step 1036, it is ascertained whether the decoded codeword is an EOB code.
If no, the subsequent codeword is read.
If yes, the data block counter i is first incremented by 1 (step 1038). In this way, all codewords in the double macroblock will be the final EOB.
The code is decrypted until found (step 1037).

[Other Matters] In order to avoid overflow of the OVF memory, the length of the channel block and the number of channel blocks for each television image should match the amount of data. However, the length of the channel block does not have to match the average length of the double macroblock. If for some reason a shorter channel block is needed, the transmission of multiple channel blocks with corresponding data can be replaced by a channel block with only surplus data. In that case, the status byte of each channel block contains an indication of the channel block type.

It may further be noted that the channel blocks do not necessarily have to start at equidistant bit positions. To clarify the channel bitstream,
It suffices that the bit position at which each channel block starts is predetermined and known at the receiver end. In practice, different formats of recorder can be standardized for general and professional use. The same applies for the transmission and recording of standard TV signals and HDTV signals.

[Brief description of drawings]

FIG. 1 is a block diagram of a video recorder including a device for storing television images and a device for receiving the same according to the present invention.

2 is a diagram illustrating the operation of the encoding mechanism of FIG. 1. FIG.

FIG. 3 is another diagram illustrating the operation of the encoding mechanism of FIG.

FIG. 4 is a block diagram showing an embodiment of the format circuit of FIG.

5 is a diagram illustrating the operation of the format circuit of FIG.

FIG. 6 is a flowchart illustrating an operation of the format circuit of FIG.

FIG. 7 is a flowchart illustrating an operation of the format circuit of FIG.

8 is a block diagram showing an embodiment of the reformatting circuit of FIG. 1. FIG.

9 is a flowchart illustrating an operation of the deformatting circuit in FIG. 8;

FIG. 10 is a flowchart illustrating an operation of the deformatting circuit in FIG.

FIG. 11 is a flowchart illustrating an operation of the deformatting circuit in FIG. 8.

FIG. 12 is a flowchart illustrating an operation of the deformatting circuit in FIG. 8.

[Explanation of symbols]

 1 Image Signal Source 2 Encoding Mechanism 3 Modulating Circuit 4 Writing Head 5 Magnetic Tape 6 Reading Head 7 Demodulating Circuit 8 Decoding Mechanism 9 Monitor 21 A / D Converter 22 Discrete Cosine Transform (DCT) 23 Quantization Circuit 24 Variable Length Coding (VLC) circuit 25 Format circuit 26 Control circuit 60-61 Step 62-65 Process 71-75 Step 81 Deformat circuit 82 Variable length decoding circuit 83 Inverse quantization circuit 84 Inverse DCT circuit 85 D / A converter 91- 95 steps 101 steps 102-103 process 251 buffer memory 252 distribution switch 253 first memory 254 second memory 255 multiplex switch 256 first control circuit 257 second control circuit 621 -638 step 81 1 channel block buffer 812 distribution switch 813 first memory 814 Second memory 815 Multiplex switch 816 First control circuit 817 Second control circuit 1021-1026 Steps 1031-1038 -Up

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Wilhelms Jakobs van Hestel The Netherlands 5621 Beer Aindow Fenflune Wautzwech 1

Claims (15)

[Claims] 1. A means for dividing each television image into blocks of pixels; a coding means for coding each block of pixels into a corresponding data block of a variable length codeword; and a fixed length corresponding A format means for accommodating a code word of a data block in a channel block, wherein a surplus of data of the data block is accommodated in another channel block, and a lack of data in the channel block is data of another data block. In the transmission or storage device of a digital television image, the formatting means for padding with a surplus of is provided so that the formatting means stores the start address of the surplus data in the channel block at a predetermined position of the channel block. A digital test characterized by being configured Transmission or storage device vision image. 2. The formatting means does not transmit the start address when there is no surplus data in the channel block, and stores a status code indicating that there is no surplus data in another predetermined position of the channel block. The device for transmitting or storing digital television images according to claim 1, wherein 3. An apparatus for transmitting or storing digital television images according to claim 1, wherein the address is represented by a fixed-length integer. 4. A digital signal according to claim 3, wherein the space between the corresponding data block and the surplus data is filled with the start portion of a variable-length codeword longer than the space. Transmission or storage of television images. 5. The formatting means further comprises selecting selected codewords of at least two data blocks as 1.
Accommodated in corresponding consecutive sections of one channel block, while for each channel block section,
5. A digital signal according to claim 1, wherein a length code representing the length of the channel block section is configured to be accommodated in a predetermined position of the channel block. Transmission or storage of television images. 6. The encoding device according to claim 5, wherein the coding means classifies the data blocks according to the energy components of the image, and the length code is constituted by the class of the data blocks. A device for transmitting or storing the described digital television image. 7. A digital television image transmission or storage device according to claim 6, wherein said length code represents an integer of fixed word length. 8. Deformatting means for decomposing a channel block into a codeword of a corresponding data block and surplus data of another data block and adding the surplus data to the codeword of the corresponding data block, and a data block. In a device for receiving a digital television image in the form of a series of fixed-length channel blocks, including decoding means for decoding the television image, the de-formatting means comprises means for converting the surplus data contained in the channel blocks. An apparatus for receiving a digital television image, characterized in that the channel block is decomposed according to a start address. 9. A codeword contained in a predetermined contiguous portion of a channel block is assigned to a corresponding data block, the length of each block section being the length code contained in the channel block. 9. The digital television image receiving apparatus according to claim 8, wherein the receiving apparatus is configured to have a fixed length according to the above. 10. A digital television image transmitting or storing device according to any one of claims 1 to 7 and a digital television image receiving device according to claim 8 or 9. A video recorder. 11. A storage medium for storing a digital television picture coded in the form of a series of data blocks with variable length codewords, wherein the codewords of one data block correspond to one corresponding fixed length channel block. Stored in another channel block, the surplus data of the data block is accommodated in another channel block, the lacking portion of the data in the channel block is filled with the surplus data of the other data block, while the start address of the surplus data is stored in the other channel block. A storage medium characterized by being stored at a predetermined position. 12. The start address is not stored when there is no surplus data in the channel block, and a status code indicating that there is no surplus data is stored in another predetermined position of the channel block. The storage medium according to claim 11. 13. The storage medium according to claim 11, wherein the address is represented by a fixed-length integer. 14. The space between the corresponding data block and the surplus data is filled with a start portion of a variable-length codeword longer than the space.
The storage medium according to item 3. 15. A selected codeword of at least two data blocks is contained in corresponding consecutive sections of one channel block, while for each channel block section a length representing the length of the channel block section. The storage medium according to any one of claims 11 to 14, characterized in that the code is stored in a predetermined position of the channel block.