KR0147402B1 - Method for forming metal interconnection - Google Patents
Method for forming metal interconnectionInfo
- Publication number
- KR0147402B1 KR0147402B1 KR1019940021063A KR19940021063A KR0147402B1 KR 0147402 B1 KR0147402 B1 KR 0147402B1 KR 1019940021063 A KR1019940021063 A KR 1019940021063A KR 19940021063 A KR19940021063 A KR 19940021063A KR 0147402 B1 KR0147402 B1 KR 0147402B1
- Authority
- KR
- South Korea
- Prior art keywords
- titanium
- film
- contact hole
- forming
- layer
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
Abstract
본 발명은 금속배선 형성방법에 관한 것으로, 저온에서 단순한 공정에 의해 금속배선을 형성하기 위한 것이다.The present invention relates to a method for forming metal wiring, and to form metal wiring by a simple process at low temperature.
본 발명은 실리콘기판상의 절연막에 형성된 콘택홀 내부에 타이타늄을 증착하는 단계, 상기 타이타늄층에 질소이온을 이온주입하고 열처리를 행하여 타이타늄층 상부 표면부위에 타이타늄질화막을 형성하는 단계를 포함하는 것을 특징으로 하는 금속배선 형성방법을 제공한다.The present invention includes the steps of depositing titanium into a contact hole formed in an insulating film on a silicon substrate, ion implantation of nitrogen ions into the titanium layer and heat treatment to form a titanium nitride film on the upper surface portion of the titanium layer. It provides a metal wiring forming method.
Description
제1도는 종래의 금속배선 형성방법을 도시한 공정순서도.1 is a process flow chart showing a conventional method for forming metal wiring.
제2도는 본 발명에 의한 금속배선 형성방법을 도시한 공정순서도.2 is a process flowchart showing a metal wiring forming method according to the present invention.
제3도는 본 발명의 다른 실시예에 의한 금속배선 형성방법을 도시한 도면.3 is a view showing a metal wiring forming method according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 절연막1 silicon substrate 2 insulating film
3 : 타이타늄막 5 : 타이타늄질화막3: titanium film 5: titanium nitride film
6 : 텅스텐 7 : 알루미늄층6: tungsten 7: aluminum layer
본 발명은 금속배선 형성방법에 관한 것으로, 특히 금속배선형성시의 장벽금속(barrier metal) 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming metal wirings, and more particularly, to a method of forming a barrier metal in forming metal wirings.
일반적으로 반도체장치에서 서브마이크론(submicron) 이하의 고집적 소자제작에는 빠른 응답속도, 높은 집적도를 얻기 위한 다층배선구조가 필수적이며, 이러한 다층 배선구조가 높은 신뢰성을 갖기 위해서는 전극재료의 컨포멀(conformal)한 형성이 대단히 중요하다.In general, a multi-layered wiring structure for obtaining a high response speed and high integration is essential for fabricating highly integrated devices of submicron or less in semiconductor devices. In order to have high reliability, such a multilayer wiring structure is conformal to electrode materials. One formation is very important.
배선재료로 사용되는 알루미늄과 텅스텐등은 바이어스 스퍼터링(bias sputter ing), 선택적 기상 화학증착(selective chemical vapor deposition)등의 새로운 기술이 제안되면서 높은 애스펙트비(Aspect ratio)를 가지는 콘택 또는 비아홀(via hole)의 매립(filling)을 가능하게 하였다. 그러나 이러한 방법을 사용한다 하더라도 알루미늄과 텅스텐증착전에 신뢰성 있는 장벽층 또는 밀착층(Glue layer)을 형성하는 것이 선결조건이다. 이러한 장벽층 또는 밀착층으로는 타이타늄(Ti)막 또는 타이타늄 질화막(TiN)등이 널리 쓰이고 있는데 타이타늄막은 실리콘과 오믹접촉(ohmic contact) 형성이 용이한 반면에 타이타늄질화막은 열적안정도가 뛰어나고 접촉저항특성을 개선시킬 뿐 아니라 텅스텐과 타이타늄사이의 반응을 억제시켜주는 장점도 가지고 있다.Aluminum and tungsten, which are used as wiring materials, have high aspect ratio contacts or via holes with new technologies such as bias sputtering and selective chemical vapor deposition. ) Filling is possible. However, even with this method, it is a prerequisite to form a reliable barrier layer or glue layer before deposition of aluminum and tungsten. Titanium (Ti) film or titanium nitride film (TiN) is widely used as the barrier layer or adhesive layer. While the titanium film easily forms ohmic contact with silicon, the titanium nitride film has excellent thermal stability and contact resistance characteristics. In addition to improving the performance, the reaction between tungsten and titanium has the advantage.
그러나 높은 애스펙트비를 가지는 콘택구조에서 콘택의 바닥부위에 타이타늄질화막을 형성하는 방법이 어려워 이를 해결하기 위해 여러가지 방법이 시도되고 있다.However, in the contact structure having a high aspect ratio, a method of forming a titanium nitride film on the bottom portion of the contact is difficult, and various methods have been tried to solve this problem.
현재 64M DRAM급 이상의 소자에서 널리 사용되는 Al/W/TiN/Ti/Si의 배선구조에서 콘택홀내에 형성되는 텅스텐(W)은 단차피복성이 좋은 저압화학증착법으로 형성되나, 그 밑에 형성되는 타이타늄막(Ti)과 타이타늄질화막(TiN)은 스퍼터링방법에 의해 형성된다. 즉, 제1도에 도시된 바와 같이 실리콘기판(1)상의 절연막(2)에 형성된 배선 접촉홀 내부에 타이타늄막(3)을 스퍼터링방법에 의해 형성한 후(제1도 (a)), 이위에 타이타늄질화막(5)을 반응성 스퍼터링(reactive sputtering)법을 사용해 형성한다(제1도 (b)). 이때, 실제로 원하는 두께의 타이타늄질화막이 형성되지 않아 RTN(Rapid Thermal Nitridation)공정을 추가로 진행하는 경우가 많다. 이때, 타이타늄이 충분히 질화되기 위한 온도는 700℃이상의 고온이 되어야 하는 것으로 알려져 있다(제1도 (c)). 타이타늄질화막(5)을 형성한 후, 콘택홀 내부를 저압화학증착법을 이용하여 텅스텐(6)을 형성함으로써 매립한 다음 콘택홀 상부에 알루미늄층(7)을 형성한다.Tungsten (W) formed in contact holes in Al / W / TiN / Ti / Si wiring structure widely used in devices of 64M DRAM class or higher is formed by low pressure chemical vapor deposition with good step coverage, but the titanium formed thereunder The film Ti and the titanium nitride film TiN are formed by a sputtering method. That is, after forming the titanium film 3 by the sputtering method in the wiring contact hole formed in the insulating film 2 on the silicon substrate 1 as shown in Fig. 1 (Fig. 1 (a)), The titanium nitride film 5 is formed by using a reactive sputtering method (FIG. 1 (b)). At this time, since a titanium nitride film having a desired thickness is not actually formed, the RTN process is often further performed. At this time, it is known that the temperature for the titanium to be sufficiently nitrided should be a high temperature of 700 ° C. or more (FIG. 1C). After the titanium nitride film 5 is formed, the inside of the contact hole is buried by forming tungsten 6 using low pressure chemical vapor deposition, and then an aluminum layer 7 is formed on the contact hole.
한편, 스퍼터링시 스퍼터링된 원자의 직진성향을 높여 깊은 콘택홀 내부에 막형성을 용이하게 하기 위해 칼리메이터(collimator)(4)(하층기판에 수직운동성분이 큰 이온만을 통과시키는 창)를 사용하는 공정이 최근에 제안되고 있지만 이는 막형성율이 낮아 양산공정에 쓰이기 힘들뿐더러 이 방법 역시 700℃이상의 급속열처리공정을 거쳐야 하는 단점이 있다.On the other hand, a collimator 4 (a window through which only ions having a large vertical motion component pass through the lower substrate) is used to increase the straightness of the sputtered atoms during sputtering to facilitate film formation inside the deep contact hole. Although a process has recently been proposed, it is difficult to use in mass production because of low film formation rate, and this method also has a disadvantage of undergoing a rapid heat treatment process of 700 ° C. or more.
본 발명은 상술한 종래기술의 문제점을 해결하기 위한 것으로, 저온에서 단순한 공정에 의해 금속배선을 형성하는 방법을 제공하는 것을 그 목적으로 한다.The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a method for forming a metal wiring by a simple process at low temperature.
상기 목적을 달성하기 위한 본 발명의 금속배선 형성방법은 실리콘기판상의 절연막에 형성된 콘택홀 내부에 타이타늄을 증착하는 단계, 상기 타이타늄층에 질소이온을 이온주입하고 열처리를 행하여 타이타늄층 상부 표면부위에 타이타늄질화막을 형성하는 단계를 포함하여 구성된다.In order to achieve the above object, the method for forming a metal wiring according to the present invention comprises the steps of depositing titanium in a contact hole formed in an insulating film on a silicon substrate, ion implanting nitrogen ions into the titanium layer, and performing a heat treatment to form titanium on the upper surface portion of the titanium layer. And forming a nitride film.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
금속배선 형성시 장벽금속층 재료로 널리 사용되고 있는 타이타늄/타이타늄질화막이 복합구조를 형성하는데 있어서 현재 스퍼터링법이 널리 사용되고 있다. 스퍼터링법에 의해 형성된 막은 막의 균일성(Uniformity)이 뛰어나고 두께 및 조성제어가 용이한 것등의 장점이 있지만 소자가 고집적화되면서 단차피복성이 낮다는 단점이 문제로 제기되고 있다. 이를 보완하기 위해 칼리메이터공정 및 고온질화공정등이 사용되지만 이 역시 양산성등에 문제가 있고 단차피복성 개선에 한계가 있어 화학기상증착법에 의한 막 형성도 연구되고 있다. 이에 본 발명은 상대적으로 단차피복성이 좋은 타이타늄을 실제 목표두께보다 두껍게 형성한 후, 타이타늄 상층부위에 질소이온을 주입하여 타이타늄질화막을 형성한다.The sputtering method is widely used to form a composite structure of a titanium / titanium nitride film, which is widely used as a barrier metal layer material in forming metal wirings. The film formed by the sputtering method has advantages such as excellent film uniformity and easy control of thickness and composition, but has a problem of low step coverage due to high integration of devices. To compensate for this, a calibrator process and a high temperature nitriding process are used, but this also has problems in mass production, and there is a limit in improvement of step coating ability, and film formation by chemical vapor deposition is also being studied. Accordingly, the present invention forms a titanium nitride film having a relatively high step coverage and thicker than the actual target thickness, and then injecting nitrogen ions into the upper titanium layer.
제2도에 본 발명에 의한 금속배선 형성방법을 공정순서에 따라 도시하였다.2 shows a method for forming metal wiring according to the present invention according to the process sequence.
먼저, 제2도 (a)에 도시된 바와 같이 실리콘기판(1)상의 절연막(2)에 형성된 콘택홀 내부 및 절연막(2) 상부에 타이타늄막(3)을 실제 목표두께보다 후에 형성될 타이타늄질화막의 두께를 더한 두께만큼 두껍게, 예컨대 500-1500Å 정도의 두께로 스퍼터링에 의해 증착한 후, 제2도 (b)와 같이 상기 타이타늄막(3) 상부에 질소이온을 이온주입하고 열처리를 행하여 제2도 (c)에 도시된 바와 같이 타이타늄질화막(5)을 형성한다. 이때, 제3도에 도시한 바와 같이 질소이온의 이온주입깊이나 주입각도를 다양하게 하여 콘택홀 내부 측벽 및 타이타늄막내에 고루 질소이온이 주입되도록 할수도 있는데, 예를 들어 이온주입에너지를 1KeV이하의 낮은 에너지로부터 온도를 올려가며 표면에서 800Å깊이 걸쳐서 질소이온을 주입한다. 상기와 같이 질소이온주입 및 열처리에 의해 형성된 타이타늄 질화막상에 타이타늄 질화막을 스퍼터링에 의해 다시 형성할 수도 있다.First, as shown in FIG. 2A, the titanium nitride film to be formed after the titanium film 3 in the contact hole formed in the insulating film 2 on the silicon substrate 1 and on the insulating film 2 is later than the actual target thickness. After deposition by sputtering to a thickness as thick as the thickness of, for example, 500-1500Å, and then ion implanted with nitrogen ions on the titanium film 3 as shown in FIG. As shown in FIG. (C), the titanium nitride film 5 is formed. In this case, as shown in FIG. 3, the ion implantation depth or the implantation angle of the nitrogen ions may be varied so that the nitrogen ion may be evenly injected into the inner sidewall of the contact hole and the titanium film. For example, the ion implantation energy is 1 KeV or less. Inject nitrogen ions over 800 서 deep from the surface while raising the temperature from the low energy. As described above, the titanium nitride film may be formed again by sputtering on the titanium nitride film formed by nitrogen ion implantation and heat treatment.
이어서 제2도 (d)에 도시된 바와 같이 400-500℃의 온도에서 텅스텐(6)을 예컨대 저압화학증착법에 의해 증착하여 콘택홀을 매립한 후, 그 전면에 알루미늄층(7)을 증착함으로써 금속배선공정을 완료한다.Subsequently, as shown in FIG. 2 (d), tungsten 6 was deposited at a temperature of 400-500 ° C., for example, by low pressure chemical vapor deposition to fill a contact hole, and then an aluminum layer 7 was deposited on the entire surface thereof. Complete the metallization process.
이상과 같이 본 발명은 타이타늄막 표면부위에 질소이온을 주입하여 타이타늄질화막을 형성하므로 700℃이상의 고온질화공정이 필요없고 단지 낮은 온도의 반응단계만이 필요하게 되며, 이온주입시 주입깊이와 도핑농도를 정확히 조절할 수 있어 각 공정변수를 미세하게 제어할 수 있고 안정적인 공정여유도를 확보할 수 있으며, 칼리메이터공정등을 사용한 반응성 스퍼터링등 시간이 많이 소요되는 복잡한 공정이 필요없어 양상공정으로 사용할 수 있는 등 간단한 공정에 의해 신뢰성 있는 금속배선을 형성할 수 있게 된다.As described above, the present invention forms a titanium nitride film by injecting nitrogen ions into the surface of the titanium film, so that a high temperature nitriding process of 700 ° C. or more is not required, and only a low temperature reaction step is required. It can control precisely each process variable and secure stable process margin, and it can be used as modal process because it does not require time-consuming complicated process such as reactive sputtering using a calibrator process. It is possible to form a reliable metal wiring by a simple process such as.
Claims (6)
Priority Applications (1)
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KR1019940021063A KR0147402B1 (en) | 1994-08-25 | 1994-08-25 | Method for forming metal interconnection |
Applications Claiming Priority (1)
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KR1019940021063A KR0147402B1 (en) | 1994-08-25 | 1994-08-25 | Method for forming metal interconnection |
Publications (2)
Publication Number | Publication Date |
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KR960009124A KR960009124A (en) | 1996-03-22 |
KR0147402B1 true KR0147402B1 (en) | 1998-11-02 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019940021063A KR0147402B1 (en) | 1994-08-25 | 1994-08-25 | Method for forming metal interconnection |
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KR (1) | KR0147402B1 (en) |
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1994
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KR960009124A (en) | 1996-03-22 |
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