KR920010123B1 - Metal wired-film forming method - Google Patents
Metal wired-film forming method Download PDFInfo
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- KR920010123B1 KR920010123B1 KR1019890017102A KR890017102A KR920010123B1 KR 920010123 B1 KR920010123 B1 KR 920010123B1 KR 1019890017102 A KR1019890017102 A KR 1019890017102A KR 890017102 A KR890017102 A KR 890017102A KR 920010123 B1 KR920010123 B1 KR 920010123B1
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- film
- titanium
- forming
- metal wiring
- metal
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 25
- 239000002184 metal Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000010936 titanium Substances 0.000 claims abstract description 31
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 28
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 8
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 3
- -1 nitrogen ion Chemical class 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims abstract 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 abstract 2
- 238000001771 vacuum deposition Methods 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910003074 TiCl4 Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
첨부 도면은 발명의 실시예에 따른 반도체 소자의 금속 배선막의 제조공정도를 나타낸 것이다.The accompanying drawings show a manufacturing process diagram of a metal wiring film of a semiconductor device according to an embodiment of the invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : 실리콘 기판 2 : 불순물 주입영역1
3 : 절연막 4 : 콘택 홀3: insulating film 4: contact hole
5 : 티타늄막 61 : 티타늄 실리사이드막5: titanium film 61: titanium silicide film
62 : 질화 티타늄막 7 : 알루미늄 합금막62: titanium nitride film 7: aluminum alloy film
본 발명은 반도체 소자의 금속배선막 형성방법에 관한 것으로서, 더욱 상세하게는 티타늄을 이용하여 이중 구조의 전위금속(Barrier metal)을 형성하는 방법에 관한 것이다.BACKGROUND OF THE
고집적 기억소자를 제조하는 공정에 있어서, 종래에는 콘택홀에서 실리콘이 석출되는 것을 방지하기 위한 전위금속(Barrier Metal)을 형성하기 위하여 주로 티타늄막과 질화티타늄막을 스퍼터링방법으로 2번 도포하여 형성하였는데, 이런 경우에는 다음과 같은 문제점이 있었다.In the process of manufacturing a highly integrated memory device, conventionally, a titanium film and a titanium nitride film were mainly applied by a sputtering method twice to form a barrier metal for preventing silicon from depositing in a contact hole. In this case, there were the following problems.
첫째로, 티타늄(Ti)막과, 질화티타늄(TiN)막을 각각 도포해야 하므로, 공정상의 번거로움이 있으며, 둘째로, 티타늄막과 기타 실리콘과의 계면 불안정에 다른 소자의 전기적 특성이 저하되고, 셋째로, 티타늄막과 질화티타늄막을 스퍼터링방식으로 도포시키기 때문에 단차 피복성(step coverage)이 나쁘며, 넷째로, 질화티타늄막을 스퍼터링방법으로 도포하는 경우, 안정된 조성비를 가는 질화티타늄막을 재현성있게 도포하기 어려울 뿐만 아니라 다량의 입자(particle)가 발생되어 막질의 특성이 감소하고 소자의 제작시 불량율이 증가한다.Firstly, since the titanium (Ti) film and the titanium nitride (TiN) film must be applied, respectively, the process hassles. Second, the electrical properties of other devices are degraded due to the interface instability between the titanium film and other silicon. Third, the step coverage is poor because the titanium film and the titanium nitride film are applied by the sputtering method. Fourth, when the titanium nitride film is applied by the sputtering method, it is difficult to reproducibly apply a thin titanium nitride film having a stable composition ratio. In addition, a large amount of particles (particles) are generated to reduce the quality of the film quality and increase the defective rate during fabrication of the device.
본 발명의 목적은 티타늄막을 도포시킨 후 NH3 분위기하에서 램프 어닐링을 실시하여서, 콘택홀에서 티타늄 실리사이드막과 질화티타늄 실리사이드막의 이중구조의 전위금속을 형성하여 금속배선을 하는 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming metal wiring by forming a potential metal having a dual structure of a titanium silicide film and a titanium nitride silicide film in a contact hole by applying a titanium film and then performing lamp annealing in an NH 3 atmosphere. .
본 발명의 다른 목적은 티타늄을 화학증착법으로 단일막으로 도포시킴으로써 단차에 따른 단차 피복성을 개선시킨 금속배선 형성방법을 제공하는데 있다.Another object of the present invention is to provide a method for forming a metal wiring by improving the step coverage according to the step by applying titanium as a single film by chemical vapor deposition.
본 발명의 또 다른 목적은 티타늄막을 도포시킨 후, N2 이온을 주입하여 안정된 조성비를 갖는 질화 티타늄막을 형성시키는 금속배선 형성방법을 제공하는데 있다It is still another object of the present invention to provide a method for forming metal wirings by coating a titanium film and then implanting N2 ions to form a titanium nitride film having a stable composition ratio.
상기 목적을 달성하기 위하여 본 발명은 실리콘 기판위에 이온주입을 실시하여 불순물 영역을 형성시킨 후 절연막을 형성하는 공정과, 불순물 영역위에 콘택홀을 형성하는 공정과, 플라즈마 화학증착법으로 티타늄막을 도포시키는 공정과, 티타늄막위에 N2 이온을 주입하는 공정과, 티타늄막을 램프 어닐링방법으로 열처리하여 티타늄 실리사이드막과 질화 티타늄막을 형성하는 공정과, 질화 티타늄막위에 알루미늄 합금막을 도포시키는 공정으로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a process for forming an insulating film after forming an impurity region by ion implantation on a silicon substrate, forming a contact hole on the impurity region, and applying a titanium film by plasma chemical vapor deposition. And a step of injecting N2 ions onto the titanium film, heat treating the titanium film by a lamp annealing method to form a titanium silicide film and a titanium nitride film, and applying an aluminum alloy film on the titanium nitride film.
이하, 본 발명의 실시예를 첨부 도면에 의거하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부도면은 본 발명의 실시예에 따른 금속배선을 형성하는 제조공정도이다.The accompanying drawings are manufacturing process diagrams for forming metal wiring according to an embodiment of the present invention.
도면(a)에서와 같이, 실리콘 기판(1)에 불순물을 주입하여 불순물 주입영역(2)을 형성하고, 그 위에 절연막(3)을 화학 증착법으로 도포시킨 후 사진 식각공정을 실시하여 불순물 주입영역(2) 상부에 콘택 홀(4)을 형성한다.As shown in (a), the
콘택 홀(4)을 형성한 후 도면(b)에서처럼 티타늄막(5)을 플라즈마 화학 증착법으로 1200Å의 두께로 도포시키는데, 이때 사용가스는 TiCl4과 H2 가스가 사용되고, 온도는 400 내지 500℃이며, 반응로의 압력은 1.0Torr이다.After the contact hole 4 is formed, the
도포된 티타늄막(5) 위에 도면(c)에서와 같이, N2 이온 주입을 전면에 걸쳐 실시하는데, 이때 불순물의 량(dose)은 3×1015개/cm2이고, 에너지는 40KeV이다.As shown in (c) on the coated
티타늄막(5) 위에 N2 이온을 주입한 후, 램프 어닐링 방법으로 1차로 600℃ 내지 650℃, NH3 가스분위기하에서 10초 동안 열처리를 실시하고, 다시 2차로 800℃ 내지 850℃, NH3 분위기하에서 10초 동안 열처리를 실시하면 티타늄막(5)이 콘택 홀(4)에서 질화 티타늄막과 티타늄 실리사이드막으로 경합반응이 일어나게 된다.After injecting N2 ions onto the
즉, 도면(d)에 나타낸 바와 같이, 티타늄막(5)의 티타늄(Ti)과 실리콘 기판(1)의 실리콘(Si)이 반응하여 불순물 주입영역(2)내의 실리콘 기판(1)의 경계면에서는 티타늄 실리사이드막(61)이 형성되고, 티타늄막(5)의 티타늄(Ti)과 이온 주입된 질소(N2) 및 어닐링시의 암모니아 개스(NH3)가 반응을 하여 티타늄막(5)은 안정된 질화티타늄막(62)으로 된다.That is, as shown in (d), titanium (Ti) of the titanium film (5) reacts with silicon (Si) of the silicon substrate (1) to react at the interface of the silicon substrate (1) in the impurity implantation region (2). A
다음, 질화 티타늄막(62)위에 알루미늄 합금막이나 고융점 금속막으로 된 금속배선(7)을 도포하면, 도면(e)와 같이 안정된 특성을 유지하는 전위 금속을 포함하는 금속배선막이 형성된다.Next, when the
상기한 바와 같은 본 발명에 의하면, 다음과 같은 효과를 얻을 수 있는 이점이 있다.According to the present invention as described above, there is an advantage that the following effects can be obtained.
첫째로, 티타늄막을 화학 증착법으로 도포시킴으로써 전위금속의 단차 피복성을 향상시킬 수 있으며, 둘째로, 티타늄막을 도포시킨 후 저온의 램프 어닐링을 실시하므로써 티타늄 실리사이드막과 질화 티타늄막으로 구성되는 이중 구조의 전위금속을 갖는 금속배선을 할 수 있고, 셋째로, 티타늄막을 화학 증착법으로 형성하므로써 종래의 스퍼터링 방법으로 형성시킬 때 발생하는 입자의 발생을 방지할 수 있으며, 넷째로, 단일의 티타늄막을 도포한 후 질소이온을 주입하여 안정된 조성비를 갖는 질화 티타늄막을 형성할 수 있다.First, by applying the titanium film by chemical vapor deposition, the step coverage of the dislocation metal can be improved. Second, by applying the titanium film and performing a low temperature lamp annealing, a double structure composed of a titanium silicide film and a titanium nitride film Metal wiring with a potential metal can be carried out. Third, by forming a titanium film by chemical vapor deposition, it is possible to prevent generation of particles generated when forming by a conventional sputtering method. Fourth, after applying a single titanium film Nitrogen ions may be implanted to form a titanium nitride film having a stable composition ratio.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890017102A KR920010123B1 (en) | 1989-11-24 | 1989-11-24 | Metal wired-film forming method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890017102A KR920010123B1 (en) | 1989-11-24 | 1989-11-24 | Metal wired-film forming method |
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| Publication Number | Publication Date |
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| KR910010629A KR910010629A (en) | 1991-06-29 |
| KR920010123B1 true KR920010123B1 (en) | 1992-11-16 |
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| KR1019890017102A KR920010123B1 (en) | 1989-11-24 | 1989-11-24 | Metal wired-film forming method |
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| KR19980060529A (en) * | 1996-12-31 | 1998-10-07 | 김영환 | Metal wiring formation method of semiconductor device |
| KR100443517B1 (en) * | 2001-12-27 | 2004-08-09 | 주식회사 하이닉스반도체 | Method of manufacturing bit line of semiconductor device |
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