KR0146628B1 - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor deviceInfo
- Publication number
- KR0146628B1 KR0146628B1 KR1019940016081A KR19940016081A KR0146628B1 KR 0146628 B1 KR0146628 B1 KR 0146628B1 KR 1019940016081 A KR1019940016081 A KR 1019940016081A KR 19940016081 A KR19940016081 A KR 19940016081A KR 0146628 B1 KR0146628 B1 KR 0146628B1
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- KR
- South Korea
- Prior art keywords
- oxide film
- film
- field oxide
- semiconductor device
- manufacturing
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 콘택홀의 크기가 작은 고집적 반도체 제조공정에서 콘택홀의 얼라인먼트 마진(alignment margin) 확보와 BPSG에 의한 결정결함(crystal defect)을 방지하기 위하여, 실리콘 기판상에 필드 산화막 형성후 콘택홀이 형성될 부분의 주변 필드 산화막의 중간 부위만을 감광막으로 개방(open)하여 채널스톱(channel stop) 이온주입을 실시하여, 필드 산화막의 가장자리부분에는 채널스톱영역이 형성되지 않게하고, 필드 산화막 사이의 노출된 실리콘 기판에 소오스 및 드레인 전극용 불순물을 고에너지(high energy)로 주입하여 불순물 영역이 필드 산화막의 가장자리내부까지 형성되게 하므로써, 이후의 공정으로 형성되는 콘택홀의 얼라인먼트 마진을 충분히 확보하면서 기존의 플러그(plug) 이온주입공정으로 인한 BPSG막상의 결정결함 발생을 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in order to secure alignment margins of contact holes and to prevent crystal defects caused by BPSG in highly integrated semiconductor manufacturing processes having small contact holes, After the field oxide film is formed, only the middle portion of the field oxide film around the portion where the contact hole is to be formed is opened with a photoresist to perform channel stop ion implantation so that the channel stop region is not formed at the edge of the field oxide film. Then, the implantation margin of the contact hole formed in a subsequent process is formed by injecting impurities for source and drain electrodes with high energy into the exposed silicon substrate between the field oxide films so that the impurity regions are formed to the inner edge of the field oxide film. On the BPSG membrane due to the conventional plug ion implantation process Information is capable of preventing defects of the method of manufacturing a semiconductor device.
Description
제1, 2a 및 2b도는 종래의 기술로 반도체 소자를 제조할 때의 문제점을 설명하기 위한 소자의 단면도.1, 2A and 2B are cross-sectional views of a device for explaining a problem when manufacturing a semiconductor device by a conventional technique.
제3a도 내지 제3d도는 본 발명에 의한 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도.3A to 3D are cross-sectional views of devices for explaining the method for manufacturing a semiconductor device according to the present invention.
제4도는 본 발명을 적용하여 콘택홀에 금속배선을 형성한 상태를 도시한 소자의 단면도.4 is a cross-sectional view of a device showing a state in which metal wiring is formed in a contact hole by applying the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘 기판 12 : 패드 산화막11 silicon substrate 12 pad oxide film
13 : 질화막 14 : 제1감광막13: nitride film 14: first photosensitive film
15, 15A : 채널스톱영역 16, 16A : 필드산화막15, 15A: Channel stop area 16, 16A: Field oxide film
17 : 제2감광막 18 : 불순물 영역(소오스/드레인)17 second photosensitive film 18 impurity region (source / drain)
19 : 로드 산화막 20 : BPSG막19: loaded oxide film 20: BPSG film
21 : 금속배선21: metal wiring
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 콘택홀의 크기가 작은 고집적 반도체 제조공정에서 콘택홀의 얼라인먼트 마진(alignment margin) 확보와 BPSG에 의한 결정결함(crystal defect)을 방지하기 위하여, 실리콘 기판상에 필드 산화막 형성후 콘택홀이 형성될 부분의 주변 필드 산화막의 중간 부위만을 감광막으로 개방(open)하여 채널스톱(channel stop) 이온주입을 실시하여, 필드 산화막의 가장자리부분에는 채널스톱영역이 형성되지 않게하고, 필드 산화막 사이의 노출된 실리콘 기판에 소오스 및 드레인 전극용 불순물을 고에너지(high energy)로 주입하여 불순물 영역이 필드 산화막의 가장자리내부까지 형성되게 하므로써, 이후의 공정으로 형성되는 콘택홀의 얼라인먼트 마진을 충분히 확보하면서 기존의 플러그(plug) 이온주입공정으로 인한 BPSG막상의 결정결함 발생을 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, in order to secure alignment margins of contact holes and to prevent crystal defects caused by BPSG in highly integrated semiconductor manufacturing processes having small contact holes. After the formation of the field oxide film, channel stop ion implantation is performed by opening only the middle portion of the field oxide film around the portion where the contact hole is to be formed with the photoresist film, so that the channel stop region is not formed at the edge of the field oxide film. And implanting impurities for the source and drain electrodes into the exposed silicon substrate between the field oxide films at high energy so that the impurity regions are formed to the inside of the edge of the field oxide film, thereby aligning the contact holes formed in the subsequent process. BPSG membrane due to existing plug ion implantation process with sufficient margin The decision relates to a method for producing a semiconductor device capable of preventing defect generation.
일반적으로 콘택홀 크기가 작은 고집적 반도체 제조공정에서 콘택홀의 얼라인먼트 마진을 확보하기 위하여 플러그 이온주입공정을 실시하게 되는데, 이때 고온의 플러그 열처리를 통해 발생하는 BPSG막 표면상의 결정결함으로 인하여 소자의 신뢰성을 저하시키는 문제가 있다.In general, in a highly integrated semiconductor manufacturing process having a small contact hole size, a plug ion implantation process is performed to secure alignment margin of a contact hole. In this case, the reliability of the device is improved due to crystal defects on the surface of the BPSG film generated through high temperature plug heat treatment. There is a problem of deterioration.
제1도는 플러그 이온주입공정 없이 일반적인 공정에 의해 금속배선을 형성한 상태의 소자 단면도를 도시한 것으로, 실리콘 기판(1)상에 채널스톱영역(2), 필드 산화막(3), 소오스 및 드레인 전극용 불순물영역(4), 로드 산화막(5) 및 BPSG막(6)을 형성한 상태에서 콘택 마스크를 사용하여 콘택홀을 형성하고, 콘택홀을 통해 불순물 영역(4)에 연결되는 금속배선(7)을 형성한 상태를 도시한 것이다.1 is a cross-sectional view of a device in which a metal wiring is formed by a general process without a plug ion implantation process. The channel stop region 2, the field oxide film 3, the source and drain electrodes on the silicon substrate 1 are shown in FIG. A contact hole is formed using a contact mask in a state where the impurity region 4, the rod oxide film 5, and the BPSG film 6 are formed, and the metal wiring 7 connected to the impurity region 4 through the contact hole. ) Is a state formed.
그런데, 반도체 소자가 고집적화 되어감에 따라 콘택홀이 형성될 부분도 좁아지게 되고, 이로인하여 제1도에 도시한 바와같이 일측의 필드 산화막(3)의 가장자리부분이 식각되어진 콘택홀이 형성되고, 따라서 콘택홀 저면에는 채널스톱영역(2)이 노출되어 이 부분을 통해 누설전류(leakag current)가 발생된다.However, as the semiconductor device is highly integrated, the portion where the contact hole is to be formed is also narrowed, thereby forming a contact hole in which the edge portion of the field oxide film 3 on one side is etched, as shown in FIG. Therefore, the channel stop region 2 is exposed on the bottom of the contact hole, and leakage current is generated through this portion.
상기한 누설전류의 발생을 방지하기 위하여 제2a도에 도시된 바와같이 콘택홀(10) 형성후에 플러그 이온주입공정을 실시하여 상기 제1도와 같은 콘택홀(10) 저면에 노출된 채널스톱영역(2)을 불순물 영역(4)으로 전환시킨다. 이후 고온상태에서 플러그 열처리공정을 실시하게 되는데, 제2b도에 도시된 바와같이 BPSG막(6) 표면에 결정결함(8)이 발생되어 소자의 신뢰성을 저하시키는 문제가 있다.In order to prevent the occurrence of the leakage current, as shown in FIG. 2A, after the contact hole 10 is formed, a plug ion implantation process is performed to expose the channel stop region exposed to the bottom of the contact hole 10 as shown in FIG. 2) is converted to the impurity region 4. Thereafter, the plug heat treatment process is performed at a high temperature. As shown in FIG.
상기한 바와같이 플러그 이온주입공정을 실시하지 않을 경우 얼라인먼트 마진이 열악하여 누설전류가 발생되는 문제가 있고, 이런 문제를 해결하기 위해 플러그 이온주입공정을 반드시 실시해야 하는데, 이 방법 또한 BPSG막 표면에 생성되는 결정결함으로 인하여 소자의 신뢰성을 저하시킨다.As described above, when the plug ion implantation process is not performed, there is a problem in that leakage margin is generated due to poor alignment margin. To solve this problem, the plug ion implantation process must be performed. The resulting crystal defects reduce the reliability of the device.
따라서, 본 발명은 플러그 이온주입공정 없이 콘택홀의 얼라인먼트 마진을 충분히 확보하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of sufficiently securing an alignment margin of a contact hole without a plug ion implantation process and improving the reliability of the device.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자 제조방법은 실리콘 기판(11)상에 패드 산화막(12)과 질화막(13)을 순차적으로 형성한 후 소자분리 마스크를 사용하여 필드영역의 패드 산화막(12) 및 질화막(13)을 제거하고, 전체구조 상부에 제1감광막(14)을 도포한 후 이후의 공정으로 콘택홀이 형성될 영역 A와 그 주변부의 필드영역 B 상부에 제1감광막(14)이 남도록 패턴화하고, 노출된 다른 필드영역에 불순물 이온주입공정을 실시하여 채널 스톱영역(15)을 형성하는 단계와, 상기 단계로부터 패턴화된 제1감광막(14)을 제거한 후 산화공정을 실시하여 필드영역에 필드 산화막(16 및 16A)을 성장시키고, 이후 질화막(13) 및 패드 산화막(12)을 제거하는 단계와, 상기 단계로부터 전체구조 상부에 제2감광막(17)을 도포한 후 콘택홀이 형성될 부분의 주변 필드 산화막(16A)의 중앙 상부를 개방하고, 상기 제2감광막(17)의 개방부분을 통해 불순물 이온주입공정으로 채널스톱영역(15A)을 형성하는 단계와, 상기 단계로부터 게이트 전극등을 형성한 후 소오스 및 드레인 전극용 불순물을 주입하여 불순물 영역(18)을 형성하는 단계로 이루어지는 것을 특징으로 한다.In the semiconductor device manufacturing method of the present invention for achieving the above object, the pad oxide film 12 and the nitride film 13 are sequentially formed on the silicon substrate 11, and then the pad oxide film 12 in the field region is formed using an element isolation mask. ) And the nitride film 13 are removed, and the first photosensitive film 14 is applied over the entire structure, and then the first photosensitive film 14 is placed over the area A where the contact hole is to be formed and the field area B around the periphery thereof. Patterning the remaining portions, and performing impurity ion implantation on other exposed field regions to form the channel stop region 15, and removing the patterned first photosensitive film 14 therefrom and performing an oxidation process. Growing the field oxide films 16 and 16A in the field region, and then removing the nitride film 13 and the pad oxide film 12, and applying the second photoresist film 17 over the entire structure from the step, and then contacting. Field fields around the area where the hole will be formed Opening the center upper portion of the film 16A, and forming the channel stop region 15A through the impurity ion implantation process through the open portion of the second photosensitive film 17, and after forming the gate electrode and the like from the step And impurity regions 18 are formed by implanting impurities for the source and drain electrodes.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제3a 내지 제3d도는 본 발명에 의한 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도로서,3A to 3D are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the present invention.
제3a도는 실리콘 기판(11)상에 패드 산화막(12)와 질화막(13)을 순차적으로 형성한 후 소자분리 마스크를 사용하여 필드영역의 패드 산화막(12) 및 질화막(13)을 제거하고, 전체구조 상부에 제1감광막(14)을 도포한 후 이후의 공정으로 콘택홀이 형성될 영역 A와 그 주변부의 필드영역 B 상부에 제1감광막(14)이 남도록 패턴화하고, 노출된 다른 필드영역에 불순물 이온주입공정을 실시하여 채널 스톱영역(15)을 형성한 상태를 도시한 것이다.3A shows that the pad oxide film 12 and the nitride film 13 are sequentially formed on the silicon substrate 11, and then the pad oxide film 12 and the nitride film 13 in the field region are removed using an element isolation mask. After applying the first photoresist film 14 to the upper part of the structure, patterning the first photoresist film 14 to remain on the area A where the contact hole is to be formed in the subsequent process and the field area B of the periphery thereof, and other exposed field areas. The state where the channel stop region 15 is formed by performing an impurity ion implantation process is shown in FIG.
제3b도는 상기 패턴화된 제1감광막(14)을 제거한 후 산화공정을 실시하여 필드영역에 필드 산화막(16 및 16A)을 성장시키고, 이후 질화막(13) 및 패드 산화막(12)을 제거한 상태를 도시한 것이다.3B illustrates the removal of the patterned first photoresist film 14, followed by an oxidation process to grow the field oxide films 16 and 16A in the field region, and then to remove the nitride film 13 and the pad oxide film 12. It is shown.
제3c도는 전체구조 상부에 제2감광막(17)을 도포한 후 콘택홀이 형성될 부분의 주변 필드 산화막(16A)의 중앙 상부를 개방(open)하고, 상기 제2감광막(17)의 개방부분을 통해 불순물 이온주입공정으로 채널스톱영역(15A)을 형성한 상태를 도시한 것이다. 상기에서 제2감광막(17)의 개방부위는 필드 산화막(16A)보다 0.4~0.8㎛ 정도 작게 형성된다. 그로인해 상기 채널스톱영역(15A)은 필드 산화막(16A)의 중앙부위에만 형성되고 필드 산화막(16A)의 가장자리부위에는 형성되지 않는다.FIG. 3C illustrates that after applying the second photoresist film 17 over the entire structure, the center upper portion of the peripheral field oxide film 16A of the portion where the contact hole is to be formed is opened, and the open portion of the second photoresist film 17 is opened. The channel stop region 15A is formed through the impurity ion implantation process through FIG. The open portion of the second photosensitive film 17 is formed to be about 0.4 to 0.8 [mu] m smaller than the field oxide film 16A. As a result, the channel stop region 15A is formed only at the center portion of the field oxide film 16A and not at the edge portion of the field oxide film 16A.
제3d도는 게이트 전극등을 형성한 후 소오스 및 드레인 전극용 불순물을 주입하여 불순물 영역(18)을 형성한 상태를 도시한 것으로, 이때 고에너지로 불순물 주입공정을 실시하여 불순물 영역(18)이 필드 산화막(16A)의 가장자리내부까지 형성되게 한다.FIG. 3D illustrates a state in which the impurity region 18 is formed by injecting impurities for source and drain electrodes after forming a gate electrode or the like, wherein the impurity region 18 is filled by performing an impurity implantation process at high energy. It is made to form inside the edge of the oxide film 16A.
제4도는 상기 제3d도의 상태하에서 로드 산화막(19) 및 BPSG막(20)을 형성한 후 콘택 마스크를 사용하여 콘택홀을 형성하고, 콘택홀을 통해 불순물 영역(18)에 연결되는 금속배선(21)을 형성한 상태를 도시한 것이다.FIG. 4 illustrates the formation of the rod oxide film 19 and the BPSG film 20 in the state of FIG. 3d, and then forming a contact hole using a contact mask, and a metal wiring connected to the impurity region 18 through the contact hole. 21 shows the state formed.
제4도에서는 불순물 영역(18)이 필드 산화막(16A)의 가장자리 내부까지 형성되고, 또한 제3d도에 도시된 채널스톱영역(15A)이 제4도의 금속배선(21) 형성 공정동안의 소정의 열처리공정으로 인하여 확산되었으나, 불순물 영역(18)내로 확산되지 않아 일측의 필드 산화막(16A)의 가장자리부분이 식각되어진 콘택홀이 형성되더라도 콘택홀 저면에 채널스톱영역(15A)이 노출되지 않는다.In FIG. 4, the impurity region 18 is formed to the inside of the edge of the field oxide film 16A, and the channel stop region 15A shown in FIG. 3d is formed during the process of forming the metal wiring 21 of FIG. Although diffused due to the heat treatment process, the channel stop region 15A is not exposed on the bottom of the contact hole even when a contact hole is formed in which the edge portion of the field oxide layer 16A on one side is etched because it is not diffused into the impurity region 18.
제1도와 제4도를 동일한 조건하에서 비교해 볼 때, 콘택홀의 얼라인먼트 마진은 제4도에서 지시된 부호 M의 2배 만큼 크기때문에 제2a도에 도시된 바와같은 플러그 이온주입공정을 행하지 않아도 된다.When comparing FIG. 1 and FIG. 4 under the same conditions, the alignment margin of the contact hole is twice as large as the symbol M indicated in FIG. 4, so that the plug ion implantation process as shown in FIG. 2A does not need to be performed.
상술한 바에 의거한 본 발명은 고온의 플러그 열처리공정시 발생하는 결정결함의 생성을 방지할 수 있고, 콘택홀의 얼라인먼트 마진을 충분히 확보할 수 있어 소자의 수율 및 신뢰성을 향상시킬 수 있다.According to the present invention as described above, it is possible to prevent the formation of crystal defects generated during the plug heat treatment at a high temperature, and to sufficiently secure the alignment margin of the contact hole, thereby improving the yield and reliability of the device.
Claims (4)
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