JPH09148457A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To clarify the identification of an identification pattern, and improve the separation property of a field oxide film by covering the top of the identification pattern with a buffer polycrystalline silicon of refractive index different from that of a silicon oxide film. SOLUTION: Wiring 18 consisting of aluminum is made all over the surface, and a photosensitive resin is also made all over the surface, and the photosensitive resin is patterned to be formed in the formation area of wiring 18. Then, with the photosensitive resin as an etching mask, the wiring 18 is patterned, using etching gas, and the wiring 18 and a heavily doped diffusion area 15, and the wiring 18 and the gate electrode 14 are connected with each other, respectively. The identification pattern 24 made on the field oxide film 12 is covered largely with a buffer polycrystalline silicon 25 difference in refractive index from the silicon oxide film. Accordingly, the interference color of the light 34 is decided by only the difference between the thickness of the identification pattern 23 and the thickness of the field oxide film 12. Hereby, the difference of interference color becomes clear and also the element separation property improves more than conventional one, by the interference color of the film thickness including a conventional insulating film 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a ROM so-called read-only memory identification pattern.

[0002]

2. Description of the Related Art A conventional method of manufacturing a semiconductor device having a read-only memory identification pattern will be described with reference to sectional views of FIGS. 19 to 25 and a plan view of the semiconductor device of FIG.

First, as shown in FIG. 19, a field oxide film 12 having a film thickness of 550 nm is formed in an element isolation region on a semiconductor substrate 11.

Next, as shown in FIG. 20, the first photosensitive resin 21 is formed by photolithography so that the N-type channel layer forming region 31 and the identification pattern forming region 32 on the field oxide film 12 are opened. To form.

Next, as shown in FIG. 21, phosphorus is ion-implanted into the semiconductor substrate 11 in which the first photosensitive resin 21 and the field oxide film 12 are aligned, and the depletion MOS is formed.
An N-type channel layer 27 is formed in a region which will be a channel portion of the transistor.

Next, as shown in FIG. 22, using the first photosensitive resin 21 as an etching mask and using hydrofluoric acid as an etching solution, the field oxide film 12 is etched to form an identification pattern 23. Since the identification pattern 23 is formed to identify the contents of the ROM after the semiconductor device is formed, the field oxide film 12 is etched by 50 nm or more so that the pattern can be identified until the final step.

However, the N-type channel layer forming region 31 is
Not only is the semiconductor substrate 11 aligned with the field oxide film 12 opened, but a field opening 29 is also partially formed on the field oxide film 12. Therefore, the field oxide film 12 in the field opening 29 is also etched.

Next, as shown in FIG. 23, the first photosensitive resin 21 is removed. After that, a gate oxide film 13 made of silicon oxide is formed on the semiconductor substrate 11 in which the field oxide film 12 is aligned by thermal oxidation. After that, the gate electrode 14 made of polycrystalline silicon is formed by a chemical vapor deposition method (hereinafter referred to as a CVD method). Then, the gate electrode 14 and the gate oxide film 13 are patterned by photoetching.

Next, as shown in FIG. 24, the gate electrode 1
Semiconductor substrate 11 matching field oxide film 4 with field oxide film 12
Impurities are introduced by ion implantation to form high-concentration diffusion regions 15 serving as the source and drain of the transistor.

Next, as shown in FIG. 25, an interlayer insulating film 16 made of silicon oxide containing phosphorus and boron is formed by the CVD method. Then, heat treatment is performed in a nitrogen atmosphere to fluidize the interlayer insulating film 16, so-called reflow is performed to planarize the surface of the interlayer insulating film 16, and at the same time,
The impurities in the high concentration diffusion region 15 formed by the ion implantation are activated.

After that, a connection hole 17 is formed in the interlayer insulating film 16 by photoetching. After that, the wiring 18 made of aluminum is formed on the entire surface, and the aluminum is patterned by photoetching.

[0012]

The problems of the prior art will be described with reference to FIGS. 25 and 26. FIG. 26 is a plan view showing a conventional semiconductor device, and a cross section of the one-dot chain line is the cross section of FIG. The identification pattern 23 formed on the field oxide film 12 is composed of symbols, letters, and numbers, and these patterns are formed so as to identify the contents of the ROM.

The identification pattern 23 formed on the field oxide film 12 is different from the field oxide film 12 region in the thickness difference of the silicon oxide film on the semiconductor substrate 11. Therefore, the identification pattern 23 can be identified from the difference in the interference color of the light 34 due to the difference in the film thickness.

Identification pattern 2 is used to clarify this identification.
In the etching process for forming 3, the field oxide film 1
2 must be sufficiently etched. The reason for this discrimination is the difference in the interference color of the light 34 as described above. Since the field oxide film 12 and the interlayer insulating film 16 are the same silicon oxide film and have the same refractive index, the difference in the interference color of the light 34 is due to the identification pattern 23 and the interlayer insulating film 16, and the field oxide film 12 and the interlayer insulating film. It is determined by the film thickness difference with 16.

Further, as shown in FIG. 26, in the ROM, the gate electrode 14 is arranged perpendicularly to the element region 30 between the field oxide films 12, and the element region 30 and the gate electrode 14 have a lattice structure. There is. The N-type channel layer 27 of the depletion MOS transistor is formed in the region where the gate electrode 14 and the element region 30 intersect, and the N-type channel layer 27 is formed in the region where the gate electrode 14 and the element region 30 intersect. Various ROM depending on whether or not
Can be formed.

However, the first photosensitive resin opening region 33 for forming the N-type channel layer 27 is provided with the gate electrode 14
The field oxide film 12 region is also opened because it is necessary to open not only the region where the element region 30 intersects with the device region 30 but also the periphery thereof in consideration of misalignment in the photolithography process.

Therefore, when the field oxide film 12 is sufficiently etched to ensure the identification of the identification pattern 23, the field oxide film 12 around the N-type channel layer 27 is formed.
Becomes lighter. As a result, the threshold voltage of the parasitic MOS transistor in the field opening 29 is lowered, and an electrical leak occurs, causing a malfunction during the read operation of the ROM.

That is, if the field oxide film 12 is sufficiently etched to ensure the identification of the identification pattern 23, the separability of the field oxide film 12 deteriorates. vice versa,
If the field oxide film 12 is not sufficiently etched, there arises a problem that the identification pattern 23 becomes difficult to identify.

An object of the present invention is to solve the above problems, to provide a method of manufacturing a semiconductor device capable of clarifying the identification of the identification pattern 23 and improving the isolation of the field oxide film 12. Is.

[0020]

In order to achieve the above object, the method for forming a semiconductor device of the present invention employs the following steps.

According to the method of manufacturing a semiconductor device of the present invention, a field oxide film is formed in an element isolation region on a semiconductor substrate, and an N-type channel layer forming region and an identification pattern forming region are opened by a photolithography process. Forming a photosensitive resin, a step of forming an N-type channel layer serving as a channel region of the depletion MOS transistor on a semiconductor substrate in which the field oxide film and the photosensitive resin are aligned, and an etching step. Thin the field oxide film that matches the field oxide film, form the identification pattern on the field oxide film, remove the photosensitive resin, and form the gate oxide film on the semiconductor substrate that matches the field oxide film. A step of forming polycrystalline silicon on the gate, and forming a gate electrode by photo-etching treatment,
Simultaneously with the formation of the gate electrode, a step of forming buffer polycrystalline silicon so as to largely cover the upper part of the identification pattern forming area, a step of forming a high-concentration diffusion area on the semiconductor substrate where the gate electrode and the field oxide film are aligned, A step of forming an interlayer insulating film, a step of performing heat treatment to activate impurities in the high-concentration diffusion region, a step of forming a connection hole in the interlayer insulating film by a photoetching process, and a step of forming a wiring. Have and.

In the method of manufacturing a semiconductor device of the present invention, an N-type channel layer forming region and an identification pattern forming region are opened by a step of forming a field oxide film in an element isolation region on a semiconductor substrate and a photolithography step. Forming a photosensitive resin, a step of forming an N-type channel layer serving as a channel region of the depletion MOS transistor on a semiconductor substrate in which the field oxide film and the photosensitive resin are aligned, and an etching step. Of the field oxide film that is aligned, the identification pattern is formed on the field oxide film, the photosensitive resin is removed, and the step of forming the sacrificial oxide film on the semiconductor substrate that is aligned with the field oxide film, The upper part of the identification pattern formation area is enlarged by the step of forming the buffer silicon nitride film on the A step of forming a buffer silicon nitride film so as to cover it completely, a step of removing the sacrificial oxide film, a step of forming a gate oxide film on a semiconductor substrate in which a field oxide film is aligned, and a step of forming polycrystalline silicon on the entire surface. A step of forming a gate electrode by a photo etching process,
A step of forming a high-concentration diffusion region on the semiconductor substrate in which the gate electrode and the field oxide film are aligned, a step of forming an interlayer insulating film on the entire surface, and a heat treatment to activate impurities in the high-concentration diffusion region The method includes a step, a step of forming a connection hole in the interlayer insulating film by a photoetching process, and a step of forming a wiring.

In the method of manufacturing a semiconductor device according to the present invention, the identification pattern formed on the field oxide film is largely covered with polycrystalline silicon or a silicon nitride film having a refractive index different from that of the silicon oxide film. Therefore, the difference in interference color between the identification pattern and the field oxide film is determined only by the difference between the film thickness of the identification pattern and the film thickness of the field oxide film.

As a result, the interference color does not vary with the film thickness including the interlayer insulating film as in the prior art, so that an interference color occurs when comparing the prior art with the present invention. For this reason, the relative film thickness difference becomes larger than in the conventional technique, and the difference in interference color becomes clear.

Further, in the case of the film thickness including the interlayer insulating film as in the prior art, the interference color is less likely to appear as the film thickness increases,
Hard to see. In the present invention, even if the etching of the field oxide film of the identification pattern is reduced, the relative difference in the film thickness of the silicon oxide film, which causes the difference in the interference color, can be afforded as compared with the conventional technique. Is clearer than before. Therefore, the amount of etching of the field oxide film for forming the identification pattern is less than in the conventional case, and the isolation of the field oxide film is improved.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION The best embodiment of the method for manufacturing a semiconductor device of the present invention will be described below. Introduction Figure 1
To FIG. 9, the first best mode for carrying out the present invention will be described.
A method of manufacturing the semiconductor device according to the embodiment will be described.
1 to 9 are cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps, and FIG. 10 is a plan view showing the semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 1, a silicon nitride film (not shown) having a film thickness of 150 nm is formed on the entire surface of a P-type semiconductor substrate 11 by the CVD method. After that, a photosensitive resin (not shown) is formed on the entire surface by a spin coating method, exposed by using a predetermined photomask, developed, and patterned to form the photosensitive resin on the element region.

Then, using this photosensitive resin as an etching mask and using carbon tetrafluoride as an etching gas, silicon nitride is patterned in the element region by a reactive ion etching method (hereinafter referred to as RIE) to form an antioxidant film. (Not shown). After that, the photosensitive resin is removed.

After that, the semiconductor substrate 11 with the matched anti-oxidation film is heated at a temperature of 1000 in an oxygen atmosphere containing water vapor.
Heat treatment at ℃ for 105 minutes to form silicon oxide,
A field oxide film 12 of silicon oxide having a film thickness of 550 nm is formed in the element isolation region by so-called selective oxidation.
Thereafter, the antioxidant film is removed with phosphoric acid heated to a temperature of 180 ° C.

Next, as shown in FIG. 2, the first photosensitive resin 21 is formed on the entire surface by a spin coating method, exposed using a predetermined photomask, and developed to perform N-type channel layer forming region 31. Then, the first photosensitive resin 21 is patterned so as to open the identification pattern forming region 32.

Next, as shown in FIG. 3, phosphorus is accelerated into the semiconductor substrate 11 in which the first photosensitive resin 21 and the field oxide film 12 are aligned, with an acceleration energy of 50 keV and an implantation amount of 3.
Ions are implanted at 0 × 10 ¹³ atoms / cm ² to form the N-type channel layer 27 of the depletion MOS transistor.

Next, as shown in FIG. 4, the field oxide film 12 is etched using the first photosensitive resin 21 as an etching mask and hydrofluoric acid as an etching solution. This etching is 10 nm to 30 nm by controlling the time.
Etching is performed to a thickness of nm to form a step in the field oxide film 12 and an identification pattern 23 is formed.

Next, as shown in FIG. 5, the first photosensitive resin 21 is removed. After that, the temperature is 100 in an oxygen atmosphere.
A heat treatment at 0 ° C. is performed for 12 minutes to form a gate oxide film 13 of silicon oxide having a film thickness of 20 nm on the semiconductor substrate 11 matching the field oxide film 12.

Thereafter, polysilane 24 having a thickness of 350 nm is formed on the entire surface by CVD using monosilane as a reactive gas.

Next, as shown in FIG. 6, a second photosensitive resin 22 is formed on the entire surface by a spin coating method, exposed by using a photomask, and developed to perform a development process on the gate electrode formation region and the identification pattern 23. Patterning is performed so that the second photosensitive resin 22 is formed on the upper surface. Identification pattern 2 here
The second photosensitive resin 22 on 3 is also patterned on the surrounding field oxide film 12 so as to sufficiently cover the identification pattern 23.

After that, the polycrystalline silicon 24 is etched by RIE using the second photosensitive resin 22 as an etching mask and sulfur hexafluoride as an etching gas to etch the gate electrode 14 and the buffer polycrystalline silicon 25. And the gate oxide film 13 is patterned with hydrofluoric acid.

Next, as shown in FIG. 7, the second photosensitive resin 22 is removed. Then, arsenic is accelerated into the semiconductor substrate 11 in which the gate electrode 14 and the field oxide film 12 are aligned with an acceleration energy of 60 keV and an implantation amount of 3.0 × 10 ¹⁵ atom.
Ions are implanted at s / cm ² to form the high-concentration diffusion region 15 serving as the source / drain of the transistor.

Next, as shown in FIG. 8, a 700 nm-thickness silicon oxide interlayer insulating film containing phosphorus and boron was formed by a CVD method using monosilane, phosphine, diborane, oxygen, and nitrogen as reactive gases. 16 is formed.

After that, heat treatment at a temperature of 900 ° C. is performed for 30 minutes in a nitrogen atmosphere to fluidize the interlayer insulating film 16, so-called reflow is performed to planarize the surface of the interlayer insulating film 16 and at the same time, it is formed by ion implantation. , Activate the impurities in the high concentration diffusion region 15.

After that, a photosensitive resin (not shown) having a film thickness of 1.1 μm is formed on the entire surface, exposed and developed using a predetermined photomask, and the photosensitive resin is patterned so that only the connection hole forming region is opened. To do. After that, the interlayer insulating film 16 is etched by RIE using methane trifluoride as an etching gas using the photosensitive resin as an etching mask, the photosensitive resin is removed, and a connection hole 17 having an opening diameter of 0.8 μm is formed. To do.

Next, as shown in FIG. 9, a wiring 18 made of aluminum having a film thickness of 1 μm is formed on the entire surface by a sputtering method, and a photosensitive resin (not shown) having a film thickness of 1.6 μm is formed on the entire surface by a spin coating method. Then, it is exposed to light using a predetermined photomask, developed, and patterned so that a photosensitive resin is formed in the formation region of the wiring 18.

After that, the wiring 18 is patterned by RIE using boron trichloride and methane trichloride as an etching gas with the photosensitive resin as an etching mask, and the wiring 18 and the high-concentration diffusion region 15, and the wiring 18 and the gate. The electrode 14 is connected. After that, the photosensitive resin is removed.

The ROM and the identification pattern 23 are shown in the plan view of FIG. The cross-sectional view shown in FIG. 9 shows a cross section taken along one-dot chain line in FIG. As shown in FIG. 10, since the identification pattern 23 formed on the field oxide film 12 is largely covered with the buffer polycrystalline silicon 25 having a different refractive index from the silicon oxide film, the interference color of the light 34 is identified as shown in FIG. It is determined only by the difference between the film thickness of the pattern 23 and the film thickness of the field oxide film 12.

Therefore, as in the prior art, the interlayer insulating film 1
The relative film thickness difference that causes the interference color difference is larger than the interference color of the film thickness including 6 and the difference in the interference color becomes clear.
Further, the film thickness of the identification pattern 23 or the field oxide film 12 in which a difference in interference color appears is not thickened to the film thickness including the interlayer insulating film 16 unlike the conventional technique, and is thickened to a film in which an interference color is hard to appear. I won't.

Therefore, the interference color is also easily generated, and the identification pattern 23 can be identified more easily than in the prior art. Further, the etching of the field oxide film 12 for forming the identification pattern 23 may be as small as 10 nm to 30 nm, and the separability of the field oxide film 12 is improved as compared with the conventional case.

Next, another embodiment in which an effect equivalent to that of the first embodiment is obtained will be described. A method for manufacturing a semiconductor device according to the second preferred embodiment of the present invention will be described below with reference to FIGS. 11 to 17. 11 to 17 are sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps, and FIG. 18 is a plan view showing the semiconductor device according to the second embodiment of the present invention. .

First, as shown in FIG. 11, the field oxide film 12 is formed in the element isolation region on the P type semiconductor substrate 11 as in the first embodiment, and the N type channel layer 27 is formed on the semiconductor substrate 11. An identification pattern 23 is formed on the field oxide film 12.

Next, as shown in FIG. 12, a heat treatment at a temperature of 1000 ° C. is performed for 12 minutes in an oxygen atmosphere, and a sacrificial oxide film 26 made of silicon oxide and having a thickness of 20 nm is formed on the semiconductor substrate 11 matching the field oxide film 12. To form. This sacrificial oxide film 26 is formed so as not to give damage such as crystal defects to the surface of the semiconductor substrate 11 when the buffer silicon nitride film 28 to be formed later is etched.

After that, a film thickness of 150 n is obtained by a CVD method using dichlorosilane and ammonia as reactive gases.
A buffer silicon nitride film 28 of m is formed on the entire surface.

Next, as shown in FIG. 13, a photosensitive resin (not shown) is formed on the entire surface by a spin coating method, is exposed using a photomask, is developed, and the identification pattern 2 is formed.
Patterning is performed so as to form a photosensitive resin on the surface 3.
At this time, the photosensitive resin on the identification pattern 23 is covered with the surrounding field oxide film 12 so as to sufficiently cover the identification pattern 23.
Also pattern on the top.

Then, using a photosensitive resin as an etching mask and using fluorocarbon as an etching gas, R
The buffer silicon nitride film 28 is patterned by IE. After that, the photosensitive resin is removed.

Since the semiconductor substrate 11 is covered with the field oxide film 12 or the sacrificial oxide film 26, the semiconductor substrate 11 is not damaged during etching.

Next, as shown in FIG. 14, the sacrificial oxide film 26 is removed using hydrofluoric acid as an etching solution.

Next, as shown in FIG. 15, a heat treatment at a temperature of 1000 ° C. is performed for 12 minutes in an oxygen atmosphere to form a gate oxide film 13 of silicon oxide having a thickness of 20 nm on the semiconductor substrate 11 matching the field oxide film 12. To form.

Then, a polycrystalline silicon 24 having a film thickness of 350 nm is formed on the entire surface by a CVD method using monosilane as a reactive gas.

Next, as shown in FIG. 16, a second photosensitive resin 22 is formed on the entire surface by a spin coating method, exposed by using a photomask, and developed to perform a second treatment on the gate electrode formation region. Patterning is performed so as to form the photosensitive resin 22.

After that, the polycrystalline silicon 24 is etched by RIE using the second photosensitive resin 22 as an etching mask and sulfur hexafluoride as an etching gas to form the gate electrode 14. Then, the gate oxide film 13 is patterned using hydrofluoric acid as an etching solution.

Next, as shown in FIG. 17, as in the first embodiment, the second photosensitive resin 22 is removed, the high-concentration diffusion region 15 and the interlayer insulating film 16 are formed, and the interlayer insulating film is formed. 1
6, the connection holes 17 are formed, the wiring 18 is formed, and the wiring 18, the high-concentration diffusion region 15, and the wiring 1 are formed.
8 and the gate electrode 14 are connected.

A plan view of the ROM and the identification pattern 23 is shown in FIG. The cross-sectional view shown in FIG. 17 shows a cross-section taken along alternate long and short dash line in FIG. Similar to the first embodiment, as shown in FIG. 18, the identification pattern 23 formed on the field oxide film 12 is largely covered with a buffer silicon nitride film 28 having a refractive index different from that of the silicon oxide film. As described above, the interference color of the light 34 is determined only by the difference between the film thickness of the identification pattern 23 and the film thickness of the field oxide film 12.

Therefore, as in the prior art, the interlayer insulating film 1
With the film thickness including 6 as well, the relative film thickness difference that causes the interference color difference becomes larger than the interference color, and the interference color difference becomes clear. Further, the thickness of the identification pattern 23 or the field oxide film 12 that causes a difference in interference color is the same as in the conventional technique.
The film thickness including 6 is not increased, and the film thickness in which interference color is hard to appear is not increased.

Therefore, the interference color is also easily generated, and the identification pattern 23 can be identified more easily than in the prior art. Further, the field oxide film 1 for forming the identification pattern 23
The second etching also requires a small etching of 10 nm to 30 nm, and the separability of the field oxide film 12 is also improved as compared with the conventional case.

Furthermore, in the first and second embodiments of the present invention, the N-type channel MOS transistor has been described. However, when the ROM is formed by the P-type channel MOS transistor, it is the same as the above-described embodiment. The same effect can be obtained.

[0063]

As is apparent from the above description, in the method of manufacturing a semiconductor device of the present invention, the recognition of the identification pattern is
This is more improved than before and the element isolation of the field oxide film is also improved.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 11 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 12 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 13 is a cross-sectional view showing the method for manufacturing the semiconductor device in the embodiment of the present invention.

FIG. 14 is a sectional view illustrating the method of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 15 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 16 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 17 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 18 is a plan view of the semiconductor device according to the embodiment of the present invention.

FIG. 19 is a cross-sectional view showing the method of manufacturing the semiconductor device in the conventional technique.

FIG. 20 is a cross-sectional view showing the method of manufacturing the semiconductor device in the conventional technique.

FIG. 21 is a cross-sectional view showing the method of manufacturing the semiconductor device in the conventional technique.

FIG. 22 is a cross-sectional view showing the method of manufacturing the semiconductor device in the conventional technique.

FIG. 23 is a cross-sectional view showing the method of manufacturing the semiconductor device in the conventional technique.

FIG. 24 is a cross-sectional view showing the method of manufacturing a semiconductor device in the related art.

FIG. 25 is a cross-sectional view showing the method of manufacturing the semiconductor device in the conventional technique.

FIG. 26 is a plan view of a semiconductor device according to a conventional technique.

[Explanation of symbols]

 12 field oxide film 14 gate electrode 23 identification pattern 24 polycrystalline silicon 26 sacrificial oxide film 32 identification pattern formation region

Claims (2)

[Claims] 1. A step of forming a field oxide film in an element isolation region on a semiconductor substrate, and a step of forming a photosensitive resin having an N-type channel layer forming region and an identification pattern forming region opened by a photolithography process. On the semiconductor substrate in which the field oxide film and the photosensitive resin are aligned, N serving as the channel region of the depletion MOS transistor is formed.
By the process of forming the mold channel layer and the etching process, the field oxide film matching the photosensitive resin is thinned,
Forming an identification pattern on the field oxide film, removing the photosensitive resin, forming a gate oxide film on the semiconductor substrate in which the field oxide film is aligned, and forming polycrystalline silicon on the entire surface, A step of forming a gate electrode by photo-etching and forming a buffer polycrystalline silicon so as to largely cover the upper part of the identification pattern forming region at the same time as forming the gate electrode, and a step of forming a gate electrode and a field oxide film on the semiconductor substrate are aligned. A step of forming a concentration diffusion region, a step of forming an interlayer insulating film on the entire surface, a step of performing heat treatment to activate impurities in the high concentration diffusion region, and a connection hole in the interlayer insulating film by photoetching treatment. A method of manufacturing a semiconductor device, comprising a step of forming and a step of forming wiring. 2. A step of forming a field oxide film in an element isolation region on a semiconductor substrate, and a step of forming a photosensitive resin having an N-type channel layer forming region and an identification pattern forming region opened by a photolithography process. On the semiconductor substrate in which the field oxide film and the photosensitive resin are aligned, N serving as the channel region of the depletion MOS transistor is formed.
By the process of forming the mold channel layer and the etching process, the field oxide film matching the photosensitive resin is thinned,
A step of forming an identification pattern on the field oxide film and removing the photosensitive resin; a step of forming a sacrificial oxide film on the semiconductor substrate in which the field oxide film is aligned; and a step of forming a buffer silicon nitride film on the entire surface. A step of forming a buffer silicon nitride film so as to largely cover the upper part of the identification pattern forming region by photoetching and removing the sacrificial oxide film, and a step of forming a gate oxide film on the semiconductor substrate in which the field oxide film is aligned. , A step of forming polycrystalline silicon on the entire surface, a step of forming a gate electrode by photoetching treatment, a step of forming a high-concentration diffusion region on a semiconductor substrate in which the gate electrode and the field oxide film are aligned, A step of forming an interlayer insulating film, a step of performing heat treatment to activate impurities in the high concentration diffusion region,
A method of manufacturing a semiconductor device, comprising: a step of forming a connection hole in an interlayer insulating film by photoetching; and a step of forming a wiring.