KR0146439B1 - Ipc transmission apparatus in atm switching system - Google Patents

Abstract

The present invention relates to an IPC transmission device of an ATM exchange system, which separates and transmits a message in a cell form defined inside an exchange through an ATM unit switch and an ATM centralized switch without configuring a separate communication network, and receives and reassembles a cell into a message. In order to provide an IPC transmission device that performs communication between processors through the process of receiving the data, the data is received in an IMI cell format from an external switch, the routing tag, the block code, and the CRC are removed, converted into an ATM cell, and transmitted. PSIA (31) for receiving and transmitting to the switch in the IMI cell format; An IARA 32 which receives an ATM cell from the PSIA 31, assembles the cell data into a message, verifies the CRC, and transmits it to an external MP 34; And an IASA 33 which receives an IPC message from the MP 34, decomposes it into cell data, pads the rest, calculates a CRC, and then inserts a trailer and transmits it to the PSIA 31. This reduces complexity, simplifies the IPC transport protocol, and frees up processor number selection.

Description

IPC Transmission Device in ATM Switching System

1 is a schematic structural diagram of an ATM switch to which the present invention is applied.

2 is a structural diagram of an IMI cell

3 is a block diagram of an IPC transmission apparatus according to the present invention

4 is a configuration diagram of the message transmission format between MPMA-IASA and IASA

5 is a diagram of the cell primitive format between IASA-PSIA and IARA

6 is a configuration diagram of the received message format between the MPMA and IARA and IARA

7 is a message format and matching structure diagram between PSIA-IARA

* Explanation of symbols for main parts of the drawings

31: PSIA 32: IARA

33: IASA 34: MPMA

The present invention relates to an inter-processor communication (IPC) transmission apparatus of an Asynchronous Transfer Mode (ATM) exchange.

Conventionally, since IPC channels are implemented by configuring separate communication networks for each processor for IPC transmission, the number of cables increases, communication protocols become complicated, and it is difficult to change the processor numbering system.

The present invention devised to solve the above problems is an ATM unit switch without configuring a separate communication network using a processor switch interface board assembly (PSIA), IPC AAL Sender Board Assembly (IASA) and IPC AAL Receiver Board Assembly (IARA) It is an object of the present invention to provide an IPC transmission apparatus that performs communication between processors through a process of separating and transmitting a message in a cell form defined within an exchange through an ATM centralized switch, receiving a cell, and reassembling the message.

In order to achieve the above object, the present invention receives data from an external switch in an inter-module interface (IMI) cell format, removes a routing tag, block code, and cyclic redunancy check (CRC), and converts the data into an ATM cell. PSIA (Processor Switch Interface Board Assembly) which receives the cell data and sends it to the switch in IMI cell format; receives ATM cell from the PSIA, assembles the cell data into a message, verifies the CRC, and transmits it to an external MP (Main Processor). IARA (IPC AAL Receiver Bard Assembly); and IASA (IPC AAL Sender Board Assembly) which receives IPC message from MP and decomposes it into cell data, pads the rest to calculate CRC, and then adds trailer to PSIA. Characterized in having a.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

1 is a schematic structural diagram of an ATM exchanger to which the present invention is applied, and is composed of two types of subsystems as shown in the figure.

One of them is the Access Central Subsystem (ACS) 20, which controls and manages the entire system, and provides an operator matching function so that the operator can manage the system. The ACS 20 includes an operation management processor (OMP) 22, an operator matching device, a data storage device 23, and a central switch (CSW) 21.

The other is an access local subsystem (ALS) 10 that controls and manages the subscriber matching device 11 and the unit switch 12. ALS 10 is a subscriber call processor (SCP) (13), a subscriber matching device (11) and a unit switch (ASW) (Access Switch (ASW)) that manages the status of various connections and manages the status of hardware devices. 12).

The OMP 22 transmits and receives an IPC connected to one port of the CSW 21 and the SCP 13 is connected to one port of the ASW 12 through an inter-module interface (IMI) link. The IPC path between SCP (13) and SCP (13) has a three-stage structure via ASW (12) and CSW (21) and again ASW (12), and communication between OMP (22) and SCP (13) is CSW. It has a two-stage structure that passes through the 21 and the ASW 12.

The physical layer used in the IPC uses IMI, which uses a cell-based communication method that delivers a cell stream without a frame to an internal cell consisting of 64 octets on a coaxial cable. The link communication speed is about 187.78 MHz. As shown in FIG. 2, the cell structure used in the IMI is classified into four blocks by routing 3 octets of the routing header, 53 octets of the payload, and 8 octets of coding information before coding and transmitting the same.

In the IMI cell form, B indicates whether a cell slot is in use or not, and M indicates whether it is a multicast cell. In IPC, an end-to-end cell is always used. CET identifies the payload of the cell. In IPC, B'11 indicates the IPC. ASW ORG indicates the ASW output port of the originating SCP, CSW indicates the output port of the CSW, and ASW_DES indicates the ASW of the destination SCP. Display the output port. Cell Delay Priority (CDP) determines priority with respect to cell transmission.

The payload of each block is coded according to a certain coding principle, and the coding information is displayed in a block code of each block, and a CRC is calculated by calculating a cyclic redundancy check (CRC) of each block.

3 is a configuration diagram of an IPC transmission apparatus according to the present invention, 31 denotes PSIA, 32 denotes IARA, 33 denotes IASA, and 34 denotes MPMA.

The ATM layer transfers the cell received from the ATM Adaptation Layer (AAL) layer into an IMI cell form and delivers it to the physical layer, and removes the routing header and block code from the IMI cell received from the physical layer and delivers it to the AAL layer. Perform.

The AAL layer uses AAL Type 5 (TYPE5). When a message is received from the main processor (MP) 34, the payload is divided into 48 octets of cells, and the cells not divided into 48 octets are filled with '0' and the CRC-32 is calculated to calculate a CRC-32 trailer. After inserting the data transmission to the ATM layer, when receiving a cell from the ATM layer performs a function of assembling a message for each VCI (Virtual Channel Indentifier) to verify the CRC-32 and then deliver it to the MP (34).

The hardware that handles the IPC performs the functions of the processor switch interface assembly (PSIA) 31 performing the physical layer and the ATM layer, the IPC AAL sender assembly (IASA) 33 performing the AAL layer transmitter function, and the AAL layer receiver function. IARA (IPC AAL Receiver Assembly) 32 is composed of. The relationship of IPC protocol hardware is shown in FIG. The IPC protocol stack includes applications, Concurrent Realtime Operating System (CROS), Common Part Convergence Sublasyer (CPCS), Segmentation and Reassembly (SAR), ATM, and IMI.

The interface and operation between PBAs (Printed Board Assembly) performing each layer function are as follows.

4 is a configuration diagram of a message transmission format between the MPMA-IASA and the IASA.

When sending an IPC, the MP 34 writes the message in the message format shown in Figure 4 to the message First In First Out (FIFO) in the IASA 33.

Here, the SOM (Start of Message) is a part indicating the start of the message, when the most significant bit is set to '1', the IASA 33 recognizes the beginning of the message. The next two bytes of the message to be transmitted are displayed in 16-bit binary numbers, and are divided into upper bytes and lower bytes. CPCS_CP, CPCS_CI, and CPCS_UU are user-configurable data. Transmit transparently to lower layers. In addition, the VPI (Virtual Path Indentifier) and VCI indicate the VPI and VCI values of the cell in which the message is to be carried, which has a unique number for each processor and for each message. The remaining three bytes ASW_ORG, CSW, and ASW_DES are the switch routing tags. If the proper tag is set to be routed from the switch to the processor to send the IPC message from the MP 34, the IASA 33 transparently transfers the data as it is. Set to send. A PDU (Protocol Data Unit) is data to be transmitted.

Message transmission request after writing data in the above format from MP 34 to IASA 33 (CTXRDY: MPMA sends IPC message to IASA, decomposes the message into cells, and then transmits to PSIA) In this case, the SSCOP matching unit 331 in the IASA 33 reads the data of the message FIFO, decomposes the payload into cells of 48 octets, and transmits the routing information and the cell header to the primitive FIFO in order to transmit them to the PSIA 31. The payload of is written to the cell data FIFO and then sends a cell transfer request to the PSIA 31 (IREQ: IASA requests the PSIA to read the cell data when the IPC message is decomposed into cells and stored in the IASA).

At this time, the MP 34 reads the status register 336 of the IASA 33 to determine a length mismatch between the MP 34 and the IASA 33 or the IASA 33 and the PSIA 31. After the determination, the reset signal is transmitted to the IASA 31 so that the next message can be transmitted after the IASA 33 is initialized. The MSG is an IPC message sent from the MPMA 34 to the IASA 33. (The detailed structure of the IASA is filed on April 22, 1994 under the name of AAL Type 5 Common Part Transmitter. Filed under No. 94-8589)

5 is a configuration diagram of a cell primitive type and IARA between IASA and PSIA.

When the PSIA 31 receives a transmission request (IREQ) to transmit a cell from the IASA 33 as shown in FIG. 5, the IASA 33 receives the payload data read clock (IDRD) of the cell and the hair data read clock of the cell. After receiving the IPRD signal, the cell primitive (IPR) and the cell data (IDATA) are read to make a cell for transmission on the IMI link, converted into serial data, and a routing tag is attached to the cell. In this case, there are two types of cell data transmitted from the IASA 33, primitive data and payload data. The primitive data represents 48 bytes of payload of the cell, and the primitive data has cell hair data of the same format as the fifth degree.

In the primitive data format, SOM denotes the beginning of primitive data, while ATM User-to User Indication (AUU), Cell Loss Priority (CLP), Congestion Indication (CI), VPI, and VCI are data received from higher layers, or MPs (34). Is transmitted as it is, and the AUU only the first cell and the intermediate cell are set to '0' and only the last cell of the message is set to '1' to indicate the end of the message. The remaining ASW_ORG, CSW, and ASW_DES transfer the routing information received from the higher level. A PDU (Protocol Data Unit) is data to be transmitted.

In addition, when data is input from the IMI link, the cell is extracted and converted into parallel data, and only the ATM cell from which the routing information and block coding information of the IMI cell is removed is stored in the FIFO to indicate that there is a receiving cell (FNE: FIFO). Not Empty: A signal indicating that more than one cell is stored in the PSIA cell buffer) is transmitted to the IARA 32 to read the received cell.

At this time, the PSIA 31 transmits the cell data ID and the cell sync bit SYNCH to the IARA 32 according to the cell read clock IDRCLK generated by the IARA 32 as shown in FIG. In this case, the data format is the same as the ATM cell format shown in FIG. 7, and adds one cell sync bit to the IARA 32 so that the cell boundary can be found accurately.

6 is a configuration diagram of a received message format and an IARA between MPMA and IARA.

The IATA 32 reads a cell from the PSIA 31, refers to a LookUp Table 327 for each VCI, determines whether to allocate a free list pointer, and then checks whether it is the last cell of the message. In the case of a cell, the message is stored in the complete queue 324, then reassembled and stored in the message buffer 322, CRC-32 verification is performed, and an MP 34 generates an interrupt (IRQ IACK). Read from MP (34). If it is not the last cell, the cell is classified by VCI and stored in the connection buffer 326. The format of the message delivered from the IARA 32 to the MP 34 and the interface between the IARA 32 and the MP 34 are shown in FIG.

In the message format, the first two bytes represent the length of the received IPC message in 16-bit binary, separated by the high byte and the low byte, and the CPI (Commom Part Indication), CPCS_UU, CLP, and AUU_CI are the users included in the message. Pass the information as it is. In addition, VCI and VPI carry the value contained in the cell before the message is assembled, and NULL is the space reserved for future use. A PDU (Protocol Data Unit) is data to be transmitted. (The detailed structure of IARA was filed under application No. 94-7612 on April 12, 1994 under the name of AAL type 5 common convergence sublayer receiver and reassembly circuit in a separate buffer method.)

When the MP 34 receives an interrupt request (IRQ), which is a message reassembly completion signal of the IARA 32, the MP34 generates an interrupt acknowledgment (IACK) when the service is available, and reads the status register 323 of the IARA 32 to read the message. Determines whether the CRC-32 verification condition is satisfied, and generates a message read clock to IARA 32 to read the message. At this time, a message sync bit is also added to the message to indicate the message boundary.

In the present invention as described above, the IPC transmission path of the ATM exchanger does not form a separate communication network, but through the ATM unit switch and the ATM centralized switch, the message is decomposed and transmitted in a cell form defined inside the exchange, and the cell is received and reconstructed as a message. Assembly reduces the cable complexity inside the exchange, simplifies the IPC transport protocol, and frees up processor number selection.

Claims (4)

Receives data in IMI (Inter-mudule Interface) cell format from an external switch, removes routing tags, block codes, and cyclic redundancy checks (CRC), converts them into ATM cells, transmits them, and receives cell data into the IMI cell format. PSIA (Processor Switch Interface Board Assembly) to transmit to; An IRC (IPC AAL Receiver Board Assembly) 32 which receives an ATM cell from the PSIA 31 and assembles the cell data into a message to verify the CRC and then transmits it to an external MP (Main Processor) 34; And an IPC AAL Sender Board Assembly (IASA) 33 which receives an IPC message from the MP 34, decomposes it into cell data, pads the remainder, calculates a CRC, and inserts a trailer to transmit to the PSIA 31. IPC transmission device in the ATM exchange, characterized in that provided The cell payload data read clock (IDRD) of the cell and the header data read clock of the cell are transmitted to the IASA 33 when the PSIA 31 receives a transfer request (IREQ) from the IASA 33. (IPRD) transmits a cell primitive (IPR) and cell data (IDATA) from the IASA 33 to make a cell, converts it into serial data, attaches a routing tag, and transmits the cell to the switch. When data is inputted from the IARA (32 FIFO Not Eempty) signal, indicating that there is a receiving cell after extracting the cell, extracting the cell, converting the data into parallel data, and removing the IMI cell routing information and block coding information. And transmits the IARA (32) cell data (ID) and the cell sync bit (SYNCH) by receiving a cell read clock (IDRCLK) from the IARA (32). IPC transmission device 3. The method of claim 2, wherein the IASA 33 writes data from the MP 34 to the IASA 33, and then sends a message request (CTXRDY), the SSCP matching unit 331 in the IASA 33 sends a message FIFO. In order to read the data of the cell and decompose the payload into cells and transmit it to the PSIA 31, the routing information and the cell header are written to the primitive FIFO, and the payload is written to the cell data FIFO, and then the cell transfer request to the PSIA 31 (IREQ). The MP 34 reads the status register 336 of the IASA 33 to read a length mismatch between the MP 34 and the IASA 33 or between the IASA 33 and the PSIA 31. ) In the case that the IASA 31 transmits a reset signal to initialize the IASA 33 and then transmits the next message MSG in the ATM exchanger. IPC transmission device 4. The method of claim 3, wherein the IARA 32 reads a cell from the PSIA 31 and references a LookUp Table 327 for each VCI and then determines whether to allocate a free list pointer. Check if it is the last cell of the message, and if it is the last cell, store it in the Complete Queue 324, reassemble the message, store it in the message buffer 322, CRC-32 verification, and then go to the MP 34. If an interrupt (IRQ IACK) is generated and not the last cell, the cells are classified by VCI and stored in the connection buffer 326. The MP 34 is a message reassembly completion signal of the IARA 32. When an IRQ (Interrupt Request) is received, an interrupt acknowledgment (IAC) is generated at the moment of service, and the status register 323 of the IARA 32 is read to determine whether the message satisfies the CRC-32 verification condition and is correct. Message read clock with IARA (32) IPC transmission device in ATM exchange, characterized in that generating MRD)