KR0146086B1 - Reset detecting circuit using outer pulse - Google Patents

Abstract

The present invention relates to a reset detection circuit and a method using an external pulse, and conventionally, the microprocessor must be in an ACTIVE state in order to recognize the interrupt signal from the timer to read the binary count value. There are many problems such as efficiency and inefficiency due to the hassle and unnecessary operation of continuously performing READ / WRITE operation by the timer even if no pulse is generated because the turbine or rotor is not moving. . Therefore, in the present invention, when the microprocessor operates in the active mode at power-on and the reset signal is input, the microprocessor executes a program from the beginning and does not continue to operate when the operation is completed. In this case, power consumption can be reduced by about 1/100 by repeating the power down mode.

Description

Reset Detection Circuit Using External Pulse

1 is a pulse counter circuit diagram using a conventional timer.

2 is a flowchart of an operation of a timer in FIG. 1.

3 is a flow chart in FIG. 1 where an interrupt signal from a timer is delivered to the microprocessor.

4 is a reset detection circuit using an external pulse of the present invention.

5 is an input and output waveform diagram of each part in FIG.

6 is a flowchart illustrating a reset detection method using an external pulse.

* Explanation of symbols for the main parts of the drawings

10: microprocessor 20: timer

30: memory 40: binary counter

50: pulse counter 60: turbine and rotor

AD1: Andgate DF / F: Deflip

ENR: Exclusive Noah Gate

The present invention relates to minimizing power consumption when driving a microprocessor. More particularly, the present invention relates to a reset sensing circuit and a method using an external pulse that enables the microprocessor to control a power-down mode with minimum power consumption using an external pulse. .

Conventional pulse counter circuit configuration using a timer detects the movement of the microprocessor (1) and the turbine and the rotor (5) for controlling all peripheral devices as shown in FIG. A pulse generator 4 which outputs an output, a binary counter 2 representing a pulse value input from the pulse generator 4 as a BCD (Binary Code) value, and a counter value read from the binary counter 2 Memory 6 used for storing or calculating the data, and a timer 3 for generating an interrupt signal when the alarm value stored by the microprocessor 1 is reached.

Referring to the prior art configured in this way in detail as follows.

When the power is turned on, the microprocessor 1 performs the task of initializing the peripheral circuit and then clears the binary counter 2, stores the alarm value in the timer 3, and stores the current counter value. Write it.

At this time, as the turbine and the rotor 5 begin to rotate, the pulse generator 4 checks the number of revolutions of the rotor and generates a pulse corresponding to the number of revolutions. The pulse value is converted into a binary code.

At this time, the timer 3 continuously checks the time and delivers the interrupt signal INT to the microprocessor 1 when the counted value in the zoom reaches the alarm value.

Therefore, the microprocessor 1 again writes the next alarm value to the timer 3 and then reads the counted value from the binary counter 2 and writes it to the memory 6 to store the data value. . It then waits until the interrupt signal (INT) is generated from the timer (3).

When the interrupt signal INT is generated from the timer 3 while in the standby state, the microprocessor 10 writes the next alarm value to the timer 3, and then counts the value of the binary counter 2 counted up to that time. The process of repeatedly reading and writing the data to the memory 6 and storing the data value is performed.

In other words, the operation of the timer 3 is initialized by the microprocessor 1 at power-on as shown in FIG. 2, and the alarm value is stored. When the timer 3 starts counting time, the microprocessor ( 1) waits for the generation of the interrupt signal (INT) that occurs when the alarm value is reached.

Then, when the interrupt signal INT is transmitted from the timer 3 to the microprocessor 1, the microprocessor 1 writes the next alarm value to the timer 3, and then of the next binary counter 2; The binary value is read and written to the memory 6 to store the data value.

Then it exits the interrupt routine and waits until the interrupt signal of the next timer 3 is generated.

However, in the above technique, the microprocessor must be in the ACTIVE state in order to recognize the interrupt signal from the timer and read the binary count value. In this case, power consumption is inefficient and inefficient, and the turbine or the rotor moves. Because of this, there is a problem in that efficiency is reduced due to the hassle and unnecessary operation of continuously performing a READ / WRITE operation by a timer even if a pulse does not occur.

Accordingly, an object of the present invention is to provide a reset detection circuit and a method using an external pulse for minimizing power consumption by checking a state of an external pulse in a power down mode, which is a low power mode of a microprocessor. .

The present invention for achieving the above object is a first step of checking whether the power down mode at the time of the reset signal, and if the step is not the power down mode after performing the initialization operation, the binary count value is read and the power down mode immediately binary A second step of reading a count value, a third step of comparing the count value read in the step with a previous count value, and a new pulse signal is input if the current count value is larger than the previous count value in the step. In the fourth step, it is determined that the current count value is written to the memory, and the power down mode is entered and the reset signal is waited.

As shown in FIG. 4, the configuration for realizing the method consisting of the above steps includes the microprocessor 10 operating in the power down mode while controlling all the circuits in the vicinity, and the operation of the microprocessor 10. A memory 30 for storing a command, an OS program, and temporarily storing a data value changed according to a change of an external device, or outputting the stored information, a timer 20 for generating a constant pulse regardless of other devices; A pulse generator 50 for detecting the rotational speed of the turbine and the rotor 60 and generating pulses according to the rotational speed, and a pulse of the pulse generator 50 and the pulses of the timer 20 are respectively received. It consists of a reset signal generator 70 for generating a and a binary counter 40 for counting the pulses generated from the pulse generator (50).

The reset signal generator 70 outputs an AND gate AD for transmitting or blocking a predetermined pulse of a timer and a pulse of a pulse generator upon falling edge of a pulse transmitted through the AND gate AD. Exclusive flipping (AF / F), the output of the flip-flop (DF / F) and the pulse of the pulse generator exclusive exclusive ring to generate a reset signal (ENR).

When described in detail with respect to the operation and effect of the present invention configured as described above.

When the pulse generator 50 which generates the pulse by the movement as the turbine or the rotor 60 moves generates the pulse a as shown in (b) of FIG. 5, the pulse a is a timer. The pulse b as shown in FIG. 5 (a) generated from (20) passes through the AND gate AD of the reset signal generator 70 to the clock terminal CLK of the deflip-flop DF / F. When it is input to the data input terminal (D) of the flip-flop (DF / F), the clock (CLK) as shown in Fig. 5 (c) when the falling edge as shown in Fig. 5 (d) The pulse d is output through its output terminal Q.

The inverted output Q of the deflip-flop DF / F, i.e., the pull in the low state as shown in FIG. 5 (f) is input to the AND gate AD, The signal b is cut off so that the clock CLK is no longer input.

At this time, the exclusive oar gate (ENR) exclusively rings the output signal (a) of the pulse generator (50) and the output signal (d) of the deflip-flop (DF / F), respectively, and resets the reset signal (e). The output is reset to the reset terminal RST of the microprocessor 10.

In other words, the output Q of the deflip-flop DF / F of the reset signal generator 70 is the output signal b of the timer 20 after the output signal a of the pulse generator 50 is input. Since the falling edge is delayed as it is detected, the exclusive difference gate (ENR) uses the time difference of the signal to generate the reset waveform as shown in FIG. 5 (e) to automatically reset the microprocessor 10.

Then, the microprocessor 10 performs a power down mode (PDM) by detecting a reset signal, which is described below with reference to FIG.

If the microprocessor 10 is reset and the program is executed from the beginning, the initialization operation is omitted when one state is reset in the power down mode. Otherwise, the initialization operation is performed in the case of the first power-up.

The microprocessor 10 reads the value counted up to now from the binary counter 40 that receives the pulse generated from the next pulse generator 50 through the clock terminal CLK, and the value is greater than the previous count value. If it is large, it recognizes as evidence that a new pulse signal has been input and writes and stores the read value in the memory 30, and then returns to the power down mode and keeps the standby state until the next reset signal. If the current count value is not greater than the previous count value, the power immediately returns to the power down mode.

In addition, the present time can be known by reading the value of the timer 30, and the input state of the hourly pulse can be known using the value.

In brief, the operation mode of the microprocessor 10 operates in an active mode that continuously executes a program as long as a voltage state exists, and then resets the program in a power-down mode. Only through signals.

Therefore, when the microprocessor 10 enters the power down mode while operating in the active mode, the microprocessor 10 stops all operations, waits only for the reset signal, and executes the program from the beginning again when the reset signal is input.

As described in detail above, in the present invention, when the microprocessor operates in the active mode at power-on, when the reset signal is input, the microprocessor executes a program from the beginning and does not continue to operate when the operation is completed, and is kept in the standby state until the reset signal comes. When the reset signal is input, the power down mode is repeated to reduce power consumption by about 1/100.

Claims (3)

A microprocessor operating in a power-down mode while controlling all surrounding circuits, and a storage means for storing an OS program of the microprocessor and temporarily storing or outputting data stored in response to changes in an external device. And a timer for counting the current time and transmitting it to the microprocessor and generating a constant pulse irrespective of other devices, and for detecting the rotational speed of the turbine and the rotor and generating a pulse according to the rotational speed. An external pulse comprising a means, a reset signal generating means for receiving a pulse of said pulse generating means and a pulse of a timer, respectively, for generating a reset signal, and a binary counter for counting pulses generated from said pulse generating means. Reset detection circuit using. 2. The apparatus of claim 1, wherein the reset signal generating means comprises: an AND gate for transmitting or blocking a predetermined pulse of the timer, a flip-flop for outputting a pulse of the pulse generator upon falling edge of the pulse transmitted through the AND gate; A reset detection circuit using an external pulse, comprising an exclusive no-gate that generates a reset signal by exclusively ringing the output of the flip-flop and the pulse of the pulse generator. A first step of checking whether the power is in the power down mode when the reset signal is input; and the second step of reading the binary count value after performing an initialization operation if the power is not in the power down mode. And a third step of comparing the count value read in the step with a previous count value, and if the current count value is larger than the previous count value in the step, it is determined that a new pulse signal is input and the current count value is stored in the memory. And a fourth step of entering into the power down mode and waiting for a reset signal and immediately entering the power down mode if it is not large.