KR0144907B1 - MOS transistor manufacturing method having a multilayer gate electrode - Google Patents

Abstract

A method of manufacturing a MOS transistor having a multilayer gate electrode structure is disclosed. The present invention flattens the polysilicon layer, which is the lower layer of the gate electrode, to remove diffused reflections in the inclined portion due to the surface step of the silicide layer, which is the upper layer of the multilayer gate electrode, during the photolithography process for forming the gate electrode. By forming a silicide layer, the manufacturing method of the MOS transistor which can form a desired gate electrode is provided.

Description

MOS transistor manufacturing method having a multilayer gate electrode

1 to 3 are cross-sectional views illustrating a method of manufacturing a MOS transistor having a multilayer gate electrode according to the prior art.

4 through 10 are cross-sectional views illustrating a method of manufacturing a MOS transistor having a multilayer gate electrode according to the present invention.

The present invention relates to a method of manufacturing a MOS transistor having a multi-layered gate electrode structure, in particular, in a highly integrated semiconductor storage having a fine structure, it is possible to prevent a pattern defect by the photo process when forming a multi-layered gate electrode pattern including a metal layer A method for manufacturing a MOS transistor.

As semiconductor devices have been miniaturized and highly integrated, sheet resistance of gates has increased. This causes a slow speed of signal transmission. Therefore, recently, in order to reduce the sheet resistance of the gate electrode, a polyside layer including a low resistance metal layer is widely used as a material for forming the gate electrode. However, the polyside layer has a step of 1000 GPa to 2000 GPa as it is by the field oxide layer for device isolation. As a result, there is a problem of causing a pattern defect due to diffuse reflection during the photolithography process for forming the gate electrode.

1 to 3 are cross-sectional views illustrating a method of manufacturing a MOS transistor according to the prior art.

FIG. 1 shows a step of performing an exposure process after applying the photoresist layer 21 to pattern the gate electrode. Specifically, after forming the field oxide layer 12 for device isolation on the semiconductor substrate 10 to define the active region and the inactive region, the gate insulating layer 14 is formed. Next, a polysilicon layer 16, a silicide 18, and an oxide layer 20 are sequentially deposited on the entire surface of the semiconductor substrate having the surface stepped by the field oxide layer 12, and then a photoresist is formed on the entire surface of the oxide layer 20. Layer 21 is applied. As the silicide layer 18, a tungsten silicide layer is widely used. An exposure process using a gate mask is then performed to pattern the gate electrode. At this time, diffused reflection of light is generated by the inclined surface of the silicide layer 18 in which the arrow inside the circle indicated by the reference mark A is formed, which forms a pattern to obtain the hatched portion.

FIG. 2 shows the step of patterning to form a gate electrode. The photoresist layer 21 is developed to form a photoresist pattern (not shown). Subsequently, the oxide layer pattern 20a is formed using the photoresist layer pattern as a mask. Next, the silicide 18 and the polysilicon layer 16 are etched using the oxide layer pattern 20a as a mask to form the silicide layer pattern 18a and the polysilicon layer pattern 16a. At this time, as described in FIG. 1, the photoresist layer 21 exhibits a pattern defect after the development process due to diffuse reflection of light, which prevents the oxide layer pattern 20a from having a shape desired to be obtained, and thus has a crushed shape. Have it. Accordingly, the silicide layer pattern 18a and the polysilicon layer pattern 16a obtained by using the oxide layer pattern 20a as an etching mask are also formed like the inside of the circle indicated by the reference B. Next, a low concentration of impurities are implanted into the entire surface of the resultant product, followed by annealing to form the impurity region 22.

FIG. 3 illustrates a step of completing a MOS transistor. An insulating layer, for example, an oxide layer is deposited on the entire surface of the semiconductor substrate on which the impurity region 22 is formed, and then anisotropically etched to form the polysilicon pattern 16a and the silicide layer. The spacers 24 are formed on the pattern 18a and the sidewalls of the oxide layer pattern 20a. Next, the gate insulating layer 14 over the predetermined impurity region 22 is etched by a conventional method to form a contact hole, and then a MOS transistor for forming a pad layer 26 filling the contact hole is completed.

As described above, in the MOS transistor manufacturing method according to the related art, the silicide layer constituting the gate electrode has a step by the field oxide layer below it. This step causes diffuse reflection in the photolithography process for patterning the gate electrode, thereby forming an unwanted photoresist layer pattern. Therefore, this pattern defect affects the etching process for forming the gate electrode of the subsequent process, and as a result, the desired pattern of the gate electrode cannot be obtained.

Accordingly, an object of the present invention is to manufacture a MOS transistor which can prevent a pattern defect due to diffuse reflection on the surface of the silicide layer on the top thereof by planarizing the polysilicon layer constituting the gate electrode during the photolithography process for forming the gate electrode. To provide a method.

The present invention to achieve the above object,

Forming a field oxide layer for device isolation on a semiconductor substrate:

Sequentially forming a gate insulating layer and a polysilicon layer on the entire surface of the semiconductor substrate having the surface step formed by the field oxide layer:

Planarizing the polysilicon layer:

Sequentially forming a silicide layer and an oxide layer on an entire surface of the substrate on which the planarized polysilicon layer is formed:

Patterning the oxide layer to form an oxide layer pattern:

Forming a polysilicon layer pattern and a silicide layer pattern by etching the planarized polysilicon layer and the silicide layer using the oxide layer pattern as a mask, wherein the multi-layer gate including the polysilicon layer pattern and the silicide layer pattern A MOS transistor manufacturing method of a semiconductor device having an electrode is provided.

According to the present invention, the desired gate electrode can be patterned by flattening the polysilicon layer constituting the gate electrode and removing diffuse reflection on the surface of the silicide layer formed thereon.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

4 through 10 are cross-sectional views illustrating a method of manufacturing a MOS transistor having a multilayer gate electrode according to the present invention.

4 illustrates forming polysilicon 36. After the field oxide layer 32 is formed on the semiconductor substrate 30, the gate insulating layer 43 and the polysilicon layer 36 are sequentially formed on the entire surface of the semiconductor substrate having the step formed by the field oxide layer 32.

5 illustrates the step of planarizing the polysilicon layer 36 to form a planarized polysilicon layer 36a. Specifically, the present invention is flattened by a chemical mechanical polishing (CMP) method unlike the prior art. At this time, the polysilicon layer 36 is etched and planarized until the field oxide layer 32 is exposed or etched and planarized until it has a predetermined thickness on the field oxide layer 36.

FIG. 6 illustrates a step of depositing an oxide layer 40. A silicide layer 38 such as a tungsten silicide layer and an oxide layer 40 are sequentially deposited on the entire surface of the semiconductor substrate on which the planarized polysilicon layer 36a is formed.

FIG. 7 illustrates the step of patterning to form a gate electrode. The oxide layer pattern 40a is formed by patterning the oxide layer 40 using a photo / etch process. Next, the silicide layer pattern 38a and the polysilicon layer pattern 36b are formed by etching the silicide layer 38 and the planarized polysilicon layer 36a using the oxide layer pattern 40a as a mask. Next, an impurity ion is implanted into the entire surface of the resultant using the field oxide layer 32 and the oxide layer pattern 40a as a mask, followed by annealing to form an impurity region 41. At this time, the impurity ion implantation is carried out with one of N-type ions and P-type ions with a dose of 1.0E12 ions / cm ² to 1.0E14 ions / cm ² .

8 shows forming the silicide layer pattern 38b modified as necessary, so that the silicide layer pattern 38a has a better isolation from the conductive layer formed around it by a subsequent process. If necessary, both ends of the silicide layer pattern 38a are etched by an isotropic etching process to form a modified silicide layer pattern 38b. At this time, the etching solution during the isotropic etching process using ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂₎ and water, a mixed solution (H ₂ 0).

FIG. 9 illustrates forming a contact hole 43. An insulating layer, for example, an oxide layer is deposited on the entire surface of the semiconductor substrate on which the modified silicide layer pattern 38b is formed, and then anisotropically etched to form the polysilicon layer pattern 36b. ), A spacer 42 is formed on sidewalls of the modified silicide layer 38b and the oxide layer pattern 40a. Next, the gate insulating layer 34 over the impurity region 41 is etched to form a contact hole 43 for forming a source / drain electrode.

FIG. 10 illustrates the polysilicon layer pattern 36b and the modified silicide layer pattern 38b by forming a pad layer 44 which serves as a source / drain electrode while filling the contact hole 43. Shows a step of completing the MOS transistor of the present invention to form a gate electrode.

According to the embodiment of the present invention described above, a planar silicide layer surface can be obtained by planarizing the polysilicon layer, which is the lower layer of the multilayer gate electrode, and then forming the silicide layer, which is the upper layer. This can greatly reduce the diffuse reflection on the surface of the silicide layer during the photolithography process for forming the gate electrode using the gate mask, thereby patterning the desired gate electrode. In addition, by removing both ends of the silicide layer pattern, it is possible to further improve the isolation state between the conductive layer and the gate electrode by a subsequent process, thereby preventing a decrease in yield due to a short circuit between the conductive layer and the gate electrode.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (5)

Forming a field oxide layer for device isolation on the semiconductor substrate: sequentially forming a gate insulating layer and a polysilicon layer on an entire surface of the semiconductor substrate having a surface step formed by the field oxide layer: planarizing the polysilicon layer: Forming a silicide layer and an oxide layer on the entire surface of the substrate on which the planarized polysilicon layer is formed: forming an oxide layer pattern by patterning the oxide layer: and the planarized polysilicon layer and the oxide layer pattern as a mask Forming a polysilicon layer pattern and a silicide layer pattern by etching the silicide layer, wherein the polysilicon layer pattern and the silicide layer pattern have a multi-layered gate electrode. The method of claim 1, wherein after forming the polysilicon layer pattern and the silicide layer pattern, forming an impurity region by ion implantation of impurities using the field oxide layer and the oxide layer pattern as a mask: the polysilicon layer Forming a spacer on a sidewall of the pattern, the silicide layer pattern, and the oxide layer pattern: forming a contact hole by etching the gate insulating layer formed on the impurity region; and forming a pad layer filling the contact hole And further comprising a multi-layered gate electrode composed of the polysilicon layer pattern and the silicide layer pattern. The method of claim 1, wherein the polysilicon layer is planarized by a chemical mechanical polishing (CMP) method. The MOS transistor of claim 1, wherein when the polysilicon layer is planarized, the MOS transistor of the semiconductor device is etched and planarized until the field oxide layer is exposed, or etched and planarized until it has a predetermined thickness on the field oxide layer. Manufacturing method. The MOS transistor of claim 2, further comprising forming an undercut by etching both ends of the silicide layer pattern by an isotropic etching process before forming the spacer. Way.