KR100734260B1 - Method for fabricating MOS transistor using double spacer - Google Patents

Abstract

According to the manufacturing method of the MOS transistor of this invention, a 1st oxide film, a 1st insulating film, a 2nd oxide film, and a 2nd insulating film are formed in order on a semiconductor substrate. A portion of the second insulating film, the second oxide film, the first insulating film, and the first oxide film is sequentially removed to form an opening that exposes a portion of the surface of the semiconductor substrate. A first spacer covering side surfaces of the first oxide film, the first insulating film, and the second oxide film in the opening is formed. A second spacer covering side surfaces of the first spacer, the second oxide film, and the second insulating film in the opening is formed. A gate insulating film and a gate conductive film pattern are formed in the opening surrounded by the second spacer. The second insulating film, the second oxide film, and the first spacer are removed to expose a portion of the surface of the semiconductor substrate covered by the first spacer. A halo ion implantation process is performed at an oblique angle over some surfaces of the exposed semiconductor substrate. The first insulating film and the first oxide film are sequentially removed. Low concentration impurity ions are implanted into the semiconductor substrate at a predetermined angle using the second spacer and the gate conductive layer pattern as an ion implantation mask. High concentration impurity ions are vertically implanted into the semiconductor substrate using the second spacer and the gate conductive film pattern as an ion implantation mask. The implanted impurity ions are diffused to form a halo region, a low concentration source / drain region, and a high concentration source / drain region.

Description

Method for fabricating MOS transistor using double spacer

1 to 7 are cross-sectional views illustrating a method of manufacturing a MOS transistor according to the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a MOS transistor using a double spacer.

In recent years, as the integration of semiconductor devices increases, the channel length of metal oxide semiconductor (MOS) transistors is also getting shorter. However, as the channel length is shortened, performance problems and process problems are on the rise.

The dual process problems are mostly related to the photolithography process. That is, as an example, in the case of performing a photolithography process for forming a gate conductive layer in a fine pattern, the finer the pattern is, the more likely it is to cause various misalignments, and because of irregular CD (Critical Dimension) control in the wafer, Devices having different characteristics for each tooth are made, thereby decreasing process uniformity.

On the other hand, among the problems in performance, the thickness of the gate insulating film formed below the edge of the gate conductive film is reduced as an example, thereby increasing the capacitance component of the gate insulating film, causing a problem that the operation speed of the transistor is slowed. This will be described in more detail using a formula as follows. Equation 1 below is a formula showing the capacitance component of the gate insulating film.

Where C is the capacitance of the gate insulating film, ε ₀ and ε _ox are the dielectric constants, A is the cross section, and T _ox is the thickness.

As can be seen from Equation 1, as the thickness T _ox of the gate insulating film decreases, the capacitance C increases. Since this capacitance is inversely related to the time constant, the larger the capacitance, the slower the operation of the device.

Therefore, in order to suppress the reduction of the thickness of the gate insulating film at the edge of the gate conductive film as described above, after forming the gate conductive film made of the polysilicon film, the oxidation process of the polysilicon film is performed again, followed by the heat treatment process. Method was used. However, due to the oxidation process for the polysilicon film, the saturation current I _dsat may be reduced because the impurity diffusion is not sufficiently achieved in the subsequent ion implantation process due to the rather thick oxide film. The heat treatment process may be performed to intensify impurity diffusion, but this makes it difficult to form a shallow junction.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a MOS transistor using a double spacer to reduce a channel length and to suppress performance and process problems in the related art.

In order to achieve the above technical problem, a method of manufacturing a MOS transistor according to the present invention comprises the steps of sequentially forming a first oxide film, a first insulating film, a second oxide film and a second insulating film on a semiconductor substrate; Sequentially removing portions of the second insulating film, the second oxide film, the first insulating film, and the first oxide film to form an opening exposing a part surface of the semiconductor substrate; Forming a first spacer covering side surfaces of the first oxide film, the first insulating film, and the second oxide film in the opening; Forming a second spacer covering side surfaces of the first spacer, the second oxide film, and the second insulating film in the opening; Forming a gate insulating film and a gate conductive film pattern in an opening surrounded by the second spacer; Removing the second insulating film, the second oxide film, and the first spacer to expose a portion of the surface of the semiconductor substrate covered by the first spacer; Performing a halo ion implantation process at an oblique angle on a portion of the exposed surface of the semiconductor substrate; Sequentially removing the first insulating film and the first oxide film; Implanting low concentration impurity ions into the semiconductor substrate at a predetermined angle using the second spacer and the gate conductive layer pattern as an ion implantation mask; Implanting high concentration impurity ions vertically into the semiconductor substrate using the second spacer and the gate conductive layer pattern as an ion implantation mask; And diffusing the implanted impurity ions to form a halo region, a low concentration source / drain region, and a high concentration source / drain region.

The method may further include forming a first silicide layer on the gate conductive layer pattern and a second silicide layer on the low concentration source / drain region and the high concentration source / drain region.

The first insulating film, the second insulating film, and the second spacer may be formed using a nitride film.

The first spacer may be formed using an oxide film.

The forming of the first spacer may include forming a third oxide film covering the first oxide film, the first insulating film, the second oxide film, the second insulating film, and the exposed semiconductor substrate in the opening, and the second insulating film. Anisotropically etching the third oxide film until the upper surface is exposed to form the first spacer.

The forming of the second spacer may include forming a third insulating film covering the first spacer, the second oxide film, the second insulating film, and the exposed semiconductor substrate, and until the upper surface of the second insulating film is exposed. Anisotropically etching the third insulating film to form a second spacer.

The implantation angle at which the low concentration impurity ions are implanted is preferably an angle at which an overlapping area between the gate conductive layer pattern and the low concentration source / drain region can be minimized.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

1 to 7 are cross-sectional views illustrating a method of manufacturing a MOS transistor according to the present invention.

First, referring to FIG. 1, a first oxide film 101, a first insulating film 102, a second oxide film 103, and a second insulating film 104 as a pad oxide film are sequentially formed on a semiconductor substrate 100. The first oxide film 101 is formed to have a thickness of about 100-300Å, the first insulating film 102 is formed to have a thickness of about 100-300Å, and the second oxide film 103 is formed to have a thickness of about 500Å. And, the second insulating film 104 is formed to have a thickness of approximately 1500Å. The first insulating film 102 and the second insulating film 104 are formed of a nitride film. Next, a photoresist film pattern 105 is formed on the second insulating film 104. The photoresist film pattern 105 has an opening 106 exposing a portion of the surface of the second insulating film 104.

Next, referring to FIG. 2, an etching process using the photoresist film pattern 105 of FIG. 1 as an etching mask is performed to form the second insulating film 104, the second oxide film 103, and the first insulating film 102. And the exposed portions of the first oxide film 101 are sequentially removed. When the etching process is finished, a part of the surface of the semiconductor substrate 100 is exposed, and then the photoresist film pattern 105 is removed. Next, a third oxide film 108 is formed over the entire surface. The third oxide film 108 is formed to a thickness of approximately 500 GPa, and after the third oxide film 108 is formed, the openings 106 in FIG. 1 become openings 107 having smaller widths.

Next, referring to FIG. 3, anisotropic etching of the third oxide film 108 of FIG. 2 is performed to form a first spacer on side surfaces of the first oxide film 101, the first insulating film 102, and the second oxide film 103. 109 is formed. In order to form the first spacer 109, the anisotropic etching is performed until a part of the surface of the semiconductor substrate 100 and the top surface of the second insulating layer 104 are completely exposed. The height of the first spacer 109 is about 1000 mm or less, and the thickness is about 500 mm or less. After the first spacer 109 is formed, a third insulating film 110 is formed on the entire surface to have a thickness of about 500-1000 Å. The third insulating film 110 is formed using a nitride film.

Next, referring to FIG. 4, anisotropic etching is performed on the third insulating layer 110 to form a second spacer 111. In order to form the second spacer 111, the anisotropic etching is performed until a part of the surface of the semiconductor substrate 100 and an upper surface of the second insulating layer 104 are completely exposed. After the etching is finished, the second anisotropic etching is performed. The spacer 111 covers the side surfaces of the first spacer 109, the second oxide film 103, and the second insulating film 104. At this time, the thickness of the second spacer 111 is approximately 200 mm.                     

Next, referring to FIG. 5, a gate insulating layer 112 is formed on the exposed surface of the semiconductor substrate 100. The gate insulating film 112 is formed using an oxide film. Next, the gate conductive film pattern 113 is formed by filling the inside surrounded by the second spacer 111 with a gate conductive film such as a polysilicon film. In order to form the gate conductive layer pattern 113, a damascene process is used. That is, a gate conductive film is formed over the entire surface of the resultant having an opening exposing the gate insulating film 112. A portion of the gate conductive film is removed until the second insulating film 104 is exposed using a planarization process. As a result, the gate conductive layer pattern 113 is formed.

Next, referring to FIG. 6, the second insulating film 104 (in FIG. 5) is selectively removed, and then the second oxide film (103 in FIG. 5) is also selectively removed. When the second oxide layer 103 is removed, the first spacer 109 made of the same material is also removed. That is, a notch for exposing the surface of the semiconductor substrate 100 between the first oxide film 101 and the lower end of the second spacer 111 is formed. Next, a halo ion implantation process (indicated by an arrow in the drawing) is performed using the first insulating film 102 as an ion implantation mask. In the case of an n-channel MOS transistor, n-type impurity ions are implanted, and in the case of a p-channel MOS transistor, p-type impurity ions are implanted.

Next, referring to FIG. 7, the first insulating film 102 of FIG. 6 and the first oxide film 101 are sequentially removed. At this time, the second spacer 111 made of the same material is also removed by a predetermined thickness when the first insulating layer 102 is removed. In order to form a lightly doped drain (LDD), a low concentration of impurity ions are implanted at a slight angle. In the case of an n-channel MOS transistor, n-type impurity ions are implanted, and in the case of a p-channel MOS transistor, p-type impurity ions are implanted. Subsequently, a high concentration of impurity ions are implanted vertically. In this case, n-type impurity ions are implanted in the case of the n-channel MOS transistor, and p-type impurity ions are implanted in the case of the p-channel MOS transistor. After the impurity ion implantation processes are performed, a diffusion process is performed to form the halo region 114, the low concentration source / drain region 115, and the high concentration source / drain region 116. In this case, the implantation angle of the low concentration impurity ions may be adjusted to minimize the area where the low concentration source / drain region 115 and the gate insulating layer 112 overlap each other. Thus, the gate conductive layer pattern 113 and the source / drain region ( The overlapping capacitances 115 and 116 can be minimized. Next, a first silicide layer 117 is formed on the gate conductive layer pattern 113 by performing a conventional metal silicide process, and at the same time, the second silicide layer is formed on the low concentration source / drain region 115 and the high concentration source / drain region 116. The silicide film 118 is formed. In this case, since the lower portion of the second spacer 111 is recessed, the second silicide layer 117 may be formed not only on the high concentration source / drain region 116 but also on the low concentration source / drain region 115. Accordingly, the resistance R _sd between the source and the drain may be reduced. Next, the usual metal wiring process is performed.

As described above, according to the method of manufacturing the MOS transistor using the double spacer according to the present invention has the following advantages.

First, since the gate conductive layer pattern is formed using the damascene process, it is easy to form a fine pattern.

Second, the area where the low concentration source / drain region overlaps with the gate insulating layer may be minimized by adjusting the implantation angle of low concentration impurity ions, thereby minimizing the capacitance where the gate conductive layer pattern and the source / drain region overlap. .

Third, since the lower portion of the second spacer is recessed, the silicide layer may be formed not only on the high concentration source / drain region but also on the low concentration source / drain region, thereby reducing the resistance between the source and the drain.

Claims (7)

Sequentially forming a first oxide film, a first insulating film, a second oxide film, and a second insulating film on a semiconductor substrate; Sequentially removing portions of the second insulating film, the second oxide film, the first insulating film, and the first oxide film to form an opening exposing a part surface of the semiconductor substrate; Forming a first spacer covering side surfaces of the first oxide film, the first insulating film, and the second oxide film in the opening; Forming a second spacer covering side surfaces of the first spacer, the second oxide film, and the second insulating film in the opening; Forming a gate insulating film and a gate conductive film pattern in an opening surrounded by the second spacer; Removing the second insulating film, the second oxide film, and the first spacer to expose a portion of the surface of the semiconductor substrate covered by the first spacer; Performing a halo ion implantation process at an oblique angle on a portion of the exposed surface of the semiconductor substrate; Sequentially removing the first insulating film and the first oxide film; Implanting low concentration impurity ions into the semiconductor substrate at a predetermined angle using the second spacer and the gate conductive layer pattern as an ion implantation mask; Implanting high concentration impurity ions vertically into the semiconductor substrate using the second spacer and the gate conductive layer pattern as an ion implantation mask; And Diffusing the implanted impurity ions to form a halo region, a low concentration source / drain region, and a high concentration source / drain region. The method of claim 1, And forming a first silicide layer on the gate conductive layer pattern and a second silicide layer on the low concentration source / drain regions and the high concentration source / drain regions. The method of claim 1, And the first insulating film, the second insulating film, and the second spacer are formed using a nitride film. The method of claim 1, The first spacer is formed by using an oxide film. The method of claim 1, wherein the forming of the first spacer comprises: Forming a third oxide film covering the first oxide film, the first insulating film, the second oxide film, the second insulating film, and the exposed semiconductor substrate in the opening; And And anisotropically etching the third oxide film until the upper surface of the second insulating film is exposed to form the first spacer. The method of claim 1, wherein the forming of the second spacer comprises: Forming a third insulating film covering the first spacer, the second oxide film, the second insulating film, and the exposed semiconductor substrate; And And anisotropically etching the third insulating film until the upper surface of the second insulating film is exposed, thereby forming a second spacer. The method of claim 1, And a implantation angle at which the low concentration impurity ions are implanted is an angle at which an overlap area between the gate conductive layer pattern and the low concentration source / drain region is minimized.

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