KR0142961B1 - Internal source voltage generator circuit - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

The present invention relates to an internal power supply voltage generation circuit for supplying a power supply voltage to a circuit inside the chip.

2. The technical problem to be solved by the invention:

Conventionally, in order to reduce current consumption in the standby state, the standby internal power supply voltage generation circuit and the active internal power supply voltage generation circuit have to be divided. As a result, current consumption is reduced while chip area is greatly increased.

3. Summary of the solution of the invention:

In the present invention, the operation of the active and standby internal power supply voltage generation circuits performed by the conventional internal power supply voltage generation circuit in one circuit by using the second current source means operating in the active state by changing the circuit arrangement slightly. It was possible to perform without difficulty.

4. Important uses of the invention:

Since the integrated internal power supply voltage generation circuit is provided, the chip area can be significantly reduced, thereby implementing a semiconductor memory device which is advantageous for high integration.

Description

Integrated internal power supply voltage generation circuit

1 is a circuit diagram showing a conventional internal power supply voltage generation circuit.

2 is a circuit diagram showing an internal power supply voltage generation circuit according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

100: internal power supply voltage generation circuit for standby

200: active internal power supply voltage generation circuit

20, 50, 60: current mirror comparator.

41, 80: activation circuit 46: control circuit

72: first current source means 74: second current source means

The present invention relates to an internal power supply voltage generation circuit of a semiconductor memory for supplying a power supply voltage to a chip, and in particular, when a standby internal power supply voltage generation circuit and an active internal power supply voltage generation circuit are configured as a single circuit to activate and deactivate the circuit. It relates to a common internal power supply voltage generation circuit that can be used in common.

In the field of semiconductor integrated circuits in which semiconductor devices such as MOS transistors are integrated, the integration density has been increasing every year. For example, in semiconductor memories such as dynamic random access memory (DRAM) and static random access memory (SRAM), memory devices of tens to hundreds of megabits have been developed. Circuits and devices incorporating transistors used in such ultra high density memory devices, for example, transistors used in memory cells and peripheral circuits such as sense amplifiers, precharge circuits and control circuits, are as small as submicrons. It must be manufactured.

Therefore, the channel length of the transistors must also be reduced to an extremely small submicron level. In such a case, problems such as punch through between the source and drain of the transistors and degradation of the gate oxide film present in the transistors occur when a normal voltage supply voltage is used, for example 5 volts. To solve such problems, an internal power supply voltage generation circuit for converting an external power supply voltage such as an external power supply voltage of 5 volts into an internal power supply voltage such as 3 to 4 volts to an internal power supply voltage of typically about 3.5 volts is a semiconductor integrated circuit of the same chip. It has been used in devices. In general, the internal power supply voltage generation circuit is divided into a standby internal power supply voltage generation circuit that always operates when an external power supply voltage is applied, and an active internal power supply voltage generation circuit that operates only in an activated state. The reason why the standby power supply internal power supply voltage generation circuit is separately provided as described above is to reduce the current consumed in the standby circuit as much as possible. The internal power supply voltage generation circuit is widely known through various papers, journals, and numerous patent applications.

The circuit shown in FIG. 1 is a circuit diagram of an internal power supply voltage generation circuit according to the prior art.

Referring to FIG. 1, the internal power supply voltage generation circuit includes a standby internal power supply voltage generation circuit 100 and an active internal power supply voltage generation circuit 200.

The standby internal power supply voltage generation circuit 100 includes a comparator 20 in which the channel transistors 2 and 4 and the N channel transistors 6.8 are combined and the N channel transistor 12 which is a current source means. And a current mirror type differential amplifier and a channel transistor such as a driving transistor 10. Sources of the channel transistors 2 and 4 constituting the comparator 20 are connected to an XVcc pad which is an external power supply voltage terminal on the same chip and source of the N-channel transistor 2 which is the current source means. Is connected to the Vss pad which is the ground power supply terminal. Gates of the channeled transistors 2 and 4 are connected to each other and are commonly connected to the drain of the channeled transistor 4. The drains of the N-channel transistors 6 and 8 are connected to the drains of the channeled transistors 2 and 4, respectively, and the sources of the N-channel transistors 6 and 8 are mutually connected. Connected to the drain of the N-channel transistor 12 in common. The drain connection point 14 of the channel transistor 2 and the N-channel transistor 6 is connected to the control electrode of the control transistor 10 through a conductive line. The source and drain of the driving transistor 10 are connected to the external power supply voltage terminal and the internal power supply voltage output line 16, respectively. The internal power supply voltage output line 16 is connected to the control electrode of the N-channel transistor 8 and the control electrode of the N-channel transistor 6 is connected to the reference voltage Vref, for example 3.5 volts, which is transmitted from a reference voltage generating circuit (not shown). It is. The reference electrode of the N-channel transistor 12 is also connected to a reference voltage Vref.

The active internal power supply voltage generation circuit 200 is a comparator 50 and a current source means in which the channel transistors 22 and 24 and the N channel transistors 26 and 28 and the channel transistor 30 are combined. A current mirror type differential amplifier composed of the N-channel transistor 34, an activation circuit 41 for inputting a channel transistor, for example, a driving transistor 32, and a control signal B, and the N-channel transistor 34. The discharge control circuit 46 is connected to the control electrode. The sources of the P-channel transistors 22 and 24 constituting the comparator 50 are connected to an XVcc pad which is an external power supply voltage terminal on the same chip and the source of the N-channel transistor 34 serving as the current source means. Is connected to the Vss pad which is the ground power supply terminal. The gates of the channeled transistors 22 and 24 are connected to each other and are commonly connected to the drain of the channeled transistor 24. The drains of the N-channel transistors 26 and 28 are connected to the drains of the channeled transistors 22 and 24, respectively, and the sources of the N-channel transistors 26 and 28 are mutually connected. Connected to the drain of the N-channel transistor 34 in common. The drain connection point 25 of the P-channel transistor 22 and the N-channel transistor 26 is connected to the control electrode of the driving transistor 32 through a conductive line. The source and the drain of the driving transistor 32 are connected to the external power supply voltage terminal and the internal power supply voltage output line 48, respectively. The internal power supply voltage output line 48 is connected to the control electrode of the N-channel transistor 28 and the control electrode of the N-channel transistor 26 is connected to the reference voltage Vref, for example 3.5 volts, which is transmitted from a reference voltage generating circuit (not shown). It is. The channel of the channel transistor 30 is connected between the connection contacts 27 of the comparator 50. The output of the activation circuit 41 is transmitted to the control electrode of the channel transistor 30. The activation circuit 41 receives the outputs of the inverters 36 and 38, which input the control signal B generated in the activation state, to the control electrode, and the source and drain of the channel transistor 22 constituting the comparator 50. And a channel transistor 46 to which a source and a drain are respectively connected. The inverters 36 and 38 are conventional inverter circuits. The discharge control circuit 46 is composed of inverters 42 and 44 connected between the internal power supply voltage output line 48 and the ground voltage terminal. The inverters 42 and 44 have a control signal A connected to an input terminal and an output terminal connected to a control electrode of the N-channel transistor 34.

As shown in FIG. 1, the internal power supply voltage generation circuit having the above-described configuration is divided into a standby 100 and an active 200, and a plurality of elements are connected to each other. It also occupies a large area. Therefore, it acts as a deadly weak point in the current semiconductor memory device in the trend of high integration.

Accordingly, an object of the present invention is to provide an internal power supply voltage generation circuit having a reduced chip area.

In order to achieve the object of the present invention, the internal power supply voltage generation circuit according to the present invention,

A comparator connected between an external power supply voltage terminal and a ground voltage terminal and inputting a reference voltage and an internal supply voltage having a predetermined voltage level to compare the two input voltages;

A first current source means for inputting a reference voltage and controlling the output voltage of the comparator according to a comparison result of the comparator;

A driving transistor for responding to the output of the comparator and controlling the magnitude of the internal supply voltage according to the comparison result of the comparator;

An activation circuit connected between the driving transistor and a ground voltage terminal and supplying the external power voltage in an activation state in response to a control signal detecting an activation state;

In response to the output of the activation circuit is characterized in that the merged internal power supply voltage generation circuit comprising a second current source means for controlling the output voltage size of the comparator in the active state according to the comparison result of the comparator.

Hereinafter, a preferred embodiment of an internal power supply voltage generation circuit according to the present invention will be described with reference to the accompanying drawings.

2 is a circuit diagram illustrating an internal power supply voltage generation circuit according to an embodiment of the present invention.

The circuit configuration of the present invention is similar to the internal power supply voltage generation circuit 100 for standby which constitutes FIG. That is, the internal power supply voltage generation circuit according to the embodiment of the present invention includes a comparator 60 in which the P-channel transistors 62 and 64 and the N-channel transistors 66 and 68 are combined, and the N-channel as the first current source means. A current mirror type differential amplifier comprising a transistor 72 and an en-channel transistor 74 serving as a second current source means, and a channel transistor such as a driving transistor 70 and an activation circuit 80. have. Sources of the P-channel transistors 62 and 64 constituting the comparator 60 are connected to a Vss pad which is an external power supply voltage terminal on the same chip and the N-channel transistor 72 serving as the first current source means. The source of the N-channel transistor 74, which is the source of the second transistor and the second current source means, is connected to the Vss pad, which is the ground power supply terminal. The gates of the channeled transistors 62 and 64 are connected to each other and are commonly connected to the drain of the channeled transistor 64. The drains of the N-channel transistors 66 and 68 are connected to the drains of the channel transistors 62 and 64, respectively, and are in common with the drains of the N-channel transistors 72 and 74. Connected. The drain connection point 65 of the channel transistor 62 and the N-channel transistor 66 is connected to the control electrode of the driving transistor 70 through a conductive line. The source and drain of the drive transistor 70 are connected to the external power supply voltage terminal XVCC and the internal power supply voltage output line 82, respectively. The internal power supply voltage output line 82 is connected to the control electrode of the N-channel transistor 68 and the control electrode of the N-channel transistor 66 is connected to the reference voltage Vref, for example, 3.5 volts transmitted from a reference voltage generating circuit (not shown). It is. A gate voltage of the N-channel transistor 72 is also connected to a reference voltage Vref. The activation circuit 80 is composed of inverters 76 and 78 configured between the output line 82 and the ground voltage terminal VSS. A control signal generated in an activation state is input to an input terminal of the activation circuit 80, and an output terminal is connected to a control electrode of the N-channel transistor 74. The control signal B is a low enable signal generated in synchronization with a row address strobe signal or a column address strobe signal transitioned to 'low' in an activated state.

The internal power supply voltage generating circuit according to the embodiment of the present invention having the above configuration has a single circuit configuration, which is the second current source means in order to perform the operation of the internal power supply voltage generating circuit without difficulty in the above-described prior art. The size of the channel transistor and the size of the inverter constituting the activation circuit must be increased. As a result, since the operation of the standby internal power supply voltage generator circuit and the active internal power supply voltage generator circuit are implemented as one circuit, the internal power supply voltage generator circuit, which is reduced in chip area, is implemented.

Claims (5)

In an internal power supply voltage generation circuit of a semiconductor memory that converts an external power supply voltage used outside the chip into an internal power supply voltage adaptively inside the chip, the reference voltage having a predetermined voltage level connected between an external power supply voltage supply terminal and a ground voltage terminal. A comparator for comparing the two input voltages by inputting an internal supply voltage and an internal supply voltage, first current discharge means for inputting a reference voltage and controlling an output voltage of the comparator according to a comparison result of the comparator, and an output of the comparator A driving transistor for controlling the magnitude of the internal supply voltage according to the comparison result of the comparator, an activation circuit connected between the internal supply voltage terminal and the ground voltage terminal and responsive to a control signal sensing an activation state; The output voltage of the comparator in an active state responsive to the output of the circuit and according to the comparison result of the comparator And a second current source means for controlling the power supply. The integrated internal power supply voltage generation circuit according to claim 1, wherein the integrated internal power supply voltage generation circuit constitutes a CMOS transistor. The merge internal power supply voltage generation circuit according to claim 1, wherein the control signal is a signal generated in synchronization with a row address strobe signal or a column address strobe signal for activating a chip. The integrated internal power supply voltage generation circuit according to claim 1, wherein the activation circuit is a CMOS inverter circuit for inputting the control signal. 2. The integrated internal power supply voltage generation circuit according to claim 1, wherein said first and second current source means are enMOS transistors.