KR0129202B1 - Dual back bias supply circuit - Google Patents

Abstract

A dual back bias supply circuit includes a bias section, a standby/active clamping section, a low level/high level back bias generating section, a select controlling section and a back bias selecting section. The dual back bias supply circuit supplies a high back bias voltage generated by the high level back bias generating section to a P well of a DRAM, to reduce leakage current in case of standby mode or when low power driving is required, and supplies a low back bias voltage generated by the low level back bias generating section in case of active mode, to increase signal transmission speed.

Description

Dual Backbias Supply Circuit

1 is a dual back bias supply circuit of the present invention.

2 is a partial detail of FIG.

3 is a timing diagram for the selection controller of FIG.

4 is a partial detail of FIG.

(a) is a detailed view of a low level back bias generator.

(b) is a detailed view of the high level back bias generator.

(c) and (d) are degassing circuit diagrams for the oscillator in (b).

* Explanation of symbols for main parts of the drawings

201: standby clamping portion 202: active clamping portion

203: bias section 204: low level back bias generation section

205: high level back bias generator 206: selection controller

207: Back bias selection unit 300: DRAM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual back bias supply circuit, and in particular, a back bias voltage (VBB) according to a mode of DRAM in order to reduce leakage current in a DRAM which is a low power memory device. A dual back bias supply circuit for differentially supplying In general, DRAM memory devices supply a back bias voltage to a P-substrate so that reverse bias is applied to the PN junction of the NMOS transistor that forms the DRAM, thereby reducing leakage current in the DRAM and reducing the current. It is trying to stabilize. Conventionally, the back bias voltage is supplied in the same size in the active mode and the standby node of the DRAM, and in particular, the low back bias voltage (4 μA or more) is supplied. As a result of supplying such a low back bias voltage, conventionally, there is a problem in that the leakage current (inversely proportional to the back bias voltage) increases in the standby mode, thereby increasing the power consumption. The present invention has been devised in view of these conventional problems. It is an object of the present invention to reduce leakage current by supplying a high back bias voltage to the DRAM in the standby mode, and to provide a low back bias voltage in the active mode to prevent the speed drop due to the high threshold voltage. To provide an Earth supply. Another object of the present invention is to provide a double back bias supply circuit which makes it easy to change the back bias voltage by using P wells instead of P substrates. According to the above objects, the present invention provides a double back bias supply circuit comprising: a bias unit for generating a high level bias voltage, a standby clamping unit for clamping a high level bias voltage of the bias unit to output a standby clamp voltage; An active clamping unit for clamping a bias voltage of a high level of the bias unit to output an active clamp voltage lower than the standby clamp voltage, and an active clamp voltage of the active clamping unit as a low back bias voltage. A low level back bias generator for outputting, a high level back bias generator for outputting a high back bias voltage by inputting a standby clamp voltage of the standby clamping unit, and a high back output from the high level back bias generator Bias Voltage and the Low Level Back The back bias selection unit selects a low back bias voltage output from the bias generation unit and supplies the back bias voltage to the P well of the DRAM, and a selection control unit that controls the selection operation of the back bias selection unit according to a mode. The overall operation and effects of the present invention will be described in detail with reference to FIGS. 1 to 4, which show one specific embodiment of the present invention of the present invention. In this specific embodiment, in the dual back bias supply circuit of the present invention, as shown in FIG. 1, the output of the bias unit 203 is input to the standby clamping unit 201 and the active clamping unit 202, respectively. The output of the standby clamping unit 201 is input to the high level back bias generator 205, and the output of the active clamping unit 202 is input to the low level back bias generator 204. The bias selector 207 selects one of the outputs of the low level back bias generator 204 and the high level back bias generator 205 under the control of the select controller 206 to select P of the DRAM 300. It is configured to feed the wells. In this configuration, the bias unit 203 is a current mirror type power supply circuit formed by two PMOS transistors P1 and P2 and two EMOS transistors N1 and N2 as shown on the left side of FIG. The bias voltage H-bias of the 'high' output from the PMOS transistor P2 is commonly input to the standby clamping unit 201 and the active clamping unit 202, and the NMOS transistor The bias voltage L-bias of 'low' output from N2 is input to the control logic unit 206a of the selection controller 206. As described above, the standby clamping unit 201, which has received the high bias voltage B-bias, has one PMOS transistor P4 and seven NMOS transistors N7-, as shown in FIG. N13) is connected in series, and the high bias voltage H-bias input from the bias unit 203 is applied to the gate of the PMOS transistor P4 to supply the PMOS transistor P. It is turned on and outputs a high level standby clamp voltage VC1 from the MOS transistor N8 and inputs it to the high level back bias generator 205. At this time, the magnitude of the standby clamp voltage VC1 is determined by the NMOS transistors N8-N13 serving as a resistance. The high level back bias generator 205 receiving the standby clamp voltage VC1 outputs a high back bias voltage VBB2 and inputs it to the back bias selector 207. On the other hand, similar to the standby clamping unit 201, the active clamping unit 202 received the same high bias voltage (H-bias) from the bias unit 203, as shown in FIG. Two PMOS transistors P3 and four NMOS transistors N3-N6 are connected in series, and the high bias voltage H-bias input from the bias unit 203 is It is applied to the gate of the MOS transistor P3 to turn on the PMOS transistor P3, and outputs the low-level active clamp voltage VC2 from the MOS transistor N4 to the low-level back bias generator 204. Enter it. At this time, the magnitude of the active clamp voltage VC2 is determined by the n-mo transistor N4-N6 or the like acting as a resistance. The low level back bias generator 204 receiving the active clamp voltage VC2 outputs a low back bias voltage VBB1 and inputs it to the back bias selector 207 similarly to the high level back bias generator 205. do. On the other hand, the selection controller 206 is a row address strobe signal (RAS: Row Address Strobe) input from the outside, the self enable signal (SELF-ENB) for enabling the self-driving mode (SELF) and the power-up mode (POWER) The first control signal SO and the second control signal S1 are generated according to the power-up enable signal UP-ENB for enabling the UP to control the selection operation of the back bias selection unit 207. do. As shown in FIG. 1, the selection control unit 206 is composed of a control logic unit 206a and a no-question NOR1, and the control logic unit 206a is shown in the lower part of FIG. Likewise, when the low bias voltage L-bias and the low back bias voltage VBB1 or the high back bias voltage VBB2 are inputted, the row address strobe signal (RAS: Row Address Strobe) inverted by the inverter I1. The self-enable signal SELF-ENB is subjected to NAND logic operation by the NAND gate NAND1, and then inverted by the inverters I2-I4 to output the first control signal SO. Then, the first control signal SO and the power-up acknowledgment air signal UP-ENB are subjected to a non-logical operation by the no-assign SOR1 (FIG. 1) to generate a second control signal SL. Hereinafter, a description will be given of the power up mode (POWER-UP), standby mode (STANDBY), active mode (ACTIVE) and self-driving mode (SELF). First, in the case of the power-up mode. In the power-up mode, as shown in the timing diagram of FIG. 3, the row address strobe signal (RAS: Row Address Strobe), power-up enable signal (UP-ENB), and self-enable input from the outside to the selection control unit 206 from the outside. Both signals SELF-ENB are high. Accordingly, as shown in FIG. 3, the selection controller 206 outputs the first and second control signals SO S1 of a row so that the first control signal SO is connected to the back bias selection unit 207. Is input to the inverter 11 and the second control signal S1 is input to the NMOS transistor N1 of the back bias selection unit 207 to charge the capacitors C1 and C2. At this time, the two inverters I1 and I2 are special inverters having a high back bias voltage VBB2 as a threshold. In the standby mode, as shown in the timing diagram of FIG. 3, the row address strobe signal RAS and the self enable signal SELF-ENB are high, and the power supply enable enable signal UP-ENB is low. Accordingly, the internal row address strobe signal RAS of the low level back bias generator 204 of FIG. 4A becomes low and eventually the back bias voltage VBB1 is generated by the low level back bias generator 204. Is not output. FIG. 4A is a detailed configuration diagram of the low level back bias generator 204. The inverted row address strobe signal RAS of the row address strobe signal RAS input from the outside is inputted through the inverter NOT3. The output of the NOR1 and NOA gate NOR1, which receives the interrupt signal INTB from the outside through the inverter NOT1, and performs the logic logic operation, and the NAND3 of NAND3, which inputs the inverter NOT2. NAND gate NAND2 for NAND logic operation, an output of NAND gate NAND2 and an NOR3 NAND logic for NAND logic output of NOR1, and NAND3 output NAND logic Inverter NOT4 (NOT5) (NOT6) to invert, ANMOS transistor N1 which transfers the output of this inverter NOT6 when the active clamp voltage VC2 is input, and this ANMOS transistor N1. Output of inverter (NOT6) It consists of the capacitor | condenser C1 outputted as BB1), and an an transistor transistor N2 (N3). 4 (b) shows the detailed configuration of the high level back bias generator 205, which is composed of an oscillator 205-1 and a pump 205-2. 4 (c) and (d) show equivalent configurations of the components of the oscillator 205-1. Meanwhile, in the standby mode, the selection controller 206 outputs the low first control signal SO and the high second control signal S1 as shown in FIG. NMOS transistor N1 (N2) of the ON) is turned on, and the NMOS transistor N3 connected to the NMOS transistor N2 through the inverter I2 is turned off. The ON current of the NMOS transistor N1 is compensated for the leakage current to the capacitor C1 so that level stabilization is performed in an active mode which will be performed later. As described above, the back bias voltage VBB1 is not output from the low level bias generation unit 204, while the high back bias voltage VBB2 is output from the high level back bias generation unit 205 and thus high. The back bias voltage VBB2 is supplied to the P well of the DRAM 300, more specifically, the P worm P + of the P well through the NMOS transistor N2 to bias the P well. By supplying the high back bias voltage VBB2 in the standby mode in this manner, as is well known, the leakage current is greatly reduced. The back bias voltage can be easily changed by supplying the back bias voltage to the P well instead of the P substrate of the DRAM 300. In the active mode, as shown in the timing diagram of FIG. 3, the row address strobe signal (RAS: Row Address Strobe) and the power-up enable signal UP-ENB are in a low state, and the self-enable signal SELF-ENB is low. Is high. Accordingly, the internal row address strobe signal RAS of the low level back bias generator 204 of FIG. 4 (a) becomes high and eventually the low back bias voltage VBB1 is generated by the low level back bias generator 204. Is output. As shown in the timing diagram of FIG. 3, since the first control signal SO is in a high state, the NMOS transistor N2 of the back bias selection unit 207 is turned off and the NMOS transistor N3 is turned on to be low. The low back bias voltage VBB1 output from the level back bias generator 204 is supplied to the P well of the DRAM 300 through the turned on NMOS transistor N3 as before. By supplying the low back bias voltage VBB1 in the active mode in this manner, as is well known, the signal transmission speed is increased. At this time, since the second control signal S1 is in the low state, the enMOS transistor N1 of the back bias selection unit 207 is turned off, which prevents mutual interference in the current active mode. Lastly, in the self-driven mode, only a refresh operation is performed and is independent of the signal transmission rate, so as in the standby mode, it is important to achieve low power by reducing the leakage current. Accordingly, as shown in the timing diagram of FIG. 3, in the self-driving mode, even if the row address strobe signal RAS is low, the high back bias voltage VBB2 output from the high level back bias generation unit 205 is used. Supply to P well to reduce leakage current. As described in detail above, the dual back bias supply circuit of the present invention reduces the leakage current in the DRAM by supplying a high back bias voltage to the P well of the DRAM when in standby mode or when low power driving is required, and lower back bias in the active mode. By supplying the voltage, the signal transmission speed in the DRAM is increased.

Claims (1)

A bias portion for generating a high level bias voltage, a standby clamping portion for outputting a standby clamp voltage by clamping a high level bias voltage of the bias portion, and clamping a high voltage bias voltage of the biaser portion An active clamping unit for outputting an active clamp voltage lower than a standby clamp voltage, a low level back bias generator for outputting a low back bias voltage by inputting an active clamp voltage of the active clamping unit, and the standby A high level back bias generator for outputting a high back bias voltage as a standby clamp voltage of the clamping unit, a high back bias voltage output from the high level back bias generator, and an output of the low level back bias generator Low back bias voltage The dual back bias supply circuit of claim 1, further comprising a back bias selection unit for supplying the P well of the DRAM and a selection control unit for controlling the selection operation of the back bias selection unit according to the mode of the DRAM. The select controller is configured to supply a high back bias voltage of the high level back bias generator to the P well of the DRAM in the standby mode, and a low back bias voltage of the low level back bias generator to the P well of the DRAM in the active mode. And controlling the selection operation of the back bias selection unit.