KR0135832B1 - Pip circuit - Google Patents

Abstract

A dual images display circuit capable of displaying 16:9 or 4:3 sized dual images on the screen size of 16:9 is provided. The display circuit includes: a picture determinating part(300) for determining whether an input video signal is 4:3 or 16:9 screen mode; a micom(400) for outputting a control signal according to the output of the picture determining part(300); and a clock selection part(500) for selecting a first read clock which is 4 times faster than a write clock of a picture memory(600) to output the first read clock when a first control signal displaying 4:3 sized PIP is output from the micom(400), and selecting a second read clock which is 3 times faster than the write clock of the picture memory(600) to output the second read clock when a second control signal displaying the full screen mode is output from the micom(400).

Description

Picture-in-picture display circuit

1 (a), (b) and (c) are diagrams showing a compression state of a general picture-in-picture;

2 (a), (b), (c) is a drawing in which a 4: 3 original is compressed on a 16: 9 screen by compressing each of the horizontal and vertical lines by 각각.

3 (a), (b), (c) shows a 4: 3 original picture horizontally and vertically compressed and displayed on a 16: 9 screen,

4 (a), (b), (c) is a view in which the pole mode is displayed on a 16: 9 screen by compressing each of the horizontal and vertical directions by,.

5 is a block diagram showing an embodiment of a picture-in-picture display circuit according to the present invention;

6 is a waveform diagram showing an operating state of FIG.

* Description of the symbols for the main parts of the drawings *

100: analog / digital conversion unit 200: vertical compression unit

300: screen determination unit 400: microprocessor

500: clock selection unit 600: image memory unit

700: digital / analog converter

The present invention relates to a 16: 9 aspect white screen, and more particularly, a 16: 9 and 4: 3 ratio picture in picture (hereinafter referred to as PIP) is selectively displayed on a 16: 9 screen. The present invention relates to a PIP display circuit that enables display.

A technique of displaying the screen of No. 135832 2/6 on part of the original screen by reducing the second screen so as to display another second screen on one television screen is called PIP.

In order to perform the PIP function on a TV with a 4: 3 aspect ratio, the original screen is reduced to 1/9 by reducing the zoom vertically (scanning lines) and then zooming horizontally again. A small screen of 3 is displayed on a part of the TV.

Here, the method of reducing the screen is shown in FIG. That is, if only one line is recorded in memory as one line in Fig. 1 (B) as in Fig. 1 (B), the scanning line constituting the original screen is reduced vertically, and then again in memory as shown in Fig. 1 (C). When reading the written contents, when reading with the read clock three times faster than the write clock, the original screen is reduced to 1/9 even if it is horizontally reduced.

This method is effective when the CRT of the television is 4: 3 and the PIP is also 4: 3, but the problem is as shown in FIG. 2 when the CRT is 16: 9.

In other words, the length of the scanning line scanned per unit time on the screen is longer than the previous 4: 3, and when the PIP made by the above method is displayed on the 16: 9 CRT, it is horizontally 4/3 as shown in FIG. It is stretched out sideways to the PIP of 16: 9, and the image in the PIP also spreads to the side.

FIG. 3 is to solve this problem. When reading from memory after zooming out vertically, reading with a read clock 4 times faster than the write clock and reducing it horizontally by ¼ reduces the vertical / horizontality as shown in FIG. The ratio will be 3: 3 and the image quality inside will be elliptical, but if you display it as a PIP on a 16: 9 screen, it will be 4/3 horizontally as shown in Fig. 3 (c), resulting in the original 4: 3 PIP screen.

However, Full Mode, here, means that a 16: 9 picture is compressed horizontally to a 4: 3 size that is displayed on a 16: 9 screen and spread out to the original 16: 9. If you reduce the size vertically and horizontally ¼ in the: 9-screen source, the PIP screen that should be displayed in 16: 9 is displayed in 4: 3, which is the opposite of the 4: 3 screen. Appears.

Therefore, FIG. 4 is for displaying a 16: 9 PIP on a 16: 9 screen. When the pole mode of FIG. 4A is compressed as shown in FIG. It becomes elliptical, but if it is expressed as PIP on 16: 9 screen, it can spread 4/3 times horizontally as shown in FIG. 4 (C) to realize normal 16: 9 PIP image.

Therefore, PIPs of 4: 3 and 16: 9 can be realized on a 16: 9 screen.

However, if a read clock that reads data from a memory that stores vertically compressed video signals is provided four times faster than a write clock, and the source for performing PIP is 4: 3 KRW, 4: 3 PIP is normally implemented. In case of poll mode, the screen and image are spread up, and the read clock that reads data from memory is provided 3 times faster than the write clock, and when the source to perform PIP is poll mode, 16: 9 PIP is normally implemented. In the case of the: 3 original picture, the screen and the image spread horizontally so that the two types of screens could not be expressed together.

The present invention has been made to solve this problem, and an object of the present invention is to warp a 16: 9 screen by selectively providing a clock to read data in memory at 4 times the speed in 4: 3 original mode and 3 times the speed in pole mode mode. The present invention provides a PIP display circuit capable of implementing 16: 9 and 4: 3 PIPs that cannot be seen or spread.

In order to achieve the above object, the present invention provides an analog / digital converter for converting a PIP video signal into a digital signal through a video input, and is connected to an output side of the analog / digital converter. A vertical compression unit for vertically compressing the video signal by selecting one scan line of a video signal every three lines, and a PIP for storing a signal that is vertically compressed by the vertical compression unit and connected to an output side of the vertical compression unit. A PIP display circuit comprising a picture memory section and a digital / analog converter that is connected to an output side of the picture memory section and converts a signal output from the picture memory section into an analog signal and outputs it as a PIP signal. Determining whether the video signal for PIP is 4: 3 original or pole mode The screen determination unit and the output terminal of the screen determination unit are connected to the first input terminal, and the user screen determination signal terminal is connected to the second input terminal to determine whether the video signal to be displayed in PIP is 4: 3 original or pole mode, and accordingly A PIP display circuit including a microcomputer for outputting a control signal and a clock selector connected to an output terminal of the microcomputer and selecting a 3x and 4x read clock according to a control signal output from the microcomputer and outputting the read clock to the image memory unit. have.

Hereinafter, an embodiment of a PIP display circuit according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram showing an embodiment of a PIP display circuit according to the present invention, in which a video signal for indicating a PIP is input through a video input terminal Vin.

In addition, an analog / digital converter 100 for converting an input video signal into a digital signal is connected to the video input terminal Vin, and an output side of the analog / digital converter 100 is connected to an output of the analog / digital converter 100. The vertical compression unit 200 is connected to the vertical compression unit 200 by selecting one scanning line every three lines, and the PIP for storing only the video signal selected by the vertical compression unit 200 at the output side of the vertical compression unit 200. The image memory 600 is connected.

The video input terminal Vin is connected to the analog / digital converter 100 at the same time as the screen determination unit 300 that determines whether the input video signal for the PIP is 4: 3 won or pole mode.

In addition, a first input terminal of the microprocessor 400 (hereinafter, referred to as a microcomputer) is connected to an output side of the screen determination unit 300, and a user directly selects and inputs a second input terminal of the microcomputer 400. The user screen selection signal terminal Uin is connected.

At this time, the microcomputer 400 outputs a control signal according to the type of video signal input to the first input terminal and the second input terminal, and a clock selector 500 is connected to the output terminal of the microcomputer 400 to connect the microcomputer ( A read clock three times faster than a write clock or a read clock four times faster than the write clock is provided to the image memory unit 600 according to the control signal of 400.

The image memory unit 600 outputs a horizontally compressed signal when the 3x read clock is provided from the clock selector 500, and outputs a horizontal ¼ compressed signal when the 4x read clock is provided. A digital / analog converter 700 is connected to an output terminal of the digital signal to convert the signal output from the image memory unit 600 into an analog signal and output the analog signal as a PIP signal.

FIG. 6 is a waveform diagram illustrating the operation state of FIG. 5 in detail. FIG. 6A illustrates a case in which a 4X read clock is output to the image memory unit 600. FIG. FIG. 6 illustrates a case where a triple speed clock is output to the image memory unit 600. FIG. 6 (C) shows a control signal output from the microcomputer 400. Whether the PIP video signal is 4: 3 source or pole mode. FIG. 6D illustrates a case of a read clock provided to the image memory unit 600 according to the control signal of FIG. 6C.

The present invention configured as described above allows 4: 3 screens to become mainstream, and 16: 9 screens are newly introduced to realize both 16: 9 and 4: 3 PIPs without distortion.

Therefore, when the PIP video signal is input to the analog / digital converter 100 through the video input terminal Vin, the analog / digital converter 100 converts the digital signal and outputs the digital signal to the vertical compressor 200. . The vertical compression unit 200 vertically compresses the vertical scanning lines of the video signal by selecting one line for every three lines and storing them in the image memory unit 600.

At this time, if 1 / N compression is to be performed vertically, one line may be selected for every N lines in the vertical scanning line and stored in the PIP image memory unit 600.

On the other hand, when the PIP video signal is input to the analog / digital conversion unit 100 through the video input terminal Vin and simultaneously to the screen determination unit 300, the video signal input from the determination unit 300 is 4: It is determined whether the 3 won or the pole mode, and outputs the data through the first input terminal of the microcomputer (400).

Meanwhile, a user screen selection signal input by the user directly through the second input terminal is input to the microcomputer 40. Therefore, when the output of the screen determination unit 300 and the user screen selection signal are input at the same time, the microcomputer 400 gives priority to the second input terminal, and outputs a control signal to the clock selection unit 500 according to the user screen selection signal. If the user screen selection signal is not input, the control signal is output to the clock selector 500 according to the output signal of the screen selection unit 300.

In this case, the priority is given to the user screen selection signal in order to allow the screen determination unit 300 to manually select a PIP to be displayed in case of malfunction.

On the other hand, the clock selector 500 is provided with a clock four times faster than a write clock written in the image memory unit 600 as shown in FIG. 6A and a clock three times faster as shown in FIG. 6B. And selected according to the control signal output from the microcomputer 400.

Therefore, when the microcomputer 400 outputs a control signal for determining that the PIP video signal is 4: 3 source as a high signal as shown in FIG. 6 (C), the clock selector 500 sends the image memory 600 to the image memory unit 600. The clock of FIG. 6A, which is four times faster than the write clock at the time of writing, is selected as the read clock of the image memory unit 600 (a part of FIG. 6D) to the image memory unit 600. to provide.

On the other hand, when the microcomputer 400 outputs a control signal for determining that the PIP video signal is in pole mode as a low signal as shown in FIG. 6 (C), the clock selector 500 may write to the image memory 600. The clock of FIG. 6 (b), which is three times faster than the write clock at that time, is selected as the read clock of the image memory unit 600 (B) in FIG. 6 (d) and provided to the image memory unit 600. .

Therefore, when the read clock provided for reading data from the image memory 600 is three times faster than the clock when the data is written to the image memory 600, the data of the image memory 600 is horizontally compressed and output. If the read clock is four times faster than the clock at the time of writing, the data of the image memory 600 is horizontally compressed and output.

Therefore, when the PIP video signal is determined to be in pole mode by the microcomputer 400, and the read clock is selected three times faster than the write clock from the clock selector 500, the image memory unit 600 is vertical / Outputs the compressed signals horizontally to the digital / analog converter 700, and converts the compressed signals to the analog / horizontally vertically and horizontally into analog signals to convert the 16: 9 PIP to 16. : 9 Display on the screen.

On the other hand, when the PIP video signal is determined to be 4: 3 original from the microcomputer 400, and the read clock is selected four times faster than the write clock from the clock selector 500, the image memory unit 600 is vertical. ⅓, the horizontally ¼ compressed signal is output to the digital / analog converter 700, and the digital / analog converter 700 displays the compressed signal converted to analog on a 16: 9 screen. There's a three-fold expansion that lets you display the original 4: 3 PIP on a 16: 9 screen. At this time, if the PIP is displayed on the 4: 3 screen, the PIP is 4: 3.

Another embodiment of the present invention can implement 16: 9 and 4: 3 PIP on a 4: 3 screen. That is, if the PIP video signal is 4: 3 original, if the read clock of the PIP image memory is provided 3 times faster than the write clock, the 4: 3 PIP is displayed on the 4: 3 screen, and the PIP video signal is in the pole mode. In the case of video, if the read clock of the PIP image memory is provided 4/9 times faster (= 3 * (3/4)) than the write clock, the 16: 9 PIP is displayed on the 4: 3 screen.

As described above, the present invention determines whether the PIP video signal is 4: 3 original or pole mode, and if it is 4: 3 original, the read clock is 4 times faster than the write clock of the PIP image memory. In case of pole mode, 16: 9 and 4: 3 PIP without distortion or spreading in one 16: 9 CRT is provided by providing the PIP image memory with a read clock that is three times faster than the PIP image memory write clock. All have the effect of implementing it.

Claims (1)

When the PIP video signal is input through the video input, an analog / digital converter converting the digital signal into a digital signal and a scan line of the digital signal converted into the digital signal connected to the output side of the analog / digital converter are selected for every three lines. A vertical compression unit for vertically compressing the image, a PIP image memory unit connected to an output side of the vertical compression unit, and storing a signal output after being vertically compressed at the vertical compression unit, and connected to an output side of the image memory unit. A PIP display circuit comprising a digital / analog converter for converting a signal output from the image memory unit into an analog signal and outputting the analog signal as a PIP signal, wherein the PIP video signal input through the video input terminal (Vin) is 4: 3 won. And a screen determination unit 300 for determining whether or not to be in pole mode and the screen at the first input terminal. The output terminal of the end 300 is connected, and the second input terminal is connected to the user screen determination signal terminal (Uin) to determine whether the video signal for the PIP 4: 3 original or pole mode to the final microcomputer for outputting the control signal accordingly ( 400 and a clock selector connected to an output terminal of the microcomputer 400 to select readout speeds of 3x and 4x according to a control signal output from the microcomputer 400 and output them to the image memory unit 600. A picture-in-picture display circuit consisting of 500.