KR0132431B1 - Large scale integrated circuit having low internal operating voltage - Google Patents

Abstract

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Description

Semiconductor device with low internal operating voltage

1A and 1B are circuit diagrams for explaining the prior art.

2 to 6 are diagrams for explaining problems discovered by the present inventors.

7A to 23 are views for explaining an embodiment of a first group of the present invention.

24 to 51 are views for explaining an embodiment of a second group of the present invention.

52 to 60 are views for explaining the third group embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1 semiconductor chip 2 memory array

3: peripheral circuit 6: reference voltage generating circuit

30: word line boost circuit 31: word driver

32: low decoder 33: sense amplifier

37: column decoder 39: data output buffer

40: Data input buffer

The present invention relates to, for example, a ULSI (Ultra Large Scale Integrated Circuit) having a storage capacity of 16 M bits or more and a low internal operating voltage. In particular, the structure and characteristics of the voltage limiter circuit are improved, and the configuration of the reference voltage generator circuit is provided. The present invention relates to the improvement of properties and the test method of ULSI having the same, and more particularly to the actual arrangement of ULSI. The present invention also relates to a reference voltage generating circuit of a semiconductor device, and more particularly to a circuit for generating a stable voltage with little variation due to an external power supply voltage or temperature. In a semiconductor integrated circuit, a stable reference voltage with less fluctuation due to an external power supply voltage or temperature may be required. For voltage limiters of LSIs, see, for example, ISSCC Digest Technical Papers, pp. 282-283 (published February 1984) and ISSCC Digest of Technical Papers, pp. 270-271 (published February 1986) and ISSCC Digest of Technical Papers, pp. 272-273 (published February 1986). As described in the last paper, in a memory LSI such as a DRAM (Dynamic Random Access Memory), a voltage lower than an external power supply voltage is generated in a circuit (voltage limiter) provided on an LSI chip and used as a power supply. This internal power supply voltage needs to be a stable voltage with little fluctuation caused by an external power supply voltage or temperature in order to stabilize the memory operation, and a stable reference voltage is required for this purpose. In addition, an LSI incorporating an analog circuit often requires a stable reference voltage as a reference voltage. As a reference voltage generating circuit that meets such demands, for example, US Pat. No. 3,975,648 or No. There is a circuit proposed in 4100437 et al. The circuit diagram is shown in FIG. This is a circuit which obtains a stable voltage by using the difference between the threshold voltages of the N channel enhanced MOSFET (hereinafter referred to as EMOS) and the depletion MOSFET (hereinafter referred to as DMOS). In the figure, Q91 is EMOS, Q90, Q92, and Q93 are DMOS, and V _CC and V _BB are external power supplies of constant voltage and negative voltage, respectively. The difference between the threshold voltages of the EMOS and the DMOS is the output voltage V _R. The operation of this circuit will be described below. Q _90, and the current flowing through the current passing through the Q ₉₁ to I _90, Q _92, Q ₉₃ to I _91. If all four MOSFETs operate in the saturation region, the following four equations hold.

Where V ₉₉ is the voltage of the node 99, V _TE , V _TD are the EMOS and the threshold voltages of the DMOS (V _TE 0, V _TD 0), β ₉₀ , β ₉₁ , β ₉₂ , β ₉₃ are Q, respectively. Conductance coefficients of ₉₀ , Q ₉₁ , Q ₉₂ and Q ₉₃ . In the formulas (1) to (4), the output voltage V _R is

It becomes

Here, if the constant of each MOSFET is determined so that β ₉₀ and β ₉₃ are sufficiently small or β ₉₀ / β ₉₁ = β ₉₃ / β ₉₂ ,

Becomes That is, as the output voltage V _R , the voltage of the difference between the threshold voltages of the EMOS and the DMOS is obtained, which is a stable voltage that does not depend on the voltage of the external power supply V _CC or V _BB . In recent years, as high integration of semiconductor devices has progressed, a drop in the breakdown voltage due to the miniaturization of semiconductor devices has become a problem. This problem can be solved by lowering the power supply voltage of the semiconductor device, but this is not necessarily desirable in view of the external interface. Therefore, the power supply voltage applied to the outside is left as it is (for example, 5V when a TTL (Transistor-Transistor Logic Circuit) can be converted), and an internal power supply having a voltage lower than that (for example, 3V) is applied to the semiconductor device. How to make is proposed. See, for example, IEEE Journal of Soild-State Circuits, Vol. SC-22, NO. 3, pp. 437-441 (issued in June 1987) describe an example in which this method is applied to DRAM and a circuit (voltage limiter circuit) for generating internal power from an external power source. FIG. 1B shows a circuit diagram of the voltage limiter circuit described in the above document. V _L in the figure is a voltage limiter circuit, and consists of a reference voltage generating circuit V _R and a driving circuit B. Z is a circuit that operates by the output voltage V _L of the load of the voltage limiter, that is, voltage limiter to the power source. The reference voltage generating circuit V _R generates a stable voltage V _R with little fluctuation caused by the external power supply voltage V _CC or temperature. The driving circuit B is a circuit which generates a voltage V _L having a large driving capability, similar to the voltage value V _R, and constitutes a differential amplifier DA of Q _{106 to} Q ₁₁₁ and an output MOS transistor Q ₁₁₂ . Since V _R is connected to one of the two input terminals of the differential amplifier DA and the output V _L is returned to the other, this circuit operates so that the output V _{L conforms} to the input V _R. The driving capability of the output V _L is determined by the channel width of the output MOS transistor Q ₁₁₂ . Therefore, if the channel width of Q ₁₁₂ is designed to match the current consumption of the load, stable internal power supply voltage V _L can be supplied to the load. According to the above-described prior art, the present inventors have studied the specific super-scale integrated circuit (for example, LSI of 16 Mbit or more in terms of DRAM) in detail and found the following problems. This problem is broadly divided into reference voltage generator circuits, voltage limiter circuits and their tests. First, the problem of the prior art shown in FIG. 1A is that it is difficult to match their characteristics because they use devices having different properties such as EMOS and DMOS. In the above description, the characteristics are the same for the sake of simplicity, but in practice, the characteristics such as the temperature dependence dβ / dT of the conductance coefficients β and β and the temperature dependence of the threshold voltage dv _T / dT are very different. This is because the threshold voltage difference V _TE -V _TD between the EMOS and the DMOS must be made very large for the following reason. The EMOS must be in a non-conductive state when the gate-to-source voltage is OV. For that purpose, the threshold voltage V _TE needs to be set very high (for example, V _TE? 0.5 V) in consideration of manufacturing imbalance and sub-threshold characteristics. In addition, since the DMOS may be used as a current source as shown in equations (1) and (4), in order to suppress the deformation of the current value, the absolute value of the threshold voltage V _TD is very large (for example, V _TD). ≤1.5V). Therefore, V _TE -V _TD is very large (e.g., V _TE -V _TD? 2V), which means that the impurity profile of the channel region of the MOSFET is significantly different. This causes a mismatch in the characteristics as the MOSFET as described above. One object of the present invention is to solve the above problems and to provide a reference voltage generation circuit that does not use a depletion type FET. In order to achieve the above object, in the present invention, two FETs having different threshold voltages in an enhanced type are used to draw a potential difference when a constant ratio of current flows therein to be a reference voltage. Instead of using a depletion type FET, two FETs having different threshold voltages in an enhanced type can sufficiently reduce the difference between their threshold voltages (however small may be in principle). Therefore, it is easier to match the characteristics of the two FETs compared with the above-described prior art, and a more stable reference voltage can be obtained. The first problem of the prior art shown in FIG. 1B is not taken into consideration for the stability of the operation of the voltage limiter circuit. In general, a feedback amplifier, such as the driving circuit B of FIG. 1B, becomes unstable unless designed to have sufficient phase margin. This is explained using FIG. If the relationship between the frequency-to-gain and the frequency-to-phase of the amplifier when no feedback is performed is shown as shown in the figure, a numerical value indicating how much the phase delay can afford by 180 degrees at the frequency where the gain becomes 0 Hz to be. If the phase margin is negative, the feedback amplifier oscillates and the operation becomes unstable if the margin is small. In general, it is said that 45 degrees or more of phase margin is required for stable operation. For that, the gain must be less than or equal to zero at the _second point P ₂ (the slope changes from 6 Hz / oct to 12 Hz / oct) at which the frequency-to-gain characteristic is broken. . It is a mission of the voltage limiter circuit to supply a stable internal power supply voltage to the internal circuit, and of course, oscillation or operation should not be made unstable. As a countermeasure against this problem, various methods for compensating for phase delay are described, for example, in Paul R. Gray and Robert G. Mayer Analysys and Design of Analog Integrated Circuits (2nd edition John Wiley and Sons Inc.). have. However, there are the following problems in applying phase compensation to the voltage limiter circuit of an actual semiconductor device. The circuit which becomes the load of a voltage limiter circuit is an internal circuit of an actual semiconductor device, and these include extremely many kinds and various things, such as a capacitance, a resistance, an inductance, a nonlinear element, or a combination thereof. Further, their loads are not constant in time, but may change depending on the operation mode of the semiconductor device. For example, when the semiconductor device is in the operating state and in the standby state, the current flowing to the load varies greatly. As a result, the bias condition of the output terminal of the driving circuit B in FIG. 1b is changed, and as a result, the frequency characteristic of the entire amplifier is also changed. In order to operate the voltage limiter circuit stably, it is necessary to make the amplifier having such complicated characteristics operate stably at all times. For this purpose, the conventional phase compensation method alone is insufficient. A second problem of the prior art is that no arrangement or wiring on a semiconductor chip is considered. In particular, the arrangement of the voltage limiter circuit and the wiring of the output voltage V _L when there are several circuits operating with the internal power supply voltage V _L have not been considered. The present inventors have found that when the above-described prior art is applied to a semiconductor memory, the following problems arise. 3 and 4 show an example in which the conventional technique is applied to a semiconductor memory. In FIG. 3, reference numeral 1 denotes the entire semiconductor memory chip, 3 denotes a peripheral circuit, and 7 denotes a driving circuit in the voltage limiter circuit (here, the description of the reference voltage generating circuit in the voltage limiter circuit is omitted. (14a) to (14d) are memory mats composed of pulse generating circuits and (2a) to (2d) fine MOSFET transistors, which operate at an internal power supply voltage V _L because they use fine elements. . the drive circuit 7 and the pulse generating circuit (14a) ~ (14d) is a circuit therefor. (7) generates an internal power supply voltage V _L and, (14a) ~ (14d) is of an amplitude V _L pulse ^Φ p1 to ^Φ p4, respectively, and in this example, only one drive circuit 7 is provided for four pulse generator circuits (14a) to (14d), therefore, the internal power supply voltage generated by this voltage limiter circuit. in order to supply the V _L to each pulse generating circuit over a long wiring on the lower side from the upper side of the chip, In addition, the parasitic impedance of the wiring becomes large, which causes noise. When the wiring width is increased to reduce the impedance, a problem arises in that the area occupied on the chip of the wiring increases at this time. In the figure, in order to avoid the problem of lengthening the wiring, the driving circuits 7a, 7b, 7c, and 7d are provided in correspondence with each of the pulse generating circuits. Although the wiring length between the generating circuits can be shortened, the same number of voltage limiter circuits as the number of pulse generating circuits (here, 4) is required, so that the occupied area and the current consumption on the chip of the voltage limiter circuit are the third. In the case where the number of pulse generating circuits becomes larger, the increase in the occupied area and power consumption of the voltage limiter circuit is found in semiconductor devices for the purpose of high integration and low power consumption. The third problem of the prior art is that the operating speed of the complementary metal oxide semiconductor (CMOS) circuit is not considered, and this problem is solved by using a DRAM manufactured using the state-of-the-art fine processing technology. Explain. 5 shows a part of a circuit block of an N well type CMOS DRAM. In FIG. 5, the memory cell array portion is on a P-type semiconductor substrate. The sense amplification base consists of N-channel and P-channel MOS transistors, and an N well corresponding to the substrate of the P-channel MOS transistor is connected to a power supply voltage. As described in ISSCC, FAM18, June 1984, p282, a problem arises in that the MOS transistor is made smaller in size, and the degree of integration of the DRAM is lowered so that the stress withstand voltage caused by the hot carrier of the MOS transistor decreases. In order to prevent this, it is considered to lower only the power supply voltage used in the memory array that requires miniaturization to improve the integration degree in consideration of the stress breakdown voltage. This is, for example, an operating voltage V _L (| V _L || V _CC | lower than the memory cell array unit V _CC including an external power supply voltage V _CC and a sense amplifier in the peripheral circuit portion (X decoder, Y decoder, etc.) of the DRAM. ). That is, in FIG. 5, the voltage supply line connected to the source of the P-channel MOS transistor of the sense amplifier is V _L , and the voltage supply line of the peripheral circuit part is V _CC . However, in the CMOS DRAM, it has been found that when the operating voltage of the memory array unit is lowered as described above, the operating speed is significantly lowered. As a result of the detailed analysis, it became clear that the cause is the threshold voltage rise due to the back gate bias effect of the P-channel MOS transistor. That is, if the potential of the source of the P-channel MOS transistor formed in the N well of the P-type substrate is the internal power supply voltage V _L and the potential of the N well (the back gate of the P-channel MOS transistor) is the external power supply voltage V _CC , the P-channel MOS The transistor is subjected to a back gate bias of V _CC -V _L and its threshold voltage rises. 6 shows threshold voltages for the difference between the back gate (N well) voltage and the source voltage (back gate bias) of a P-channel MOS transistor having a gate length of 1.2 mu m and a gate width of 10 mu m. In this example, when 2 V of the back gate bias is applied, the threshold voltage of about 0.35 V rises. With respect to the power supply voltage V _{CC which} is widely used in LSI, for example, V _L = 3V, the threshold voltage rise of 0.35V exceeds 10% of the operating voltage, which leads to speed degradation. One object of the present invention is to solve the first problem and provide a voltage limiter circuit with stable operation. Another object of the present invention is to solve the second problem and to provide a voltage limiter circuit of low noise, small footprint, and low power consumption. Another object of the present invention is to solve the third problem and provide a high speed and high reliability CMOS LSI. In order to solve the first problem, in the present invention, when the voltage limiter needs to drive many kinds of loads, the phase compensation is performed by dividing a plurality of driving circuits constituting the voltage limiter according to the type of load. . When the type or size of the load changes in time by the operation mode of the semiconductor device, the circuit constant of the driving circuit or phase compensation circuit is changed depending on the operation mode, or a separate driving circuit is provided for each operation mode to connect their outputs. The output of the voltage limiter. In order to solve the above second problem, the present invention arranges a voltage limiter circuit and a load circuit such as a pulse generating circuit using the output thereof as a power source in close proximity to each other. One voltage limiter circuit is shared by multiple load circuits. In order to solve the third problem, in the present invention, the back gate (well) voltage of the MOS transistor formed in the well in the CMOS LSI is equal to the operating voltage for supplying the source terminal. When the voltage limiter needs to drive many kinds of loads, the optimum phase compensation according to the type of load is possible by dividing the driving circuit into several according to the loads and performing each phase compensation. In addition, by varying the circuit constants of the driving circuit and the phase compensation circuit in accordance with the operation mode of the semiconductor device, or by providing individual driving circuits for each operation mode, connecting their outputs to output the voltage limiters to cope with load variations. Optimum phase compensation is possible. This makes it possible to make a voltage limiter circuit with stable operation. By arranging the voltage limiter circuit and the load circuit such as a pulse generating circuit which uses the output thereof as a power source in close proximity, the impedance of the wiring therebetween can be reduced, and the level of noise generated can be suppressed. In addition, the number of voltage limiter circuits can be reduced by sharing one voltage limiter circuit among several load circuits in a selection / non-selection relationship by a control signal such as an address signal. Therefore, the footprint and power consumption of the circuit can be reduced. Here, the voltage limiter circuit only needs to drive a circuit in a selected state among the load circuits. Therefore, it is not necessary to increase the current driving capability of the voltage limiter circuit by sharing. In the CMOS LSI, the MOS transistor formed in the well can prevent the rise of the threshold voltage due to the back gate bias effect by setting the well voltage to the internal power supply voltage V _L. It is an object of the present invention to provide an actual configuration of a super scale integrated circuit in addition to the above. It is yet another object of the present invention to provide a practical arrangement of the ultra-large scale integrated circuit. The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings. Next, the present invention will be described with reference to Examples. This description is divided into first, second, and third groups in order to facilitate understanding. Therefore, the application to the actual super-scale integrated circuit in each group is explained. However, this does not mean that all of these groups are independent. In other words, when it is technically possible to perform these groups in combination, the combinations of these groups are naturally suggested. In addition, as will be clear from the following description, the first, second and third groups are not mutually exclusive techniques but are techniques which exert a more synergistic effect by the combination.

(Group 1)

Next, an embodiment of the first group of the present invention will be described with reference to the drawings. In the following description, a case of generating a positive reference voltage will be described. However, a negative reference voltage can also be generated by reversing the polarity of the transistor. Fig. 7A shows a circuit diagram of the first embodiment of the present invention. This circuit is composed of N-channel MOSFETs Q _{61 to} Q ₆₃ and P-channel MOSFETs Q ₆₄ and Q ₆₅ , and V _CC is a constant voltage external power supply. Among the N-channel MOSFETs, Q ₆₂ and Q ₆₃ are enhanced FETs having a standard threshold voltage V _TE (hereinafter referred to as EMOS), and Q ₆₁ is an enhanced type having a threshold voltage V _TEE higher than V _TE. FET (hereinafter referred to as EEMOS). Next, the operation of this circuit will be described. P-channel MOSFETs Q ₆₄ and Q ₆₅ share a gate and a source, and constitute a so-called current mirror circuit 70. That is, the operation of Q ₆₄ ratio of the drain current I ₁ and the drain current of Q ₆₅ I ₂ to be constant. The current ratio (mirror ratio) is determined by the integer ratio of Q ₆₄ and Q ₆₅ . If the integers of Q _{61 to} Q ₆₃ are the same and all operate in the saturation region, the following three equations are established.

Here, β _EE is the conductance coefficient of EEMOS (Q ₆₁ ), β _E is the conductance coefficient of EMOS (Q ₆₂ , Q ₆₃ ), and V ₁ is the voltage of node 61. By the formulas (7) to (9),

It becomes only

Α is the mirror ratio I ₁ : I ₂ = α: 1 of the current mirror circuit 70. In particular, when an integer of Q ₆₄ and Q ₆₅ is the same α = 1.

At this time, if β _EE ≒ β _E ,

Becomes That is, the voltage of the difference between the threshold voltages of the EEMOS and the EMOS is obtained as the reference voltage V _R , which is a stable voltage that does not depend on the voltage of the external power supply V _CC . Instead of V _R , V ₁ (= 2 V _R ) may be used as the reference voltage. The characteristic of this reference voltage generation circuit is that it is easier to match the characteristics of the MOSFET as compared with the above-described prior art. In order to operate the Q ₆₁ ~Q ₆₃ in the saturation region may if V _TEE ≥2V _TE, i.e. V _TEE -V _TE ≥V _TE. This is because the threshold voltage difference V _TEE -V _TE can be made smaller (for example, 0.7 V) than in the prior art, and the difference in the impurity profile of the channel region can be made smaller than in the prior art. In the circuit according to the present invention, since the difference between the temperature dependence dv _T / dT of the threshold voltage can be made small, a stable reference voltage can be obtained even with temperature. However, in order to further reduce the temperature dependency, the mirror ratio α can be adjusted. Next, the method will be described.

If you differentiate (11) by the temperature T,

로 되도록 미러비 α를 설정하면, 기준전압의 온도의존성

으로 할 수 있다. 또한, 본 회로에 사용하는 MOSFET의 채널길이는 어느정도 긴쪽이 바람직하다. 예를들면, 반도체장치의 다른 회로에서 채널길이 1㎛ 정도의 MOSFET가 사용되고 있었다고 하여도 본 회로에서는 그것보다 긴, 예를들면 5㎛이상의 채널길이의 MOSFET를 사용하는 것이 좋다. (7)∼(9)식에서 간단히 하기 위하여 포화영역의 드레인 전류는 게이트, 소오스간 전압에만 의존하기로 하였지만, 실제로는 드레인, 소오스간 전압에 의해서도 다소 변화한다. 채널길이가 길수록 이 변화의 비율(드레인 콘덕턴스)이 작고, 따라서 기준전압의 안정도가 좋게 된다. 또 단채널효과에 의한 임계값 전압변동을 억제하기 위해서도 채널길이는 긴쪽이 좋다. 제7a도∼제7c도 에서 기준전압을 만들기 위한 MOSFET Q₆₁∼Q₆₃의 백게이트는 각각의 소오스에 접속되어 있지만, 공통의 기판단자에 접속하도록 하여도 좋다. 그러나, MOSFET의 임계값전압은 백게이트 전압에 의해서 변화하므로, 그 영향을 피하기 위해서는 소오스에 접속한쪽이 좋다. 여기에서, 본 발명에 사용하는 전류미러회로에 대해서 보충해둔다. 전류미러회로는 제7a도의 실시예에 사용되고 있는 2개의 MOSFET로 되는 회로에 한정되지 않는다. 예를들면, 제7b도 또는 제7c도의 회로 여도 좋다. 이들의 회로는 각각 캐스코드형, 윌슨형이라는 명칭으로 알려져 있는 회로이다. 이들의 회로의 특징은 미터특성이 좋다는 것이다. 즉, 제7a도의 전류미러회로에서는 Q₆₄와 Q₆₅의 드레인, 소오스간 전압의 변화에 의해서 미러비α가 약간 변화하지만, 제7b도는 제7c도의 회로에서는 그 변화량이 작다. 따라서, 본발명에 적용한 경우 미러비를 보다 정확하게 설정할수 있어 보다 안정된 기준전압을 얻을 수가 있다. 또, 전류미러회로도로써는 제7d도에 도시한 바와 같은 MOSFET 대신에 바이폴라트랜지스터를 사용한 회로이어도 좋다. 다음에 실시예에서는 간단하게 하기 위하여 주로 제7a도의 전류미러회로를 사용한 도면을 기재하고 있지만, 이들의 실시예에 제7b도∼제7d도의 회로를 적용하여도 좋은 것은 물론이다. 제8도에 본 발명의 제2실시예를 도시한다. 이 회로는 제7a도의 Q₆₃을 저항R₆₁로 치환한 것이다. Q₆₁과 Q₆₂의 정수가 같고, 모두 포화영역에서 동작하고 있다고 하면 다음의 3개의 식이 성립된다.therefore,

When the mirror ratio α is set to be, the temperature dependence of the reference voltage

You can do In addition, the channel length of the MOSFET used in the present circuit is preferably longer. For example, even if a MOSFET having a channel length of about 1 μm is used in another circuit of a semiconductor device, it is better to use a MOSFET having a channel length longer than that, for example, 5 μm or more. For simplicity in equations (7) to (9), the drain current in the saturation region is only dependent on the voltage between the gate and the source, but actually varies slightly depending on the drain and the source voltage. The longer the channel length, the smaller the rate of change (drain conductance), and hence the higher the stability of the reference voltage. In addition, the channel length should be longer in order to suppress the threshold voltage variation caused by the short channel effect. 7A to 7C, the back gates of the MOSFETs Q _{61 to} Q ₆₃ for generating the reference voltage are connected to the respective sources, but may be connected to a common substrate terminal. However, since the threshold voltage of the MOSFET changes with the back gate voltage, it is better to connect the source to avoid the influence. Here, the current mirror circuit used in the present invention is supplemented. The current mirror circuit is not limited to a circuit composed of two MOSFETs used in the embodiment of FIG. 7A. For example, the circuit of FIG. 7B or 7C may be sufficient. These circuits are circuits known under the names Cascode and Wilson, respectively. The characteristic of these circuits is that they have good meter characteristics. That is, in the current mirror circuit of FIG. 7A, the mirror ratio? Slightly changes due to the change of the drain and source voltages of Q ₆₄ and Q ₆₅ , while in FIG. 7B, the amount of change is small in the circuit of FIG. Therefore, when applied to the present invention, the mirror ratio can be set more accurately, and a more stable reference voltage can be obtained. As the current mirror circuit diagram, a circuit using a bipolar transistor may be used instead of the MOSFET shown in Fig. 7d. Next, in the embodiment, for the sake of simplicity, the drawings mainly using the current mirror circuit of FIG. 7A are described, but of course, the circuits of FIGS. 7B to 7D may be applied to these embodiments. 8 shows a second embodiment of the present invention. This circuit replaces Q ₆₃ in FIG. 7A with a resistor R ₆₁ . If the integers of Q ₆₁ and Q ₆₂ are the same and both operate in the saturation region, the following three equations are established.

In these formulas, the mirror ratio α = 1 β _EE ≒ β _E

The voltage difference between the threshold voltages of the EEMOS and the EMOS is obtained as the reference voltage V _R. The characteristic of this embodiment is that the difference between the threshold voltages of the EEMOS and the EMOS can be made smaller than in the case of FIG. This makes it easier to match the characteristics of the MOSFET. However, in a typical MOS process, since the MOSFET area can be made smaller than the resistor in general, the embodiment of Fig. 7A is preferable when the threshold voltage difference may be large.

Figure 9a shows another embodiment of the present invention. The difference from the embodiment of FIG. 7A lies in the method of keeping the ratio of currents I ₁ and I ₂ constant. In the case of Fig. 7A, the current mirror circuit 70 directly maintains the ratio of I ₁ and I ₂ constant, but in this embodiment, two sets of current mirror circuits 71 and 72 indirectly realize this. That is, the current mirror circuit 71 composed of four N-channel MOSFETs (this is the cascode type described above) maintains I ₂ and I ₃ at a constant ratio, and at the same time the current mirror circuit 72 composed of two P-channel MOSFETs is provided. Keep I ₃ and (I ₁ + I ₂ ) at a constant ratio. This keeps the ratio of I ₁ and I ₂ constant. For example, if the mirror ratio of the circuit 71 is I ₂ : I ₃ = 1: 1 and the mirror ratio of the circuit 72 is I ₃ : (I ₁ + I ₂ ) = 1: 2, then I ₁ : I ₂ = 1: 1. The characteristic of the present embodiment is that the voltage between the drain and the source of Q ₆₂ is substantially constant. In the embodiment of FIG. 7A, the voltage of the drain (node 62) of Q ₆₂ is V _DD- | V _TP | (V _TP is the threshold voltage of the P-channel MOSFET), which is caused by the variation of the external power supply voltage V _DD . Change. The change in the drain voltage causes a change in the drain current due to the drain conductance and causes a change in the reference voltage V _R. On the other hand, since the drain voltage of Q ₆₂ is maintained at 2V _R in this embodiment, a more stable reference voltage can be obtained with respect to V _DD . The circuit of FIG. 9B is the same embodiment. In this circuit, the current mirror circuit 73 composed of two EEMOS maintains I ₂ and I ₄ at a constant ratio, and the current mirror circuit 72 composed of two P-channel MOSFETs is composed of I ₄ and (I ₁ + I ₂ ). By maintaining a constant ratio, the ratio of I ₁ and I ₂ is kept constant. All the embodiments so far have been circuits based on the threshold voltage difference of the N-channel MOSFET, but may be based on the threshold voltage difference of the P-channel MOSFET. An example is shown in FIG. 10A and FIG. 10B. Q ₇₄ is a P-channel MOSFET with a standard threshold voltage V _TP , and Q ₇₃ is a P-channel MOSFET with a threshold voltage V _TPE lower than V _TP (large absolute value at negative). If both Q ₇₄ and Q ₇₃ are operating in the saturation region, then two equations are established.

Where V ₃ is the voltage at node 63, β _PE , β _E are the conductance coefficients of Q ₇₃ and Q ₇₄ , respectively. In these formulas, it is calculated as I ₁ : I ₂ = 1: 1, β _PE ≒ β _E.

The threshold voltage difference of the P-channel MOSFET is obtained as the reference voltage V _R. This embodiment is suitable for combining with a semiconductor integrated circuit formed on a P-type substrate and requiring a stable reference voltage. As described above, it is preferable to connect the back gate of the MOSFET for making the reference voltage to each source. However, in a semiconductor integrated circuit on a P-type substrate, N-channel MOSFETs are usually formed directly on the substrate, and all of the back gates are connected to a common substrate terminal. Therefore, when the substrate voltage changes, the threshold voltage of the N-channel MOSFET changes. On the other hand, since the P-channel MOSFET is formed in the N-type well, the back gate (well) of each MOSFET can be connected to the source so that it is not influenced by the substrate voltage variation. For example, in a DRAM, it is common to apply a voltage (usually -3V) generated in a substrate voltage generation circuit provided on a chip using a P-type substrate to the substrate. However, this substrate voltage is likely to change due to fluctuations in the external power supply voltage or operation of the memory. In such a case, the circuit of this embodiment is particularly effective. On the contrary, in the semiconductor integrated circuit formed on the N-type substrate, the circuit based on the threshold voltage difference of the N-channel MOSFET is preferable. Similarly, the 10b is a circuit based on the threshold voltage difference of the P-channel MOSFET. The difference from the above embodiments lies in the method of setting the operating point (operating current). In the above embodiments, the operating point is automatically determined in the reference voltage generation circuit. It was a so-called self-biased circuit. However, in this circuit, a circuit 76 for setting an operating point is provided independently. The current I ₅ flowing through the operating point setting circuit 76 is mainly determined by the resistor R ₆₂ (may be replaced by a MOSFET). The operating currents I ₁ and I ₂ of the reference voltage generating circuit are determined by I ₅ and two sets of current mirror circuits 72 and 75. For example, if the mirror ratio of the circuit 72 is I ₅ : (I ₁ + I ₂ ) ≤1: 2 and the mirror ratio of the circuit 75 is I ₅ : I ₂ = 1: 1, I ₁ = 1 ₂ = 1 ₅ Since the operating point setting circuit is provided independently, the present circuit has a feature that the operating point is less fluctuated by the deformation of the device than the self-biased circuit, and therefore the fluctuation in the current consumption is smaller. In a self-biased circuit, it is preferable to attach a start circuit. The starting circuit is a circuit for preventing the circuit from falling to an undesirable stable point. For example, in the circuit of FIG. 9A, a preferable stable point is a state in which V _R is generated normally as described above. In this case, the voltage V ₃ = 2 V _R of the node 63 and the voltage V ₄ ≒ V of the node 64 are shown. _DD- | V _TP | However, in addition to this, there is a stable point where I ₁ = I ₂ = 0, where V ₃ = 0, V ₄ = V _DD , and V _R = 0. In order to prevent the circuit from falling to this stable point, for example, a starting circuit 77 as shown in FIG. 11 may be added. P-channel MOSFETs Q ₇₅ , Q ₇₆ and resistor R ₆₃ (which may be replaced by MOSFETs) constitute a current source. When the circuit is at an undesirable set point, node 60 is charged by the current source because EEMOS Q ₇₇ is non-conductive at V ₃ = 0. Then, Q ₇₈ is brought into a conductive state, and the voltage of node 63 is raised to act to escape the circuit from an undesirable stable point. When the circuit reaches the desired stable point, V ₃ exceeds V _EE and Q ₇₇ becomes conductive so that the voltage at node 60 drops. Then, Q ₇₈ becomes non-conducting so that the operation of the reference voltage generating circuit main body is not affected. Next, an example in which the present invention is applied to a DRAM is shown. FIG. 12 is a configuration diagram of a DRAM in which an on-chip voltage limiter is provided to operate the memory array at an internal voltage V _L lower than the external power supply voltage V _CC . In order to generate the internal voltage V _L , the reference voltage generating circuit according to the present invention is used. In the figure, reference numeral 6 denotes a reference voltage generation circuit according to the present invention, 24 denotes a differential amplifier 7 'and 7 denotes a buffer, 30 denotes a word line boost circuit, and 2 denotes a memory cell MC. In the memory array 33 arranged vertically and horizontally, the sense amplifier 31 is a word driver. The differential amplifier 24 and the two resistors R ₂₁ and R ₂₂ are circuits for making the operating voltage V _R ′ of the memory array from the output voltage V _R of the reference voltage generator 6 as follows.

Since V _R is based on the threshold voltage difference of the FET as described above, it is not necessarily limited to an appropriate voltage as the operating voltage of the memory array. Therefore, it performs a conversion to V _R 'at V _R by that circuit. For example, when V _R = 1 V and V _R '= 3 V, R ₂₁ : R ₂₂ = 2: 1 may be used. Further, R ₂₁ and R ₂₂ may be made variable so that V _R 'can be finely adjusted, so-called trimming. As the trimming method, for example, the method described in the above-mentioned US patent can be used. The buffers 7 'and 7 are circuits for increasing the current driving capability of V _R. The buffer consists of a differential amplifier consisting of MOSFETs Q _{21 to} Q ₂₄ and current source I ₂₅ , and an output stage of MOSFET Q ₂₆ and current source I ₂₇ . In addition, since the structure of (7) is the same as that of (7 '), description is abbreviate | omitted in drawing. Since this circuit is fed back from the output to the input of the differential amplifier, it operates so that the voltages on the outputs V _L1 and V _{L2 correspond to} the input voltage V _R '. In other words, the outputs V _L1 and V _L2 , which have the same voltage value and large driving capability, can be obtained. V _L1 and V _L2 are used to drive the word lines of the sense amplifier and the memory cell, respectively. In this embodiment, a method called word line boost is used in which the word line voltage is higher than the operating voltage (here, V _L1 ) of the memory array. For that purpose, a word line booster circuit 30 is provided. The power supply of stage 30 is not an external power supply V _CC , but an internal power supply V _L2 . Therefore, the word line drive signal Φ _X is boosted on the basis of V _L2 . The word line driver 31 receives Φ _X and the decoder output XD to drive the word line WL. The sense amplifier 33 used in this embodiment is a conventional CMOS sense amplifier comprising P-channel MOSFETs Q ₁₂₅ , Q ₁₂₆ and N-channel MOSFETs Q ₁₂₇ , Q ₁₂₈ . (33) is started by conducting the MOSFETs Q ₁₃₆ and Q ₁₃₇ with Φ _S at that level and Φ _S at the low level. However, since the source of Q ₁₃₇ is connected to the internal power supply V _L1 instead of the external power supply V _CC , by operating 33, the high level side of the data line becomes V _L1 and the low level side becomes the ground potential. In other words, the amplitude of the data line is suppressed to V _L1 . Next, other embodiments in which the present invention is applied to DRAM will be described. FIG. 13 is a circuit diagram of a 16M bit DRAM to which the present invention is applied, FIG. 14 is a layout diagram in a chip, and FIG. 15 is a detailed layout diagram of the voltage limiter circuit 13. In addition, some circuits abbreviate | omit description in order to simplify in a layout. In the figure, (1) is a semiconductor chip, (2) is a memory array, (31) is a word driver, (32) is a row decoder, (33) is a sense amplifier, (34) is a data line precharge circuit, and (35) ) Are data line select circuits, (36L) and (36R) are switch circuits, (37) are column decoders, (38) are main amplifiers, (39) are data output buffers, (40) are data input buffers, (41) Is a write circuit, 42 is a low address buffer, 43 is a column address buffer, 44 is a timing generator circuit, 45 is a sense amplifier drive signal generator circuit, 46 is a word line voltage generator circuit, Reference numeral 47 denotes a data line precharge voltage generator circuit, and 48 denotes a substrate voltage generator circuit. 6 of the voltage limiter circuit 13 is a reference voltage generating circuit according to the present invention, 6a is a voltage conversion circuit, (7a), (7b), (7c) is a driving circuit, (4a), (4b), 4c is a bonding pad of ground V _SS , and 5a and 5b are bonding pads of an external power supply voltage V _CC . The reference voltage generating circuit 6 generates a stabilized voltage V _R (here, 1.1 V) with respect to the external power supply voltage V _CC (here, 5 V), and the voltage conversion circuit 6a sets it to V _R '(here, 3.3). To V). The driving circuit generates a power supply voltage V _L1 for the memory array and a power supply voltage V _L2 for the peripheral circuit along V _R ′. In this example, the voltage levels of V _L1 and V _L2 are all 3.3V. The first feature of this embodiment is that a voltage limiter circuit is also applied to the peripheral circuit. V _L1 at (45) and (47), V _L2 (32), (37), (38), (40), (41), (42), (43), (44), (46), 48, respectively. That is, circuits other than the data output buffer 39 operate at the internal power supply voltage V _L1 or V _L2 . The peripheral circuit can also be operated with the stabilized voltage V _L1 lower than the external power supply voltage V _CC , thereby reducing the power consumed by the peripheral circuit and stabilizing its operation. The second feature of this embodiment is that the voltage limiter circuit 13 is arranged in the center of the semiconductor chip. As a result, the voltage drop due to the impedance of the wirings 11a and 11b of the internal power supply voltages V _L1 and V _L2 is reduced. As a result, the operation of the circuit using V _L1 and V _L2 as a power source becomes stable and high speed. A third feature of this embodiment is the method of grounding wiring. First, a dedicated short ground wiring 8 is provided for the reference voltage generating circuit and the voltage converting circuit. Next, the ground wirings 9a and 9b are provided for the driving circuit. The bonding pads 4b for voltage limiter circuits are provided separately from the bonding pads 4a and 4c for other circuits. As a result, it is possible to prevent the noise generated on the ground wiring from adversely affecting other circuits due to the current flowing when each circuit operates. In particular, if noise occurs in the ground wiring of the reference voltage generator circuit and the voltage conversion circuit, the level of the internal power supply voltages V _L1 and V _L2 fluctuates and affects almost all circuits in the chip, thus making the wiring 8 extremely short. In addition, it is preferable to separate it from other ground wiring. Although it is most preferable to separate from the bonding pad for this purpose, the bonding pad may be common and may be separated from the lead portion of the wiring. Although not shown, it is desirable to separate the ground wiring for the memory array from other wiring. This is because in a DRAM, when a sense amplifier performs an amplification operation, a large number of data lines (usually, thousands of PFs in total) are charged and discharged at the same time, resulting in large noise in the ground wiring. A fourth feature of this embodiment is in the method of power supply wiring. Bonding pads for the external power supply voltage V _CC are provided separately from the memory array 5a and the peripheral furnace 5b. The drive circuit 7a for the memory array is disposed close to 5a, and the drive circuits 7b and 7c for the peripheral circuit are located close to 5b, respectively. As a result, the voltage drop in the power supply wirings 10a and 10b can be reduced. Of course, this voltage drop is absorbed by each drive circuit, but if the drop is too large, it cannot be absorbed, which may cause a decrease in the internal power supply voltage V ₁₁ or V ₁₂ . In order to prevent this, it is preferable to reduce the impedance of the wirings 10a and 10b as in this embodiment. The separate bonding pads for the peripheral circuit and the memory array are provided to prevent the noise generated on the power supply wiring from adversely affecting other circuits by the current flowing when the circuit is operated, as in the case of the above-described ground. The power supply for the reference voltage generating circuit and the voltage converting circuit is wired from (5b) here, but of course, other bonding pads may be provided. Although not shown, it is preferable to separate the ground wiring and the power supply wiring for the data output buffer from the other ground wiring and the power supply wiring, respectively. This is because an external load (usually hundreds of PFs) is charged and discharged when the data output buffer operates, which causes a large noise in the ground wiring and the power wiring (the data output buffer operates directly at the external power supply voltage V _CC ). Next, each part of a present Example is demonstrated in detail. First, the reference voltage generating circuit 6 will be described. As the reference voltage generating circuit, the circuits shown in Figs. 7A to 11 can be used. As described above, in order to reduce the influence of the substrate potential variation, it is preferable to connect the back gate of each MOSFET to each source. For example, in the circuits of FIGS. 10A and 10B, the threshold voltage difference between the P-channel MOSFETs Q ₇₃ and Q ₇₄ becomes the reference voltage V _R. In this case, as the Q ₇₃ and Q ₇₄ , for example, a P-channel MOSFET having the structure shown in FIGS. 16A and 16B may be used. FIG. 16A is a layout view and FIG. 6B is a sectional view. In the figure, reference numeral 101 denotes a P-type semiconductor substrate, 102 denotes an N type well, 103 denotes an N + diffusion layer, 107 denotes a P + diffusion layer, 104 denotes a separate type SiO ₂ , and 106 denotes a gate. Polycrystalline silicon or metal, wherein 113 is an interlayer insulating film, 108 is a wiring layer, 115 is a protective film, and 116 is a contact hole. The source diffusion layer (P + diffusion layer on the left side of the figure) and the N well are connected by the wiring layer 108. This terminal corresponds to the node 66 in the circuit diagram of FIGS. 10A and 10B. This structure can be made by a normal CMOS process. 17A and 17B show an example in which the well has a double structure. In the drawing, reference numeral 111 denotes an N-type substrate, and 112 denotes a P-type well. Thus, the board | substrate 111 and the back gate 102 of MOSFET are electrostatically shielded by fixing the potential of the outer side well 112 (for example, ground) by making a dual well structure. Therefore, the interference noise through the parasitic capacitance between them can be prevented and the influence of the substrate potential variation can be almost completely eliminated. The substrate 111 may be connected to, for example, an external power supply V _CC . This structure can be made only by adding one step of forming a well to a conventional CMOS process, and a large effect can be obtained at a relatively low cost. In the circuits of FIGS. 7A to 9B and 11, the threshold voltage difference between the N-channel MOSFETs Q ₆₁ and Q ₆₂ is the reference voltage. In the case of using these circuits, an N-channel MOSFET having a structure in which the conductivity type is reversed in FIGS. 16A, 16B, 17A, and 17B may be used. The arrangement pattern of a pair of MOSFETs (Q ₇₃ and Q _{74 in} FIGS. 10A and 10B, Qa and 9B in FIGS. 10A and 10B, and Q ₆₁ and Q _{62 in} FIG. 11) is geometrically generated. It is preferable in the sense that the method of arrange | positioning as a congruent figure also makes it the same in order to reduce the influence of the imbalance of a manufacturing process. For example, the effect of diffusion layer resistance can be made the same by making the arrangement of the contact holes on the source and drain diffusion layers the same. In addition, by making the direction of the channel the same, the influence of the difference in mobility due to the crystal plane direction can be eliminated. Next, the voltage conversion circuit 6a will be described. One implementation method of the voltage conversion circuit is shown in FIG. In the figure, 24 is a differential amplifier, 25 is a trimming circuit, Q _{39 to} Q ₄₇ and Q ₄₉ are P-channel MOSFETs, and F _{4 to} F ₇ are fuses. Embodiments related to this will be described with reference to FIGS. 35, 37, and 39a, which will be further clarified with reference to this. This circuit generates a voltage V _R 'that is an integer multiple of the reference voltage V _R. In addition, fine adjustment (trimming) of the voltage for compensating the V _R unbalance due to the manufacturing process or the like is possible. V _R is input to one of the input terminals of the differential amplifier 24, and the voltage V _{R obtained} by dividing V _R 'by MOSFETs Q ₄₄ to Q ₄₇ and Q _{39 to} Q ₄₂ is fed back. If the amplification factor of (24) is large enough, the output voltage V _R 'is given by the following equation.

V _R '= R _T1 + R _T2 / R _{T2V R}

Here, R _T1 is a resistance value when the circuits of Q ₄₄ to Q ₄₇ are regarded as resistances, and R _T2 is a resistance value when the circuits to Q ₃₉ to Q ₄₂ are equivalently regarded as resistances. . Since R _T1 and R _T2 are changed by cutting the fuse, V _R 'can be adjusted. Since the standard values of V _R and V _R ′ are 1.1V and 3.3V, respectively, as described above, R _T1 : R _T2 = 2: 1 when the fuse is not cut. At V _R 1.1 V, increase R _T2 by cutting F _{4 to} F ₆ , and at V _R 1.1 V, increase R _T1 by cutting F ₇ so that V _R 'does not deviate significantly from the standard value. There is a number. The MOSFETs Q ₄₉ and Q ₅₀ are intended to be V _R '= OV in rest mode. In rest mode, the signal TE is at V _CC level and the output V _R ' is at OV. The circuit shown in FIG. U.S. Patent No. Compared with the circuit described in 4100437, there is an advantage that the occupied area in the case of making in a normal MOS process is small. That is, in the circuit described in the US patent, a resistor is used as an element for dividing the output voltage V _R ', whereas a MOSFET is used in the circuit of FIG. In order to reduce the current consumption of the circuit, the equivalent resistance of the voltage dividing element must be very large (a few hundred mA). In a normal MOS process, an element having a larger equivalent resistance with a smaller MOSFET side than a resistor is obtained. However, if a MOSFET is used, the characteristics of V _R 'may fluctuate due to the variation of the threshold voltage. However, the channel width and the channel length of each MOSFET are sufficiently large to suppress the fluctuation, and the back gate is connected to the source. This can be solved by avoiding the influence of potential fluctuations and predicting the fluctuation of the threshold voltage, and selecting the fuse cutting method. In addition, the MOSFET used for trimming should have a structure shown in Figs. 16A, 16B, 17A, and 17B in order to reduce the influence of substrate potential variation. It is preferable to add a large capacitor to the terminals of the reference voltages V _R and V _R ′ between the ground and the ground. This is to reduce the impedance with respect to the high frequency of V _R , V _R ′ and to bypass the high frequency noise. In particular, when the wiring 12a of V _R ′ inevitably crosses other wirings as shown in Fig. 15, there is also a meaning of stabilizing (preventing oscillation) the operation of the circuit with a voltage limiter. This reason is explained with reference to FIG.

The driving circuits 7a, 7b, and 7c respectively produce voltages V _L1 and V _L2 having a large current driving capability at V _R ′. The output 16 of the circuit operated with V _L2 , such as V _L1 , V _L2 itself or the pulse generating circuit 14 as a power source (the voltage level is V _L2 ) is connected to the wiring 12a of V _R ′. If they intersect, feedback loops passing through the parasitic capacitances C _{C1 to} C _C3 between the wirings are generated as indicated by (17a) to (17c). If the gain of this loop is greater than 1 (0 Hz), the circuit oscillates. If it is less than 1, the circuit operation becomes unstable if the margin is small. To prevent this, capacitors C _R1 and C _R2 that are sufficiently larger than C _C1 to C _C3 may be inserted between V _R 'and ground, and the gain of the loop may be made sufficiently small (for example, -10 dB or less). An example of a method of realizing a capacitor to be used is shown in FIGS. 20A and 20B. FIG. 20A is a layout view and FIG. 20B is a sectional view. In the figure, reference numeral 101 denotes a P-type semiconductor substrate, 102 denotes an N-type well, 103 denotes an N + diffusion layer, 104 denotes SiO 2 for separation, 105 denotes a gate insulating film, and 106 denotes a gate. Polycrystalline silicon or metal, 113 is an interlayer insulating film, 108 is a wiring layer, 115 is a protective film, and 116 is a contact hole. The capacitor is formed between the gate 106 and the substrate drawing 102a with a gate insulating film interposed therebetween as in a conventional MOS capacitor. Since a thin gate insulating film is used as the capacitor insulating film, a large capacitance can be obtained with a relatively small area. The difference from a normal MOS capacitor, however, is that the threshold voltage (flatband voltage) is negative because there are N wells under the gate. Therefore, as long as the voltage in one direction is applied so that the gate side is positive, the capacitance Is almost constant. The processes required for making this capacitor are well forming, isolation region forming, gate insulating film forming, gate forming, diffusion layer forming, and wiring, but these are all included in the conventional CMOS process. Therefore, in the case of a semiconductor device manufactured by a CMOS process, it is not necessary to add a process in particular to make the capacitor. One realization method of the drive circuits 7a and 7b is shown in Fig. 21A. In the figure, reference numeral 21 denotes a differential amplifier, and MOSFETs Q _{21 to} Q ₂₅ are represented. Reference numeral 22 denotes an output terminal, and MOSFETs Q ₂₆ and Q ₂₇ are obtained. C _L is equivalently representing the load (memory array or peripheral circuit) of the driving circuit as one capacitor. Of the two input terminals of the differential amplifier 21, the reference voltage V _R 'is input to one side, and V _L1 (V _L2 ) is fed back to the output terminal. Thus, this circuit operates so that V _L1 (V _L2 ) _conforms to V _R '. 23 is a so-called phase compensation circuit for stabilizing the operation of the feedback amplifiers (21) and (22). MOSFETs Q _{28 to} Q ₃₀ are intended to make the output high impedance when the drive circuit is inactive and to bring the output V _L1 (V _L2 ) to V _CC level in test mode. That is, in the inactive state, the test signal TE is at low level, the activation signal Φ ₁ ′ (Φ ₂ ′) is at low level, the gate of Q ₂₆ is at the V _CC level, and the output V _L1 (V _L2 ) is at high impedance. At this time, since Q ₂₅ and Q ₂₇ are in a non-conductive state, power consumption of the circuit is reduced. In the test mode, TE is at the V _CC level, the gate at Q ₂₆ is at the low level, and V _CC is output directly. One realization method of the drive circuit 7C is shown in FIG. 21B. In this circuit too, the output becomes high impedance when the activation signal Φ ₃ 'is low. In addition, since the phase compensation circuit of this circuit can also use (7b) as well (since (7b) and (7C) are connected in parallel), no phase compensation circuit is provided here. As described above, the driving circuit 7a is a circuit for generating V _L1 , and (7b) and 7C are for generating V _L2 . In the normal state 7C is always activated, and 7a and 7b are only activated when the memory is in the operating state. Therefore, the activation signal Φ ₃ ′ is always at the V _CC level, and Φ ₁ ′ and Φ ₂ ′ are at the V _CC level in accordance with the operation timing of the memory (detailed description of the timing will be described later). In test mode, Φ ₁ ′, Φ ₂ ′, and Φ ₃ ′ all go to the low level, and the test signal TE goes to the V _CC level. At this time, both V _L1 and V _L2 are equal to V _CC . This is effective for directly checking the operation of the memory (e.g., power supply voltage dependence of access time) by directly applying an external power supply voltage. Immediately after turning on the power, it is desirable to activate both Φ ₁ ', Φ ₂ ', Φ ₃ 'in order to accelerate the rise of V _L1 and V _L2 . As described below, V _L2 is used to generate the word line voltage V _CH and the substrate voltage V _BB . Thus, if to activate Φ ₂ 'when the voltage level of V _CH and V _BB is deviates from the standard value, it is possible to improve the stability of these voltage. In addition, the levels of the activation signals Φ ₁ ′, Φ ₂ ′, Φ ₃ ′ and the test signal TE are set to V _CC instead of V _L2 to ensure that the P-channel MOSFETs Q ₂₈ and Q ₂₉ are not in a conductive state. will be. The drive circuits 7a and 7b must have a large current driving capability. This is because (7a) and (7b) need to drive large (hundreds to thousands of PF) load capacity when the memory is in operation. In particular, (7a) must drive a large number of data lines when the sense amplifier performs the amplification operation. For example, if the capacity of one data line is 0.3PF and the number of sense amplifiers operating at the same time is 8192, the total capacity is 2500PF. Therefore, as the output MOSFET Q ₂₆ of (7a) and (7b), for example, a channel width / channel length of about 3000 mu m / 1.2 mu m is used. Since (7C) should have a current driving capability that guarantees leakage current when the memory is in standby, its output MOSFET should be about 100 µm / 1.2 µm.

The connection circuit 15 is for preventing the potential difference between V _L1 and V _L2 from becoming too large. This is because a large potential difference between V _L1 and V _L2 may cause a mismatch in signal exchange between the memory array and the peripheral circuit. An example of this circuit is shown in FIG. In the figure, Q ₁ , Q ₂ , and Q ₅ are N-channel MOSFETs, and Q ₄ is P-channel MOSFETs. If the threshold voltage of the N-channel MOSFET is set to V _TN , Q ₁ conducts when V _L1 -V _L2 V _TN and Q ₂ conducts when V _L2 -V _L1 V _TN . Therefore, the potential difference between V _L1 and V _L2 is maintained within V _TN . Q ₅ of the gate has a signal WK is at a high level only shortly after power is turned on is input. This is particularly effective to prevent the potential difference from occurring when the time constants of the loads of V _L1 and V _L2 are greatly different. Even when Q ₁ , Q ₂ , and Q ₅ are all non-conducting, MOSFET Q ₄ with relatively small conductance is conducting. This is, for example, the role of V _L1 = V _L2 while the memory is in standby. In the memory array 2, a so-called one-transistor one-capacitor dynamic memory cell MCij, which is MOSTET Q ₁₂₁ and capacitor C ₁₂₂ , is disposed at the intersection of the word line WLi and the data line DLj. Although only two word lines and one pair of data lines are shown in the figure, they are actually arranged in a vertical direction. One end PL (plate) of capacitor C ₁₂₂ is connected to a DC power supply. Although the voltage level is arbitrary, from the viewpoint of the breakdown voltage of capacitor C ₁₂₂ , 1/2 of the operating voltage of the memory array, that is, V _L1 / 2 is preferable.

The word driver 31 is a circuit which receives the output of the tow decoder 32 and drives the selected word line. In this embodiment, the so-called word line boosting method is adopted in which the word line voltage is higher than the operating voltage of the memory array (here, V _L1 = 3.3 V). An advantage of this method is that the accumulated voltage of the memory cell can be increased. Therefore, the voltage V _CH (V _CH V _L1 ) produced by the word line voltage generation circuit 46 is supplied to the selected word line.

를 저레벨로해서 MOSFET Q₁₃₆, Q₁₃₇을 도통상태로 하는 것에 의해서 활성화된다.The sense amplifier 33 is a circuit for amplifying a small signal on the data line, and is composed of flip flops of N-channel MOSFETs Q ₁₂₅ and Q ₁₂₆ and flip flops of P-channel MOSFETs Q ₁₂₇ and Q ₁₂₈ . Sense amplifiers have a high level of Φ _S ,

It is activated by bringing the MOSFETs Q ₁₃₆ and Q ₁₃₇ into a conductive state with the low level.

의 전압 V_P와 같게된다. 또한, 데이타선 프리차지전압 V_P는 임의의 전압으로 좋지만, 데이타선충방전전류를 저감하는 관점에서는 메로리 어레이의 동작전압의 1/2, 즉 V_L1/2로 하는 것이 바랍직하다. 데이타선 선택회로(35)는 칼럼 디코더(37)의 출력 Φ_YS를 받아서 선택된 데이타선쌍을 MOSFET Q₁₃₂, Q₁₃₃을 통해서 입출력선 I/O,

에 접속하는 회로이다. 본 실시예에서 칼럼 디코더(37)은 끝에 1개만 배치하고, 그출력 Φ_YS를 여러개의 데이타선 선택회로에 분배하는, 소위 다분할 데이타선이라 불리우는 방법을 사용하고 있다. 이것은 칼럼 디코더의 점유면적 저감에 유호하다.The data line precharge circuit 34 is a circuit for setting each data line to a predetermined voltage V _P prior to the reading of the memory cell. By applying the precharge signal Φ _P , the MOSFETs Q _{129 to} Q ₁₃₁ are brought into a conductive state, and the data lines DLj,

A is equal to the voltage V _P. The data line precharge voltage V _P may be any voltage, but from the viewpoint of reducing the data line charge / discharge current, it is preferable to set it to 1/2 of the operating voltage of the memory array, that is, V _L1 / 2. The data line selection circuit 35 receives the output Φ _YS of the column decoder 37 and sends the selected data line pair to the input / output line I / O, through the MOSFETs Q ₁₃₂ , Q ₁₃₃ .

It is a circuit connected to. In this embodiment, the column decoder 37 uses a so-called multipart data line, which is arranged at one end and distributes its output? _YS to several data line selection circuits. This is advantageous for reducing the footprint of the column decoder.

In this embodiment, a so-called shared sense and shared I / O method is adopted in which the sense amplifier 33, the data line precharge circuit 34, and the data line selection circuit 35 are shared by left and right memory arrays. . This is effective for reducing the occupied area by sharing (33), (34) and (35). For this reason is provided with a memory array 33, 34, 35, the switching circuit (36L) that is controlled by a switching signal Φ Φ _SHL and _SHR between and (36R).

The main amplifier 38, the data output buffer 39, the data input buffer 40, and the write circuit 41 are circuits for inputting and outputting data. In the case of a read, the data latched in the sense amplifier 33 is output to the data output terminal DOUT via the input / output line, the main amplifier 38, and the data output buffer 39.

In the case of a write, data input from the data input terminal DIN is set to the input / output line via the data input buffer 40 and the write circuit 41, and is written to the memory cell via the data line selection circuit 35 and the data line. do. In the present embodiment, as described above, (38), (40), and (41) operate at the internal power supply voltage V _L2 to reduce power consumption and stabilize operation. Only the data output buffer 39 is operated by the external power supply voltage V _CC (= 5 V) due to the external interface (here, TTL conversion possible).

The row address buffer 42 and the column address buffer 43 are circuits which receive an external address signal A and supply address signals to the row decoder 32 and the column decoder 37, respectively. The timing generating circuit 44 receives the external control signals RAS, CAS, and WE and generates a timing signal necessary for the operation of the memory.

These circuits are also operated at the internal power supply voltage V _L2 to reduce power consumption and stabilize operation.

The word line voltage generation circuit 46 is a circuit which generates the word line voltage V _CH (here, about 5 V) as described above. (This voltage is used as a switch circuit, as described below.)

The data line precharge voltage generation circuit 47 is a circuit that generates the data line precharge voltage V _P (here, 1.65 V). The substrate voltage generation circuit 48 is a circuit for generating a voltage V _BB (here, -2v) applied to the semiconductor substrate. The power supply of these circuits is not Vcc but stable V _L1 or V _L2 . Therefore, there is an advantage that there is little variation in the output voltage even if V _CC changes.

Next, the operation in the case of the lead of this dram will be described with reference to the operation waveform diagram of FIG.

모두 고레벨)일때에는 데이타선 프라차지신호 Φ_P및 스위치신호 Φ_SHL, Φ_SHR이 모두 고레벨(=V_L2)이며, 데이타선 DL,

가 V_P로 설정되어 있다. 또, 센스증폭기 구동신호 Φ_SAN, Φ_SAP및 입출력선 I/O,

도 V_P로 프리차지 되어있다. (이들의 프리차지회로는 제13도에 도시되어 있지 않다.) 이 상태에서는 전압리미터의 구동회로 활성화신호중, Φ₃'만이 고레벨(=VCC),Φ1,Φ2는 저레벨이다. 따라서, 소비전력이 작은 대기시용의 구동회로(7C)만이 활성화되어 있으며, 이것에 의해서 내부 전원전압V_L2의 레벨이 유지되어 있다. 또, 접속회로 (15)를 통해서 V_L1의 레벨도 유지되어 있다. 전류구동 능력이 크지만 소비전력도 큰 (7a),(7b)는 비활성상태이다. 이렇게 하는 것에 의해서 대기시의 소비전력을 저감할 수가 있다.Standby state (

High level), the data line precharge signal Φ _P and the switch signals Φ _SHL and Φ _SHR are all high level (= V _L2 ), and the data lines DL,

Is set to V _P. In addition, the sense amplifier drive signals Φ _SAN , Φ _SAP and I / O line I / O,

It is also precharged at V _P. (These precharge circuits are not shown in Fig. 13.) In this state, of the voltage limiter drive circuit activation signals, only? ₃ 'is high level (= VCC), and? 1,? 2 are low level. Therefore, only the standby driving circuit 7C with low power consumption is activated, whereby the level of the internal power supply voltage V _L2 is maintained. The level of V _L1 is also maintained through the connection circuit 15. (7a) and (7b), which have a large current driving capability but large power consumption, are inactive. By doing this, the power consumption during standby can be reduced.

When the RAS becomes low, the drive circuit activation signal Φ ₂ for the peripheral circuit first becomes a high level (= Vcc). As a result, 7b having a large current driving capability is activated and a large current can be supplied to the peripheral circuit which operates with V _L2 as a power source. The precharge circuit Φ _P becomes low level (= 0V), the switch signal on the selected memory array side (Φ _{SHL in} FIG. 23 is stepped up to V _CH level), and the switch signal on the opposite side (Φ _{SHR in the} case of FIG. 23). ) Becomes 0v. The boosting of Φ _SHL is based on the following reasons. The voltage amplitude of the sense amplifier is V _L1 as described below. However, if the level of φ _SHL is V _L2 , the voltage amplification of the data line decreases to V _L2 -V _TN , and as a result, the accumulated voltage of the memory cell is also V _L2- . Decreases to V _TN . (V _TN is the threshold voltage of the N-channel MOSFETs Q ₁₂₃ , Q ₁₂₄ ).

By boosting Φ _SHL , it is possible to prevent this and ensure the accumulated voltage of the memory cell.

의 사이에 전위치를 발생하고 있다.Next, when the row address buffer 42 and the row decoder 32 operate, one word line WLI is selected and its voltage becomes V _CH . In each memory cell on the WLI, signal charges are read to each data line to change the potential of the data line. 23 shows an example in which the high potential (-V _L1 ) has been previously stored in the capacitor of the memory cell, and the potential of the data line DLJ rises slightly.

The potential value is generated between.

사이의 미소한 전위차가 증폭되고, 한쪽 (제23도의 경우는 DLJ)은 V_L1에, 다른쪽(제23도의 경우는

)은 0v로 된다.The prior to the operation of the sense amplifier drive circuit in the use of memory array activation signal Φ ₁ 'it is at a high level (= V _CC). As a result, the driving circuit 7a is activated, and a large current can be supplied to the sense amplifier driving signal generation circuit 45 which operates by using the power supply V _L1 . Next, phi s becomes high level (= V _L2 ) and phi s becomes low level (= 0 v). As a result, the MOSFETs Q ₁₃₆ and Q ₁₃₇ are brought into a conductive state, Φsan is grounded through Ω ₁₃₆ , and Φsap is connected to V _L1 through Φ ₁₃₇ . This makes the data line DLj,

The small potential difference between the two is amplified, and one side (DLJ in FIG. 23) is V _L1 and the other (FIG. 23 is

) Becomes 0v.

가 저레벨로 되면 칼럼어드레스 버퍼(43), 칼럼 디코더(37)이 동작하여 1개의 데이타선이 선택된다.

When the low level is reached, the column address buffer 43 and the column decoder 37 operate to select one data line.

As a result, the data line selection signal _.phi.YS becomes a high level (= V _L2 ), and the data line is connected to the input / output line through the data line selection circuit 35. The data latched in the sense amplifier 33 is output to the data output terminal DOUT via the input / output line main amplifier 38 and the data output buffer 39.

가 고레벨로 되돌아가면, 먼저 워드선 WLI가 저레벨로 되고, Φ_S,

, Φ_SHL, Φ_SHR, Φ_P가 본래의 레벨로 복귀한다. 메모리 어레이용의 구동회로 활성화 신호 Φ₁'는 여기에서 저레벨(=0v)로 되어 구동회로(7a)가 비활성상태로 된다. 또,

가 고레벨로 되돌아가면, 주변회로용의 구동회로활성화신호 Φ₂'도 저레벨 (=0v)로 되어 구동회로(7b)가 비활성상태로 된다.

Returns to the high level, first, the word line WLI becomes the low level, and Φ _S ,

, Φ _SHL , Φ _SHR , and Φ _P return to their original levels. The drive circuit activation signal Φ ₁ ′ for the memory array is here at a low level (= 0 v) to make the drive circuit 7a inactive. In addition,

Returning to the high level, it is a driving circuit for a peripheral circuit to the activation signal Φ ₂ 'is also the low level (= 0v) is a drive circuit (7b) is in an inactive state.

가 고레벨로되돌아갈때까지,Φ₂'는

가 저레벨로 있을 때에 각각 고레벨로 된다. 이것에 의해 구동회로(7a), (7b)에서 소비되는 전력을 저감할 수가 있다.As can be seen from the above description, the activation signals Φ ₁ ′ and Φ ₂ ′ of the driving circuit become high levels only when necessary, respectively. That is, Φ ₁ 'is just before starting the sense amplifier.

Until it returns to the high level, Φ ₂ '

Is at a high level, respectively. As a result, the power consumed by the drive circuits 7a and 7b can be reduced.

As described above, according to the present embodiment, a reference voltage generation circuit can be made based on the threshold voltage difference between the end-type FETs without using a depletion-type FET. Matching the characteristics of the enhanced FETs is easier than matching the characteristics of the depletion type and the enhanced FETs, so that a stable reference voltage can be obtained. Therefore, for example, when applied to the voltage limiter of the memory LSI described above, a more stable internal power supply voltage can be generated.

(Group 2)

Next, embodiments of a second group of the present invention will be described with reference to the drawings. The following description mainly shows an example in which the present invention is applied to a semiconductor device using MOS technology, but the present invention can be applied to other semiconductor devices, for example, a semiconductor device using bipolar or BICMOS technology. In addition, although the case where the external power supply voltage and the internal power supply voltage are positive has been described, the present invention can also be applied by reversing the polarity of the transistor, etc. even in the case of no denial.

First, the basic concept of the second group will be explained.

24 shows this embodiment. In the figure, V _L is a voltage limiter circuit and generates an internal power supply voltage V _{L1 to} V _L3 (hereinafter, referred to as V _Li (i = 1, 2, 3)) from the external power supply voltage V _CC . The voltage limiter circuit V _L is made up of the reference voltage generating circuit V _R and the driving circuits B ₁ to B ₃ (hereinafter described as Bi (i = 1, 2, 3)). The reference voltage generating circuit V _R generates a stable voltage V _R with little fluctuation caused by the external power supply voltage V _CC or temperature, and each driving circuit Bi generates a voltage V _Li having a large current driving capability according to V _R. Each driving circuit Bi is a feedback amplifier Ai (i = 1, 2, 3) and a phase compensating circuit Ci (i = 1, 2, 3). Z _{1 to} Z ₃ are circuits in the semiconductor device serving as loads of the voltage limiter circuit V _L , and operate from V _{L1 to} V _L3 , respectively. Φ ₁ ~Φ ₃ is a timing signal for controlling the load circuit Z ₁ ~Z ₃ respectively. Φ ₁ 'to Φ ₃ ' are timing signals synchronized with Φ _{1 to} Φ ₃ , respectively. The first feature of this embodiment is to divide the internal circuit serving as the load of the voltage limiter circuit into _three of Z ₁ to Z 3, and accordingly, the driving circuit in the voltage limiter circuit is also divided into _three of B _{1 to} B ₃ and the phases are respectively separated. Compensation was performed. Generally, circuits in semiconductor devices include a wide variety of capacities, resistors, inductances, nonlinear elements, or combinations thereof. In addition, they exist on a semiconductor chip in a distributed manner (ie, distributionally). Phase compensation for stably operating feedback amplifiers with such complex loads is extremely difficult. If the load circuit is divided into several types and sizes as in the present embodiment, the design of the feedback amplifier and the phase compensation circuit suitable for each load circuit becomes relatively easy. This makes it possible to stabilize the operation of each drive circuit.

As the division method of the load circuit, the following is considered, for example. (1) Dividing into resistive load and capacitive load, (2) Dividing by load size (consumption current), (3) Dividing by operation timing of circuit, (4) Semiconductor chip of circuit The method of dividing by the physical location in the inside is considered.

In the case of dividing by physical position, it is preferable to disperse the driving circuits B ₁ to B ₃ as necessary.

A second feature of this embodiment is that the signal phi i 'synchronized with the timing signal phi i for controlling each load is input to each drive circuit Bi. In general, the current flowing through a circuit in a semiconductor device varies greatly depending on the operation mode. This means that the impedance of the load changes when viewed from the power supply side. In order to cope with such a load variation, the present embodiment uses the timing signal phi i '. The circuit constants of the feedback amplifier Ai and the phase compensating circuit Ci can be changed by phi i 'so that the characteristics can always be adapted to the operating mode of the load. This made it possible to stabilize the operation of the driving circuit at all times.

In this embodiment, the levels of the operating voltages V _L1 to V _L3 of the load circuits Z ₁ to Z ₃ are all the same. Therefore, only one reference voltage generating circuit is provided, and the output V _R is commonly used in the driving circuits B ₁ to B ₃ . When the operating voltage varies depending on the load circuit, a plurality of reference voltage generating circuits may be provided as shown in FIG. Alternatively, only one reference voltage generation circuit may be provided, and a voltage conversion mechanism may be provided in the drive circuits B ₁ to B ₃ .

가 입력되어 있다. B₁₁, B₁₂의 출력 V_L11, V_L12중의 한쪽이 스위치 SW로 선택되어 부하 Z₁에 공급된다. Φ₁'가 고레벨,

가 저레벨일 때에는 B₁₁이 활성화, B₁₂가 비활성화로 되고, 스위치 SW는 V_L11측에 접속된다. 반대로 Φ₁＇가 저레벨,

가 고레벨일 때에는 B₁₁이 비활성화, B₁₂가 활성화로 되고, 스위치 SW는 V_L12측에 접속된다. 즉, 2개의 구동회로 B₁₁, B₁₂중의 한쪽 만이 부하회로 Z₁에 내부전원전압 V_L1을 공급하는데 사용되고, 다른쪽은 절리된 상태에 있다.26 shows another embodiment of the present invention. The feature of this embodiment is that a plurality of driving circuits (here, two) are provided corresponding to the operation mode of the load circuit Z ₁ , and their outputs are switched to a switch. The driving circuits B ₁₁ and B ₁₂ each include a timing signal Φ ₁ ′ synchronized with the operation of Z ₁ and a compensation signal thereof.

Is input. One of the outputs V _L11 and V _L12 of B ₁₁ and B ₁₂ is selected as the switch SW and is supplied to the load Z ₁ . Φ ₁ 'is high level,

Is low level, B ₁₁ is activated, B ₁₂ is inactive, and the switch SW is connected to the V _L11 side. Φ ₁ 저 low level,

Is at a high level, B ₁₁ is deactivated, B ₁₂ is activated, and the switch SW is connected to the V _L12 side. That is, only one of the two drive circuits B ₁₁ , B ₁₂ is used to supply the internal power supply voltage V _L1 to the load circuit Z ₁ , and the other is in a cut-off state.

In the embodiment of Fig. 24, a method of changing the circuit constant of the driving circuit is used to cope with the change in the load. However, there is a problem that the impedance of the load varies greatly depending on the operation mode, and it is difficult to operate stably in several operation modes only by changing the circuit constant. In this case, the method of this embodiment is effective. This is because each drive circuit should be designed for one operation mode only. For example, there is a very large change in current consumption when Z1 is in operation and in standby. In this case, the feedback amplifier and the phase compensation circuit may be designed so that the driving circuit B ₁₁ operates stably when Z ₁ is in an operating state and B ₁₂ is stable when Z ₁ is in a standby state.

The driving circuit on the side not used in the present embodiment is deactivated, but this is not necessary. This is because the driving circuit on the side that is not used is cut off by the switch.

However, in order to reduce power consumption, it is preferable to leave it in an inactive state. In addition, although the output of the drive circuit is switched by the switch, the switch is unnecessary if the drive circuit is designed to be the output and the impedance when the drive circuit is inactive.

In the embodiment of FIG. 24, since the driving circuit is divided, it is feared that a potential difference occurs between the internal power supply voltages V _{L1 to} V _L3 . If the potential difference between the internal power supply voltages is large, when there is a signal exchange between the load circuits Z ₁ to Z ₃ , a mismatch may occur or an element may be destroyed. Figure 27 shows one way of preventing this. For simplicity, the case where the load and the driving circuit are divided into two is shown. In this embodiment, two internal power supply voltages are connected by two N-channel MOS transistors Q ₁ and Q ₂ . When the threshold voltage of the MOS transistor is set to V _TH , Q ₁ conducts when V _L1 -V _L2 V _TH and Q ₂ conducts when V _L2 -V _L1 V _TH . Thus, the potential difference between V _L1 and V _L2 is maintained within V _TH .

The method of connecting the internal power supply voltages is not limited to that shown in FIG. Some examples are shown in FIGS. 28A-28E. The simplest method is a method of connecting by an element which is regarded as resistance or equivalent resistance as shown in Figs. 28A to 28C. 28d is a method such that the potential difference between the internal power supply voltages does not exceed a predetermined value as in FIG. In this case, diodes D ₁ and D ₂ are used instead of MOS transistors. The potential difference between V _L1 and V _L2 is suppressed within the ON voltage of the diode. FIG. 28E is a method of connecting V _L1 and V _L2 using the signal WK which becomes a high level only immediately after the power is supplied. This is particularly effective to prevent potential difference from occurring when the time constants of the rise of the loads V _L1 and V _L2 are greatly different. Of course, you may employ | adopt the connection method which combined some of FIGS. 27, 28a-28e.

In addition, the connection method described here is effective also for a voltage limiter which does not perform phase compensation.

24 to 27, the load circuit is represented by a single impedance zi for simplicity. However, the load in the actual peninsula is often distributed in the semiconductor chip as shown in FIG. In such a case, the amplifier Ai may be fed back in the middle of the distributed load or at the end of the surface. In the shown example A ₁ roneun under the feedback from the nearest end of the load distribution, but Z ₁₁ ~Z _19, A ₂ roneun at the center of the load Z ₂₁ ~Z _29, A ₃ are as in myeonkkeut the load Z ₃₁ ~Z ₃₉ Each is returning. The advantage of doing this is to compensate for the decrease in the internal power supply voltage due to the impedance of the wiring, and to stabilize the operation of the surface load in the driving circuit. It is preferable to take the input of the phase compensating circuit at the same place when returning from the middle of the distributed load or at the end.

Next, a suitable feedback amplifier and phase compensation circuit used in the present invention will be described.

Fig. 30A shows one embodiment with feedback amplifier Ai and phase compensation circuit Ci. In the figure, reference numeral 21 denotes a differential amplifier, and the MOS transistors Q _{21 to} Q ₂₅ are represented. Reference numeral 22 denotes an output terminal, which is a MOS transistor Q _{26 to} Q ₂₇ . Of the two input terminals of the differential amplifier 21, the reference voltage V _R is input to one side, and V _Li is fed back from the output terminal. Ci is a phase compensation circuit, and a resistor R _D and a capacitor C _D are connected in series. Fig. 30B shows a small signal lamp temporary circuit when the circuit is not fed back. For simplicity, the case where the load is a single capacity C _L is shown. Where gm ₁ and gm ₂ are the differential amplifier, the front conductance of the output stage, r ₁ and r ₂ are the output resistance of the differential amplifier output stage, and C _G is the input capacitance of the output stage (the gate capacitance of Q ₂₆ ).

The frequency characteristics of this circuit are explained using Figs. 31A and 31B. First, the case where phase compensation is not performed is described. Fig. 31A shows the relationship of frequency to gain in the absence of a phase compensating circuit. In the figure, a is the gain vi '/ vi of the differential amplifier 21, b is the gain vo / vi' of the output stage 22, and c is the total gain vo / vi. a and b are frequencies f ₁ and f ₂ , respectively, and start to decrease at a rate of 6db / oct.

From here,

to be. In this example, since f ₁ f ₂ , the total gain c = vo / vi decreases at 6db / oct if the frequency exceeds f ₂ , and at a ratio of 12db / oct above f ₁ . Their points f ₂ and f ₁ are the so-called pole frequencies. As described above, in order for the feedback amplifier to operate stably, the gain at the point where it starts to decrease at 12 db / oct (here, f ₁ ) must be 0 db or less. As can be seen from the figure, if f ₁ and f ₂ are relatively close, this condition is often not satisfied.

Therefore, it is not satisfied in FIG. 31A. A sufficient drop of F ₁ and F ₂ can stabilize the feedback amplifier.

When the phase compensation circuit ci is added here, the frequency characteristic is as shown in Fig. 31B. That is, the gain of the differential amplifier 21 does not change, the gain of the output stage is a characteristic binary bent at three places in the _{P 21, Z 2, P 22} . P ₂₁ and P ₂₂ are width and Z ₂ is called 0 point. The frequency of these points is as follows.

By setting the f ₂ As can be seen in the figure in the vicinity of the pole frequency f ₁ of the differential amplifier, that is bent luggage in f ₁ in the total gain by that that C _D R _D ≒ C _G R ₁ This disappears. As a result, the total gain is the frequency is reduced at a ratio of 12db / oct exceeds, and f ₂₂ at 6db / oct exceeds ₂₁ f. If n is sufficiently made large by C _D = NC _G R ₁ / R ₂ and R _D = r ₂ / n, f ₂₁ and f ₂₂ can be sufficiently dropped, so that the feedback amplifier can be stabilized.

32A shows another embodiment of the feedback amplifier and the phase compensation circuit. In this circuit, phase compensation is performed by inserting a capacitor C _F between an input and an output of the output terminal 22. Fig. 32B shows the small signal equivalent circuit when the circuit is not fed back and Fig. 33 shows its frequency characteristics. In this case, the gain of the differential amplifier is bent at three positions P ₁₁ , Z ₁ , and P ₁₂ . In this case as well, the feedback amplifier can be stabilized by setting F ₁ ≒ F ₂ and dropping F ₁₁ and F ₁₂ sufficiently. The characteristic of this embodiment is that the capacitor C _F for phase compensation is inserted between the input and the output of the amplifier stage, so that the apparent capacitance is increased by the so-called mirror effect. Therefore, even if the actual capacitance is relatively small, phase compensation can be performed, so that the occupied area of the capacitor can be reduced.

Here, the capacitor used for the phase compensation circuit of FIG. 30A or FIG. 32A is demonstrated. These capacitors require very large capacitances (usually hundreds to thousands of PFs) and low voltage dependence. 34A shows one method of realizing this with a conventional CMOS process.

In the figure, reference numeral 101 denotes a P-type semiconductor substrate, 102 denotes an N type well, 103 denotes an N + diffusion layer, 104 denotes separation SiO ₂ , 105 denotes a gate insulating film, and 106 denotes a gate. . The capacitor is formed between the gate 106 and the substrate surface 102a with the gate insulating film 105 interposed therebetween with a conventional mos capacitor. Since a thin gate insulating film is used as the capacitor insulating film, a large capacitance can be obtained with a relatively small area. The difference from the conventional mos capacitor, however, is that the threshold voltage is negated because there are n wells under the gate. This is explained using FIG. 34B. The horizontal axis represents the voltage applied to the capacitor (the gate side is positive), and the vertical axis represents the capacitance. The threshold voltage is the applied voltage V _0. Although, _O V 0 at the time of the electrostatic capacitance changes significantly. Therefore, as long as the voltage in one direction is applied so that the gate axis is positive, the capacitance is almost constant. When a bidirectional voltage can be applied, two capacitors shown in FIG. 34A may be used in parallel to each other in reverse direction as shown in FIG. 34C.

The processes required for producing the capacitor of this embodiment are well-formed isolation region formation, gate insulating film formation, gate formation, diffusion layer formation, and wiring, but these are all processes included in the normal CMOS process.

Therefore, if the semiconductor device is also made of a CMOS process, it is not necessary to add a step in particular to make the present capacitor. In the semiconductor device to which the present invention is applied, the stacked capacitance can be used. For example, a DRAM using a stacked capacitance as a capacitor of a memory cell is an example. In such a case, the stacked capacitance may be used as the phase compensation capacitor. DRAM using stacked capacitance is described in IEEE Journal of solid-state circuits, vol, sc-22, No. 3, pp. 661 to 666 (August 1980). Next, a reference voltage generation circuit suitable for use in the voltage limiter circuit according to the present invention will be described. Note that the reference voltage generating circuit described herein can, of course, also be used for a voltage limiter circuit that does not perform phase compensation. It goes without saying that the embodiment described in Group 1 can be applied. The output voltage V _L of the voltage limiter is made based on the reference voltage V _R. Therefore, the characteristic of V _L can be arbitrarily set according to the characteristic of V _R. When using a voltage limiter circuit in the semiconductor device because important external power supply voltage V _CC V _L dependence of the particular it is necessary to design in particular to note the dependence of V _CC V _R. Regarding this, a characteristic example according to various purposes and a generation method thereof are disclosed in US Patent No.4100437. It goes without saying that these circuits are applicable to the present invention. In the embodiments of FIGS. 24 to 27, the reference voltage V _R was directly input to the drive circuit. However, the voltage obtained in the reference voltage generating circuit is not necessarily limited to an appropriate value as an internal power supply voltage used in the semiconductor device. In this case, the voltage needs to be converted. In addition, in some cases, in order to compensate for the deformation caused by the manufacturing process of the reference voltage, fine adjustment of the voltage, so-called trimming, may be necessary. As a method of voltage conversion and trimming, the method described in the above-mentioned US Patent No.4100437 may be used, but here, a method suitable for a semiconductor device made of a conventional MOS processor is introduced. 35 shows a circuit diagram. In the figure, DA is a differential channel amplification, Q _{31 to} Q ₄₃ are P-channel MOS transistors, and F _{1 to} F ₆ are fuses. V _R is the input voltage (output of the reference voltage generating circuit) and V _R ′ is the output voltage (which is the input of the driving circuit). V _R is input to one of the input terminals of the DA, and the voltage V _R ″ obtained by dividing V _R 'by the MOS transistors Q _{31 to} Q ₄₂ is fed back. When the amplification factor of DA is sufficiently large, the output voltage V _R ′ is given by the following equation.

Here, R ₁ is a resistance value when the circuit of Q ₃₁ to Q ₃₉ is regarded as an equivalent resistance, and R ₂ is a resistance value when a circuit of Ω ₃₉ to Ω ₄₂ is regarded as an equivalent resistance.

Since R ₁ and R ₂ change by cutting the fuse, V _R ′ can be adjusted.

A specific trimming method will be described using FIG.

This figure shows the relationship between the input V _R and the output V _R ′.

In the figure, d is a characteristic when all the fuses are not cut.

When the fuses F ₁ , F ₂ , and F ₃ are cut in sequence, R ₁ becomes large, and as shown by c, b, a, V _R ′ becomes high.

When the fuses F ₄ , F ₅ , and F ₆ are cut in sequence, R ₂ becomes large, and as shown by e, f, and g, V _R ′ becomes low. Therefore, V _R may be observed first, and then, as shown in FIG. 36, the fuse cutting method may be selected so that V _R ′ is closest to the target value V _RO ′. The inventors 'goal is to ensure that V _R ' falls within a range of V _RO '± ΔV _R ' even if V _R is deformed over a wide range. For that purpose, a trimming method adjacent to it when V _R '= V _RO ' + ΔV _R 'is used when some trimming method (e.g. a) is used, as indicated by the dotted line in the figure (e.g. b) In this case, the circuit constant (channel width / channel length of each MOS transistor) should be selected so that V _R '= V _RO ' -ΔV _R '.

37 shows another embodiment of the trimming circuit. When the output voltage V _R ′ is lowered, fuses F ₄ , F ₅ , and F ₆ may be cut in sequence as in FIG. 35. The difference from FIG. 35 lies in the method of increasing the output voltage V _R ′. In this case, the fuse F ₇ may be cut first (the circuit constant is selected so that the input / output characteristic is equal to h in FIG. 36 at this point), and then F4, F5, and F6 may be cut in that order. This circuit has the advantage that the number of fuses is smaller than that of the circuit of FIG. 35, and hence the occupation area can be reduced.

The circuits shown in Figs. 35 and 37 have an advantage that the area occupied by the conventional MOS process is smaller than the circuits described in the above-mentioned US patent. In other words, in the circuit described in the US patent, a resistor is used as a device for dividing the output voltage V _R ', whereas a MOS transistor is used in the circuits of FIGS. 35 and 37.

In order to reduce the current consumption of the circuit, the equivalent resistance of the voltage dividing element must be very large (a few hundred KΩ).

In a normal MOS process, an element having a larger equivalent resistance can be obtained with a smaller area of the MOS transistor than the resistance. However, if MOS transistors are used, the characteristics of V _R 'may change due to variations in the threshold voltage. However, the channel width and channel length of each transistor are sufficiently enlarged to suppress the variations, so that the back gate is connected to the source and the substrate. This can be solved by avoiding the influence of the potential fluctuation and predicting the fluctuation of the threshold voltage and selecting the fuse cutting method.

Next, a MOS transistor used for a trimming circuit will be described with reference to FIGS. 38A and 38B. As described above, the back gate of each transistor is preferably connected to each source in order to suppress the influence of substrate potential variation. For example, when the substrate is of P type, a P-channel MOS transistor may be used as shown in FIG. 38A. In the case where the substrate is N-type, an N-channel MOS transistor may be used in which the conductive type is reversed in FIG. 38A.

Further, as shown in FIG. 38B, the dual well structure allows the potential of the well 112 of the outer axis to be fixed (here, ground), thereby making it possible to further strengthen the substrate potential variation.

Next, a fuse used for the trimming circuit will be described. As the fuse, for example, the same one as that used for defect relief in semiconductor memories such as polycrystalline silicon is used. Thus, if the semiconductor memory has a defect repair circuit, it is not necessary to add a process in particular to make a fuse. The method of cutting the fuse may be a method using a laser beam or an electrical method. The method of using laser light has the advantage that the occupied area can be reduced because the transistor for cutting is unnecessary, and the electrical method has the advantage of not having to use an expensive laser light irradiation apparatus.

FIG. 39A shows another embodiment of the conversion circuit from V _R to V _R ′. The difference between the circuits of FIG. 35 or FIG. 37 is the addition of a P-channel MOS transistor Q ₄₈ . As a result, the maximum value of the output voltage V _R ′ is suppressed to V _CC -V _TP (V _TP is the threshold voltage of the P-channel MOS transistor). This is explained using FIG. 39B. This figure shows the V _CC dependencies of V _R and V _R ′. In the circuit of FIG. 35 or FIG. 37, when V _CC is low, V _R ' _R V _CC . However, in the circuit of FIG. 39A, when V _CC is low due to the addition of Q ₄₈ , the voltage is lowered by V _R '= V _CC −V _TP and V _TP .

An advantage of this embodiment is that the voltage stability of the internal power supply voltage V _L is good when V _CC is much lower than the normal operating state (for example 5 V) (for example 3 V). This is explained using FIG. 39C. This figure is an example of the relationship between the output voltage V _L and the current I _L when V _CC is low in the driving circuit of FIG. 30A or 32A. When the circuit of FIG. 35 or 37 is used to generate V _R ′, the output MOS transistor of the driving circuit (Q _{26 in} FIG. 30a or 32a) is V _L ≒ V _R ≒ V _CC when V _CC is low. The voltage between the drain and the source is approximately 0, and the current driving capability is small. If this reason the output current (load current consumption) is largely V _L I _L ends up to decrease. When used with a separate first circuit 39a for generating a V _R 'On the other hand the V _L ≒ output voltage between the drain, the source of the MOS transistor of a so ≒ V _R -V _TP driver circuit is substantially V _TP (In this example, 0.5V ) Therefore, the current driving capability is relatively large, and the amount of decrease in V _L is small. That is, the amount of voltage fluctuation is reduced by setting V _L slightly lower in advance.

As a result, the operation when the V _CC of the circuit in the semiconductor device operating with the V _L is low becomes more stable, and the operation margin for the V _CC is increased.

In addition, Q ₄₈ of the circuit of FIG. 39A, like the MOS transistor of the trimming circuit described above, preferably has the structures shown in FIGS. 38A and 38B to suppress the influence of substrate potential variation.

Next, a circuit arrangement method and wiring method of the reference voltage V _R or the internal power supply voltage V _L when the present invention is incorporated in an actual semiconductor chip will be described. Although a DRAM is exemplified here as a semiconductor device to which the present invention is applied, the arrangement and wiring method described here are also effective for a voltage limiter circuit that does not perform phase compensation.

40 shows an example of a preferable circuit arrangement and wiring in the case where a DRAM is applied to the voltage limiter circuit. In the figure, (1) is a semiconductor chip, (2a) and (2b) are memory arrays composed of fine mos transistors, and (3a), (3b) and (3c) are peripheral circuits. (4) and (5) are the ground v _gnd , the bonding pads for the external power supply voltage V _CC , respectively, (6) the reference voltage generating circuit, and (7a), (7b), (7c) and (7d) the driving circuit. to be. The voltage limiter circuit is constituted by (6) and (7a) to (7d). 7a, 7b, and 7c generate internal power supply voltages V _L1 , V _L2 , V _L3 for driving the peripheral circuits 3a, 3b, and 3c, respectively. 7d generates an internal power supply voltage V _L4 for driving the memory arrays 2a and 2b.

The characteristic of this embodiment is to separate the reference voltage generating circuit 6 and the driving circuits 7a to 7d, the reference voltage generating circuit is near the bonding pad for ground potential input, and the driving circuit is near each load circuit. Will be placed in. Therefore, the ground wiring 8 from the grounding pad input bonding pad to the reference voltage generating circuit and the internal power supply voltage wirings 11a to 11d from each driving circuit to each load circuit are shortened, and their impedance is reduced.

As a result, noise on the wiring 8 is reduced, so that the ground level of the reference voltage generating circuit is stabilized, and a stable reference voltage V _R is obtained. In addition, since the voltage drop of the internal power supply voltages V _{L1 to} V _L4 due to the impedances of the wirings 11a to 11d is reduced, the level of V _{L1 to} V _L4 is stabilized and the operation of the load circuit becomes stable. Another feature of this embodiment is the method of grounding wiring. First, a dedicated short wiring 8 is provided for the reference voltage generating circuit. Wirings 9a to 9d are provided for other circuits. In other words, each driving circuit and the load circuit are wired in a common line, but are separated from the load circuits of other driving circuits. The advantage of this wiring method is that the noise generated on the ground wiring by the current flowing in each circuit is operated. This can prevent adverse effects on other circuits. In particular, if noise occurs in the ground wiring of the reference voltage generating circuit, the level of all the internal power supply voltages V _{L1 to} V _L4 is changed. Therefore, it is desirable to separate only the ground wiring for the reference voltage generating circuit from other ground wiring. In addition, it is preferable to separate the ground wiring for the memory array from other ground wiring. This is because in a DRAM, when a sense amplifier performs an amplification operation, a large number of data lines (typically, thousands of PFs) are charged and discharged at the same time, causing a large noise in the ground wiring. 41 shows another embodiment of the circuit arrangement and wiring. In this embodiment, the peripheral circuit 3 is concentrated in the center of the chip, and the bonding pads 4 and 5 for the ground and the external power supply voltage V _CC are also arranged in the center of the chip. Also in this embodiment, the reference voltage generator 6 is arranged in the vicinity of the bonding pad for ground potential input, and the drive circuits 7a and 7d are arranged in the vicinity of each load circuit. An advantage of this embodiment is that the wiring length becomes short, as is clear from FIG. This becomes strong against fluctuations in the external power supply voltage V _CC and fluctuations in the current flowing through the load circuit. In other words, in the previous embodiment, since the wiring 10 is long between the _VCC bonding pads and the respective driving circuits, the impedance is large and the level of _VCC is reduced by the current consumption of the load circuit. Of course, this decrease is absorbed in each drive circuit, but if the amount is too large, it may not be absorbed, leading to a decrease in the level of the internal power supply voltage V _L. On the other hand, in this embodiment, since the impedance of the V _CC wiring 10 is small, the load current as large as that can flow. Moreover, the fall of V _CC is also strong. The noise of the ground wiring in FIG. 40 or 41 is particularly problematic because the reference voltage V _R and the internal power supply voltage V _L1 are generated based on the ground potential. On the contrary, when V _R and V _Li are generated based on the external power supply voltage V _CC , the noise of the V _CC wiring becomes a problem. In this case, the reference voltage generating circuit may be disposed near the _VCC bonding pad, and the _VCC wiring may be separated for each circuit.

In the arrangement and wiring method shown in FIG. 40 or 41, the reference voltage V _R is wired from the reference voltage generating circuit to each driving circuit. However, it is preferable that the wiring 12 be shielded. This is to prevent V _R from fluctuating due to noise from other circuits in the semiconductor chip. An example of the shielding method method which can be realized in a normal semiconductor manufacturing process will be described next.

42A and 42B show a plan view and a cross sectional view of each example of the shielded wiring. In the figure, reference numeral 101 denotes a semiconductor substrate, 104 denotes SiO ₂ , 108 denotes a first wiring layer, 109a, 109b, and 109c, a second wiring layer, 113, 114 Is an interlayer insulating film, and 115 is a protective film. 109b is a wiring of the reference voltage V _R. Surroundings 108, 109a, and 109c are shielding wirings, which are fixed at a constant potential (here, ground).

By providing 108 below the 109b, noise due to capacitive coupling with the substrate 101 can be prevented, and by providing 109a and 109c to the left and right, adjacent wiring (not shown). Noise by capacitive coupling with) can be prevented.

42C and 42D show another embodiment of shielded wiring. In this embodiment, V _R is wired in the first wiring layer 108b, and shielding wiring is provided on the left and right 108a and 108c, the lower side 106, and the upper side 109, respectively. By providing a shielding wiring on the upper side, noise by capacitive coupling through the upper space can be prevented, so that shielding is more effective.

42e and 42f, the contact holes 116a, 116c and through holes 117a, 117c are provided to connect the shielding wires so that shielding is completed.

42G and FIG. 42H show another embodiment of wiring shielded. In this embodiment, the polysilicon layer 106 is a V _R wiring. The well 112 is formed below it, and is connected to the upper 1st wiring layer 108 through P-type diffused layer 107a, 107c, and contact hole 116a, 116c. That is, it is shielded by enclosing circumference | surroundings of 106 by 112, 107a, 116a, 108, 116c, and 107c. An advantage of this embodiment is that since the second wiring layer is not used for shielding, it can be used for other purposes as indicated by (109) in FIG. 42G. This is effective for use, for example, in a portion where the wiring of V _R and another wiring cross each other.

In addition, the parasitic capacitance is added between V _R and ground by the above shielding, but this brings about a desirable effect. This is because the parasitic capacitance acts as a so-called decoupling capacitor which bypasses the high frequency noise by reducing the impedance to the high frequency of the V _R wiring.

It is a matter of course that the shield line alone does not interfere with the addition of another capacitor when the capacitance is insufficient as the decoupling capacitor.

In the above example, the potential for fixing the shield wire is set to the ground potential. However, the potential may not necessarily be the ground potential if it is a stable potential. However, it is preferable to set it as the ground potential, since the parasitic capacitance acts as the decoupling capacitor as described above. In particular, the connection to the ground wiring (part of (8) shown in FIG. 40 and FIG. 41) for the reference voltage generating circuit is good in the sense of avoiding noise generated by the operation of other circuits. As described above, when V _R is generated based on V _CC , the shielding line is preferably fixed to V _CC .

43 shows another embodiment of the circuit arrangement and wiring.

In the figure, reference numeral 1 denotes a semiconductor memory chip, 3 denotes a peripheral circuit, 7a, 7b, and 7c, respectively, a driving circuit which generates an internal power supply voltage V _L , 14a, 14b, 14c and 14d are memory arrays using fine mos transistors operated by pulses Φ _P1 , Φ _P2 , Φ _P3 , and Φ _P4 of voltage amplitude V _L using the output of the drive circuit as a power source. Note that the description of the reference voltage generating circuit is omitted here. Fig. 44 also shows the operation timing of these circuits.

가 입력되어 있다.A single external power supply voltage V _CC (for example, 5v) is applied to the semiconductor memory chip 1 of the present embodiment. In the driving circuits 7a, 7b, and 7c, the internal power supply voltage V _L (e.g., 3v) dropped at V _CC is outputted to generate the pulse generating circuits 14a, 14b, 14c, and 14d. Are each entered. Incidentally, the pulse generating circuit has a phase inverse to the timing pulse? _T and the address signal ai shown in FIG.

Is input.

를 외부제어신호(여기에서는 로우 어드레스 스트로브신호 RAS, 칼럼 어드레스 스트로브신호

및 라이트 인에이블신호

를 받아서 내부 타이밍펄스 Φ_T를 발생한다. 주변회로는 칩의 집적도에는 그다지 영향을 받지 않으므로, 굳이 미세소자를 사용할 필요가 없는 것 및 외부 인터페이스에 의해 외부전원전압V_CC로 직접 동작시키고 있지만, 물론 내부전원전압으로 동작시켜도 좋다.The peripheral circuit 3 receives the external address signal Ai and receives the internal address signal ai and

To an external control signal (here, row address strobe signal RAS, column address strobe signal

And write enable signal

And generate internal timing pulse Φ _T. Since the peripheral circuits are not affected by chip integration so much, they do not need to use microelements and are directly operated by the external power supply voltage V _CC by the external interface, but may be operated by the internal power supply voltage.

=1)일때 어레이(2a)와 (2c)가 선택(2b)와 (2d)는 비선택), ai=1(

=0)일때 어레이(2b)와 (2d)가 선택((2a)와 (2c)는 비선택)상태로 된다. 그 때문에 선택된 어레이용의 펄스만이 출력된다. 즉, 제44도에 도시한 바와 같이 ai=0일때에는 펄스 발생회로 (14a)와 (14c)가 타이밍펄스 Φ_T에 의해 Φ_P1, Φ_P3을 출력하여 어레이 (2a)와 (2c)를, 역으로 ai=1일때는 펄스발생회로 (14d)와 (14b)가 타이밍 펄스 Φ_T에 의해 Φ_P4,Φ_P2를 출력해서 어레이(2d)와 (2b)를 동작시킨다. 본 실시예의 특징은 각 구동회로를 각 펄스발생회로에 근접해서 배치하고 또한 펄스발생회로 (14b)와 (14c)에서 구동회로(7b)를 공유하고 있는 것이다. 그 때문에 제3도에 비해서 배선이 짧게 되어 배선의 임피던스가 작게 되고, 이것에 의해서 발생하는 잡음의 레벨을 억제할 수가 있다. 또, 제4도에 비해서 구동회로수가 1개줄고, 이것에 의해서 칩점유 면적과 소비전력을 저감할 수 있다. 또한, 펄스발생회로(14b)와 (14c)는 동시에 동작하지 않으므로 구동회로(7b)는 1개의 펄스발생회로만을구동할 수 있으면 좋기 때문에 전류구동능력을 2배로 할 필요는 없다.The memory operates only the array selected by address. In this example, ai = `` 0 '' (

= 1) when arrays 2a and 2c are selected (2b and 2d are not selected), ai = 1 (

= 0), the arrays 2b and 2d are selected ((2a) and (2c) are not selected). Therefore, only pulses for the selected array are output. That is, as shown in FIG. 44, when ai = 0, the pulse generating circuits 14a and 14c output Φ _P1 and Φ _P3 by the timing pulse Φ _T to generate the arrays 2a and 2c, Conversely, when ai = 1, the pulse generating circuits 14d and 14b output Φ _P4 and Φ _P2 by the timing pulse Φ _T to operate the arrays 2d and 2b. The characteristic of this embodiment is that each driving circuit is arranged close to each pulse generating circuit, and the driving circuits 7b are shared by the pulse generating circuits 14b and 14c. Therefore, compared with FIG. 3, wiring becomes short and wiring impedance becomes small, and the level of the noise which arises by this can be suppressed. In addition, compared with FIG. 4, the number of driving circuits is reduced by one, and the chip occupied area and power consumption can be reduced. In addition, since the pulse generating circuits 14b and 14c do not operate at the same time, the drive circuit 7b only needs to be able to drive one pulse generating circuit, and thus it is not necessary to double the current driving capability.

)이다. (52)는 p채널 MOS트랜지스터 Q₅₅와 N채널 MOS트랜지스터 Q₅₆으로 되는 인버터이며, 그 전원은 V_L이다. ai가 1(전위 Vcc)일때에 Φ_T가 입력되면 내부전원 V_L의 진폭의 펄스Φ_p가 출력된다. 또한, 여기에서 NAND회로는 외부전원전압 V_CC로 동작시키고 있지만, 내부전원전압 V_L로 동작시켜도 좋다.The pulse generating circuits 14a and 14d can be realized by the circuits shown in FIGS. 45A and 45B, for example. In Fig. 45A, reference numeral 51 denotes a two-input NAND circuit consisting of P-channel MOS transistors Q ₅₁ and Q ₅₂ and N-channel MOS transistors Q ₅₃ and Q ₅₄ . The power supply of this circuit is V _CC , and the input is timing pulse and address signal ai (or

)to be. Reference numeral 52 denotes an inverter composed of p-channel MOS transistor Q ₅₅ and N-channel MOS transistor Q ₅₆ , and its power supply is V _L. When Φ _T is input when ai is 1 (potential Vcc), pulse Φ _p of the amplitude of the internal power supply V _L is output. In addition, where the NAND circuit, but to operate in an external power supply voltage V _CC, may even operate in the internal power supply voltage V _L.

타이밍펄스 Φ_T및 펄스 Φ_P1∼Φ_P4는 제 43도 에서 설명한 것과 동일하다.FIG. 46 shows an example in which the number of driving circuits is reduced by one more than in the embodiment of FIG. Address signal ai,

The timing pulses Φ _T and pulses Φ _{P1 to} Φ _P4 are the same as those described in FIG. 43.

In this embodiment, the driving circuits 7a are shared by the pulse generating circuits 14a and 14b, and the shared circuits 14c and 14d to 7b are respectively. As a result, the number of driving circuits is reduced by one compared with the embodiment of FIG. 43, whereby the chip area and power consumption can be reduced. Here, as shown in FIG. 44, 14a, 14b, 14c and 14d do not operate at the same time, respectively. Therefore, the drive circuits 7a and 7b only need to be able to drive only one pulse generating circuit, respectively, and there is no need to double the drive capability.

FIG. 47 shows an embodiment to which the present invention is applied when the memory array is divided into eight. In the figure, (1) is a semiconductor chip, (3) is a peripheral circuit, (2a) to (2h) is a memory array, (7a) and (b) are driving circuits, and (14a) to (14h) are pulse generating circuits. to be. In this embodiment, two of the eight arrays are selected by the address signals ai and aj, and only the selected array operates. (2a) and (2e) when aiaj = 0, (2b) and (2f) when aiaj = 1, (2c) and (2g) when aiaj = 10, and (2d) and (when aiaj = 11 2h) are each selected.

Therefore, only the pulse phi _PK (k = 1 to 8) for the selected array is output. That is, as shown in FIG. 48, when the address signals aiaj = 0, the pulses Φ _p1 and Φ _p5 , when aiaj = 1, the pulses Φ _p2 and Φ _p6 , and when aajaj = 10, the pulses Φ _p3 and Φ _p7 , aiaj = 11 , Pulses Φ _p4 and Φ _p8 are output, respectively. These pulses are output at the timing of these pulses phi _pk (k = 1 to 8) dms phi _T , and their amplitude is an internal power supply voltage V _L.

In this embodiment, two driving circuits 7a and 7b are shared by eight pulse generating circuits for operating the memory array. By doing this, the number of driving circuits can be greatly reduced, and the footprint and power consumption can be reduced.

Finally, an example in which the present invention is applied to a DRAM will be described.

49 is a block diagram of a DRAM to which the present invention is applied. In the figure, reference numeral 201 denotes a bonding pad for supplying a power supply voltage V _cc and is connected to an external power supply. 202 is a differential amplifier, 203 is a supply line of the internal step-down voltage VL, 204 is a starting MOS transistor of a P-channel MOS sense amplifier, 205 is a starting MOS transistor of an N-channel MOS sense amplifier, Reference numeral 206 denotes a P-channel MOS sense amplifier, 207 denotes an N-channel MOS sense amplifier, 208 denotes a memory cell, 209 denotes an N-type well portion of a P-channel MOS sense amplifier, and 210 denotes a cell array unit and a sense. A memory block including an amplifier section, 211 is an X decoder, 212 is a Y decoder, 213 is a short precharge signal line, and 214 is a power supply line V _L / 2. The power supply voltage V _CC is performed in peripheral circuits such as an X decoder, a Y decoder, a gate protection circuit and a signal generating circuit. The internal step-down power supply voltage VL is used for the source power of the P-channel MOS sense amplifier connected to the sense amplifier starting MOS transistor 204 and part of the back gate (well) and the Y decoder of the P-channel MOS transistor in this embodiment. have.

In a so-called CMOS circuit, such as a sense amplifier, when a P-type substrate is used, it is usually formed in a well of a P-channel MOS transistor N-type. In this case, as shown in the cross-sectional view of FIG. 50, the potential of the N well (the back gate of the P-channel MOS transistor) is not the external power supply voltage V _CC , but the operating voltage supplied to the source (in this case, V _L ). desirable. This reason is described next.

For example, if V _CC = 5 V and V _L1 = 3 V, the data line precharge level is 1.5 V. Therefore, the P-channel MOS transistor is subjected to a 1.5 V backgate bias before starting the sense amplifier and to 0 V after starting. Referring to FIG. 6, the threshold voltage (absolute value) before starting the sense amplifier is about 0.86V, and about 0.57V after starting. If the N well voltage is set to V _CC (= 5 V), the voltage becomes 1.1 V and 0.92 V, respectively. This is too large for the case of V _L1 . FIG. 51 is a diagram showing the operating speed of the sense system of the DRAM with respect to the threshold voltage of the P-channel MOS transistor. As can be seen from the figure, the threshold voltage rise of 0.1V corresponds to a delay of about 2ns. In this case, it can be seen that the speed of more than about 5ns is realized by setting the N well voltage to V _L1 (= 3V). have.

Since the CMOS LSI in the era of high integration tends to lower the operating voltage and increase the substrate (well) concentration (the back gate bias effect becomes large), the effect of the present invention becomes more important. Here, the N well voltage is made equal to the internal power supply voltage V _L supplied to the P-channel MOS transistor, so that the N well voltage may be changed due to capacitive coupling. In the embodiment shown in FIG. 49, the data line is precharged to V _L / 2 so that when the P-channel MOS transistor is operated, the drain voltage rises and falls, and the noise is extremely small.

Thus, no problems such as latch up due to fluctuation in the well voltage occur.

Although the foregoing description has been made using the sense amplifier as an example, the same method can be applied to other CMOS circuits. In addition, the present invention is applicable to any CMOS LSI having two or more different operating voltages, not limited to DRAM. In addition, in the embodiment of the present invention, it is clear that the present invention holds true even if the conductivity type and potential relationship of the semiconductor are reversed.

As described above, according to the present invention, the voltage limiter circuit needs to drive many kinds of loads, and the optimum phase according to the load type or operation mode even when the load type or size varies depending on the operation mode. Compensation can be enabled to stabilize the operation of the voltage limiter.

In addition, when there are several load circuits using the internal voltage as the power source in the semiconductor chip, the wiring from each drive circuit to each load circuit can be shortened, so that the noise level can be kept low. In addition, since the number of circuits can be reduced without increasing the driving capability of the drive circuit, the footprint and power consumption can be reduced.

Also, in a CMOS circuit using an internally stepped down operating voltage, the voltage of the back gate (well) of the transistor formed in the well is made equal to the stepped down voltage, thereby making it possible to increase the speed of the circuit and to achieve high integration LSI. Reliability and high speed can be realized in parallel.

(Group 3)

The problem with this technique is that it is not considered for the method of externally checking the internal voltage. For example, in the case of a memory LSI having a voltage limiter, if the internal voltage value generated by the voltage limiter is out of the design value, the operation margin of the internal circuit is narrowed or malfunctions. However, when the memory LSI is inspected by a memory tester or the like, if the internal voltage value is unknown, the above problem cannot be easily confirmed.

If a pad is provided at an internal voltage terminal and a memory tester is connected to the pad, the internal voltage value can be known from the outside.

However, this method has the following problems.

First, there is error in the measurement due to noise on the wiring from the pad to the memory tester.

Second, the voltage value may change depending on the input impedance of the memory tester.

Third, because the memory tester measures analog voltages, it takes longer to measure than to handle digital signals.

An object of this embodiment is to solve the above problems and to provide a semiconductor device in which the internal voltage can be easily inspected by a memory tester or the like from the outside.

In order to achieve the above object, the present embodiment provides a means for comparing an externally specified voltage with an internal voltage and means for outputting the comparison result.

By comparing the externally specified voltage with the internal voltage and outputting the comparison result, the signal drawn to the outside becomes a digital signal. Therefore, compared with the case of directly drawing out the above-mentioned internal voltage terminal, it is less susceptible to noise and the input impedance of the measuring instrument, and it is easier to inspect with a memory tester or the like.

Next, an embodiment will be described with reference to the drawings. In the following description, an example in which the present invention is applied to a DRAM is shown, but the present invention is not limited to a DRAM but can be applied to other semiconductor devices.

52 shows an embodiment. This is a DRAM with a voltage limiter. In the figure, (1) is a semiconductor chip, (2) is a DRAM array, (3) is a peripheral circuit of DRAM, (4) is a voltage limiter, (5) is a comparison circuit, and (6) is a multiplexer and an output buffer. (8) is a test enable signal generation circuit. The voltage limiter 4 generates an internal power supply V _L which is lower than V _CC along the external power supply V _CC . The peripheral circuit 3 of the DRAM is operated by the external power supply V _CC , while the memory array 2 is operated by the internal power supply V _L.

In the present embodiment, a method of checking the voltage of the internal power supply V _L will be described.

The comparison circuit 5 compares V _L with a comparison voltage V _S. In this embodiment, the terminal for inputting V _S is used in combination with the data input terminal Din of the DRAM, but may be a dedicated terminal or may be used in combination with another terminal, for example, one of the address terminals.

The output C of the comparison circuit is output via the multiplexer and the output buffer 6. In this embodiment, the terminal for outputting C is also compatible with the DRAM's data output terminal DOUT, but may be a dedicated terminal.

Comparison output C, when the V _L V _S is high level, V _L V _S when is the low level. Therefore, the internal voltage VL can be known by changing the comparison voltage V _S applied to Din and observing DOUT.

For example, the external power supply V _CC

Within the range of V _L is higher than the V _L min and should not be lower than if the V _L max. To check this, first, V _L min is applied to Din to change V _CC from V _CC min to V _CC max, and confirm that DOUT is always at a high level. Next, V _L max is applied to Din to change V _CC from V _CC min to V _CC max, and confirm that DOUT is always at a low level.

Thus, it is a feature of the present embodiment that the signal output from the DOUT terminal is a digital signal of high level or low level. Therefore, compared with the case of directly outputting an analog voltage, an error due to noise or an input impedance of the memory tester can be avoided, and an error due to an input impedance of the memory tester can be avoided, so that the test by the memory tester becomes easy.

The test enable signal TE is a signal indicating whether V _L is checked or a normal read / write mode. This signal is used to enable the comparison circuit 5 and to switch the multiplexer and the output buffer 6. Although a dedicated terminal for inputting TE may be provided, in this embodiment, a circuit 8 for generating TE is provided.

),칼럼 어드레스 스트로브신호(

)및 라이트 인에이블 신호(

)가 인가되는 타이밍의 조합에 의해서 TE를 발생한다.This circuit uses the row address strobe signal

), Column address strobe signal (

) And write enable signal (

TE is generated by a combination of the timings at which?) Is applied.

This will be explained using FIG. 53A and FIG. 53B.

는

보다도 먼저 인가된다. 역으로 제53b도와 같이

가

보다도 먼저 인가되고, 또한 그때의

가 저레벨일때 회로(8)은 V_L검사모드의 지정이라고 판단하고 TE를 발생한다. 또한

,

,

의 타이밍조합에 의해서 특수한 동작모드를 지정하는 방법에 대해서는, 예를들면 ISSCC Digest of Technical Papers, pp.18∼19(1987년 2월)ISSCC Digest of Technical Papers, pp.18∼19(1987년 2월) 또는 ISSCC Digest of Technical Papers, pp.286∼287(1987년 2월)에 거론되어 있다.In DRAM, in the normal read / write mode, as shown in FIG. 53A.

Is

Is applied before. Conversely

end

Is applied earlier, and then

Is low level, the circuit 8 judges that it is the designation of the V _L test mode, and generates TE. Also

,

,

For example, the ISSCC Digest of Technical Papers, pp. 18-19 (February 1987), and the ISSCC Digest of Technical Papers, pp. 18-19 (February 1987). Or ISSCC Digest of Technical Papers, pp. 286-287 (February 1987).

Here, the input / output method of dedicated signals (V _S , c and TE) used for the inspection of V _L is supplemented.

의 타이밍조합에 의해 만들어진다.The terminals dedicated to these signals may be provided as described above. However, in the embodiment of FIG. 52, the input terminal of V _S is combined with Din, and the output terminal of C is combined with DOUT, respectively.

Is made by the timing combination of

The advantage of this method is that V _L can be inspected using only the DRAM native terminals. Therefore, not only the inspection in the wafer state but also the inspection after being assembled to the package can be performed.

An example of the comparison circuit 5 is shown in FIG.

In Fig. 54, reference numeral 20 denotes a differential amplifier having V _L and V _S as inputs and a node 27 as an output, and N-channel MOS transistors 21, 22, 23 and P-channel. MOS transistors 24 and 25. Numeral 30 denotes an inverter having the node 27 as its input and outputting C as an N-channel MOS transistor 31 and a p-channel mos transistor 32. When V _L is higher than V _S , the node 27 goes low and the output c goes high. When V _L is lower than V _S , the node 27 goes high and the output c goes low.

As a comparison circuit, a single differential amplifier may be used. However, as in the present embodiment, one side can reliably set the level of the output c to a high level (≒ Vcc) and a low level (≒ ov) so as to amplify the output of the differential amplifier back to the inverter. desirable.

In this circuit, since TE is input to the gate of the mos transistor 21, no current flows to the differential amplifier except in the V _L test mode (when TE is at a high level). This can prevent an increase in power consumption during normal operation. In addition, since the P-channel MOS transistor 26 is conducting during normal operation, the node 27 is fixed at a high level.

Next, a method of realizing the multiplexer and output buffer 6 used in the present invention will be described.

55 is an example of a multiplexer and an output buffer. In Fig. 55, (41), (42) and (49) to (52) are inverters, (43) to (48) are NAND gates, (53) and (54) are N-channel MOS transistors. This circuit selects one of the data output Dout of the DRAM and the output C of the comparison circuit and outputs it to the output terminal Dout. Which one to choose is determined by TE (the test enable signal described above) and OE (the output enable signal of the DRAM). When TE is high level and OE is low level (in VL test mode), C is selected, and when TE is low level and OE is high level (in lead mode), dout is selected and output. When both TE and OE are low level (when in write mode or standby), the output terminal Dout is high impedance.

56 shows another embodiment of the present invention. The difference from the previous embodiment is that two of V _S1 and V _S2 are input as comparison voltages, and two of comparison circuits 5-1 and 5-2 are provided. The comparison circuit 5-1 compares the internal voltages V _L and V _S1 , and (5-2) compares V _L and V _S2 , respectively. Compare output C ₁ is V _L V when _S1 is high level, V _L V when _S1 is at low level. Compare output C ₂ is when the V _L V _S2 when the low level, V _L V _S2 is at a high level. The signal C output to the outside is the result of logically multiplying C ₁ and C ₂ by the AND gate 9. In this embodiment, the data input terminal and the output terminal are used together, and four bits are read / written at the same time. The so-called DRAM of X4 bit configuration, the input and output of the comparison result C of the comparative where the voltage V _S1 and V _S2, there are used three of the four data input-output terminal _{I / 0 0 ~I / 0 3} . In the case of the X1 bit structure DRAM as in the previous embodiment, for example, Dout may be used for the output of C, or Din or two of the address terminals may be used for the inputs of V _S1 and V _S2 . The advantage of this embodiment is that it can be seen in one test whether V _L is within a range. For example, V _L is higher than the V _L min is assumed unless should not be lower than V _L max. To check this, V _S1 = V _L min and V _S2 = V _L max. Only minV V _{L L} V _L max when C is at a high level. 57 is shown another embodiment of the present invention. The difference between the above-described two embodiments is that the comparison voltage V _S is designated as a digital signal and the DA is converted into the comparison voltage V _S by the DAC. In this embodiment, the input of the digital signals S _{0 to} S ₃ is made. The terminal is also compatible with the address terminal Ai. The input digital signal is converted into the analog voltage V _S by the DA converter 10. The reference voltage given to the DA converter may be V _CC , but a dedicated voltage VR is preferable. This is because the V _CC dependency of the internal voltage V _L can be measured. In this embodiment, the input terminal of V _R is combined with the data input terminal Din of the DRAM. The feature of this embodiment is that the input as well as the output is a digital signal. Thus is a more easily tested by the memory tester as compared to the former embodiment, also, it is also good to two as well as in the present embodiment, only comparison voltage V _S ppunyiji one for the example, the former embodiment. Next, the DA converter used in the present embodiment will be described. An example of a DA converter is shown in FIG. 58A. In the figure, 61 and 62 are inverters, R and 2R are resistors, where inverters, R and 2R are resistors. Here, the power supply of the inverter 62 is the reference voltage V _R. When the digital signal is input from the terminals S _{0 to} S ₃ , the output voltage of the inverter 62 becomes V _R or OV depending on the input signal. The voltage of the output V _S is

However, it is assumed that the output impedance of the inverter 62 is sufficiently small compared with the resistors R and 2R. 58B shows another embodiment of the DA converter. In the figure, 71 is a decoder, 72 is a MOS transistor, and R is a resistor. This circuit is a voltage obtained by storing and dividing the reference voltage V _R.

Select one of them as output Vs. This selection is made by the signals T ₀ to T ₁₅ which decode the input signals S ₀ to S ₃ by the decoder 71. The characteristic of this circuit is that when the load impedance (the input impedance of the comparison circuit 5 in FIG. 57) is sufficiently large (the circuit in FIG. 54 satisfies this condition), the output voltage Vs is turned on in the MOS transistor 72. It is not affected by resistance.

58A and 58B are four-bit DA converters. However, it goes without saying that the number of bits may be increased or decreased depending on how accurately the internal voltage V _L needs to be set.

Fig. 59 shows another embodiment of the present invention. The characteristic of this embodiment is that the internal voltage V _L is converted to AD and output. For this reason is provided with a register 80 for storing the digital signal S _O ~S _3. Next, the operation of this embodiment will be described according to the timing chart of FIG.

의 타이밍의 조합에 의해 테스트 인에이블 신호 TE를 발생하는 것은 전실시예와 마찬가지이다. 이 시점에서 레지스터(80)의 내용은 최상위비트 S₃만이 1, 다른것은 0인 상태로 설정된다. 이때,비교용전압 V_S는 V_R/2과 같다. 이 V_S와 내부전압 V_L을 비교한 결과, C=0, 즉 V_LB_R/2이면 최상위비트 S₃은 그대로 1로 유지되고, C=0, 즉 V_LV_R/2이면 S₃은 0으로 리세트된다.

The generation of the test enable signal TE by the combination of timings is the same as in the previous embodiment. At this point, the contents of the register 80 are set so that only the most significant bit S ₃ is 1 and the other is 0. At this time, the comparison voltage V _S is equal to V _R / 2. As a result of comparing this V _S with the internal voltage V _L , if C = 0, that is, V _L B _R / 2, the most significant bit S ₃ remains as it is, and if C = 0, ie V _L V _R / 2, S ₃ Is reset to zero.

The register S ₂ is then set to one. At this time, the comparison voltage V _S is V _R / 4 or 3 V _R / 4. As a result of comparing this V _S with the internal voltage V _L , when C = 1, S ₂ remains as it is, and when C = 0, S ₂ is reset to zero. Hereinafter, similarly, S ₁ and S ₀ are determined in order.

를클럭으로써 사용하고 있다. 즉, 먼저

를

보다도 먼저 저레벨로 해서 V_L검사모드를 지정한다. 이것에 의해 TE가 고레벨로 된다. 다음에 RAS는 저레벨로 유지된채

를 상승, 하강시키는 것에 의해 상기의 AD 변환이 행해진다. 이동안, 출력단자 Dout에는 각 회의 비교결과가 차례로 나타나므로 Dout를 관측하는 것에 의해 AD변환의 결과를 알 수가 있다. 본 실시예에 의하면, 내부전압의 검사결과가 디지탈신호로 외부에 출력되므로 내부전압을 외부에서 메모리 테스터등으로 검사하는 것이 용이하게 된다. 이상, 본 발명에 의하면 초대규모 반도체 집적회로를 실제로 마련할 수가 있고, 또한 이들의 특성, 안정동작등도 달성할 수가 있다.The above operation is performed in synchronization with the clock. In this embodiment

Is used as a clock. That is, first

To

The V _L test mode is designated as the low level first. As a result, TE is brought to a high level. RAS is then kept low

The above-mentioned AD conversion is performed by raising and lowering. In the meantime, the comparison result of each time appears in the output terminal Dout one by one, and the result of AD conversion can be known by observing Dout. According to this embodiment, since the test result of the internal voltage is output to the outside as a digital signal, it is easy to test the internal voltage from the outside with a memory tester or the like. As described above, according to the present invention, a super-scale semiconductor integrated circuit can be actually provided, and these characteristics, stable operation, and the like can also be achieved.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example, Of course, it can change variously in the range which does not deviate from the summary.

Claims (15)

A semiconductor substrate, a first conductivity type well provided in a first region of the semiconductor substrate, a first MOS transistor of a channel of a second conductivity type formed in the well, and the second conductivity type of the semiconductor substrate. A semiconductor integrated circuit comprising a second MOS transistor of a channel of the first conductivity type formed in a second region and a voltage conversion circuit provided in a third region of the semiconductor substrate, wherein the voltage conversion circuit is an external power supply. By supplying a voltage, an internal voltage smaller than the external power supply voltage is output at its output terminal, and the output terminal of the voltage conversion circuit is connected to the source of the first MOS transistor, A drain is connected to the drain of the second MOS transistor, a source of the second MOS transistor is connected to a predetermined operating potential, and the first MOS The gate of the transistor is connected to the gate of the MOS transistor of the second, the well has a semiconductor integrated circuit, characterized in that the voltage converter circuit is connected to the output terminal. The third MOS transistor of the second conductivity type channel formed in the well and the fourth MOS transistor of the first conductivity type channel formed in the second region of the semiconductor substrate. And the output terminal of the voltage conversion circuit is connected to the source of the third MOS transistor, and the drain of the third MOS transistor is connected to the drain of the fourth MOS transistor and the first MOS transistor. A source of the fourth MOS transistor is connected to the predetermined operating potential, and a gate of the third MOS transistor is connected to a gate of the fourth MOS transistor and a drain of the first MOS transistor A semiconductor integrated circuit characterized in that the connection, 23. The semiconductor device according to claim 22, further comprising a memory cell comprising one transistor and one capacitor formed in said second region of said semiconductor substrate, and a data line connected to said memory cell. And the third and fourth MOS transistors constitute a sense amplifier for detecting and amplifying a signal read from the memory cell to the data line. 24. The semiconductor integrated circuit according to claim 23, wherein the voltage which precharges said data line is half the voltage of said internal voltage. The semiconductor integrated circuit according to claim 23 or 4, further comprising a decoder for selecting the memory cell, wherein the external power supply voltage is supplied to the decoder. 27. The semiconductor integrated circuit according to claim 25, wherein the internal voltage is supplied to a part of the decoder. 27. The semiconductor integrated circuit according to claim 26, wherein the conductivity type of FIG. 1 is N type and the second conductivity type is P type. A reference voltage generation circuit for generating a reference voltage smaller than the external power supply voltage by being supplied with an external power supply voltage, the first voltage having the reference voltage input to its first input terminal and whose output connected to its second input terminal; A negative feedback amplifier, a first phase compensating circuit for compensating the phase of the output of the first negative amplifier, a second input of the reference voltage to its first input terminal and its output connected to its second input terminal A negative amplifier of, a second phase compensation circuit for compensating the phase of the output of the second negative feedback amplifier, a load circuit supplied with the output of the first negative feedback amplifier or the output of the second negative feedback amplifier And switching means provided between the output of the first negative amplifier and the output of the second negative feedback amplifier and the load circuit, wherein the first negative amplifier or The circuit constant of the first phase compensating circuit is set differently from the circuit constant of the second negative feedback amplifier or the second phase compensating circuit, and the load circuit is inputted by the first signal. The impedance is set to change, and the switch means determines whether the output of the first negative feedback amplifier or the output of the second negative feedback amplifier is determined by a second signal synchronized with the first signal. A semiconductor integrated circuit characterized in that it is connected to the load circuit. 29. The semiconductor integrated circuit according to claim 28, wherein one of said first negative feedback amplifier or said second negative feedback amplifier which is not connected to said load circuit is set in an inactive state by said second signal. A reference voltage generation circuit for generating a reference voltage smaller than the external power supply voltage by supplying an external power supply voltage, a first negative feedback amplifier in which the reference voltage is input to one input terminal thereof, and the first negative feedback amplifier A first phase compensation circuit for compensating the phase of the output of the first load circuit to which the output of the first negative feedback amplifier is supplied, and a second negative feedback amplifier to which the reference voltage is input to one input terminal thereof; And a second phase compensating circuit for compensating the phase of the output of the second negative feedback amplifier, and a second load circuit to which the output of the second negative feedback amplifier is supplied. And a connection circuit for connecting the output of the first negative feedback amplifier and the output of the second negative feedback amplifier with a signal path provided between the circuit and the second load circuit. The semiconductor integrated circuit. 31. The MOS transistor of claim 30, wherein the connection circuit comprises: a first MOS transistor having a source and a gate thereof connected to an output of the first negative feedback amplifier, and a drain thereof connected to an output of the second negative feedback amplifier; And a second MOS transistor whose source and gate are connected to the output of the negative feedback amplifier of 2, and whose drain is connected to the output of the first negative amplifier. 31. The connection circuit according to claim 30, wherein the connection circuit has a resistor whose one end is connected to an output of the first negative feedback amplifier and the other end is connected to an output of the second negative feedback amplifier. Semiconductor integrated circuits. 31. The external circuit of claim 30, wherein the connection circuit has a source or a drain thereof connected to an output of the first negative feedback amplifier, and a drain or a source thereof connected to an output of the second negative feedback amplifier. And an N-channel MOS transistor whose gate is connected to the semiconductor integrated circuit. 31. The circuit of claim 30, wherein the connection circuit has a first and a second diode, and the first terminal of the first diode and the second terminal of the second diode are connected to the output of the first negative feedback amplifier. And a second terminal of the first diode and a first terminal of the second diode are connected to an output of the second negative feedback amplifier. 31. The N-channel MOS transistor of claim 30, wherein the connection circuit comprises an N-channel MOS transistor whose source or drain is connected to an output of the first negative feedback amplifier, and whose drain or source is connected to an output of the second negative feedback amplifier. And a high level signal is applied to the gate of the N-channel MOS transistor immediately after power is turned on.

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