JP3524531B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a very large scale integrated circuit such as a dynamic memory having a storage capacity of 16 Mbits or more.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, a stable reference voltage with little fluctuation due to an external power supply voltage or temperature may be required. For the voltage limiter of the LSI, see, for example, ICS CSI Digest of Technical Papers, pages 272 to 273.
Page, February 1986 (ISSCC Digest of Technic
al Papers, pp.272-273, Feb.1986). As stated in the last paper, D
In a memory LSI such as a RAM (Dynamic Random Access Memory), a voltage lower than an external power supply voltage is generated by a circuit (voltage limiter) provided on an LSI chip and used as a power supply. This internal power supply voltage needs to be a stable voltage with little fluctuation due to the external power supply voltage or temperature in order to stabilize the memory operation, and for that purpose, a stable reference voltage is required. Also,
An LSI having a built-in analog circuit often requires a stable reference voltage as a reference voltage.

Reference voltage generating circuits that meet such requirements include, for example, US Pat. Nos. 3,975,648 and 4,
There is a circuit proposed in No. 100437 and the like. Figure 7
The circuit diagram is shown in. This is a circuit that obtains a stable voltage by utilizing the difference in threshold voltage between an H-channel enhancement type MOSFET (hereinafter abbreviated as EMOS) and a depletion type MOSFET (hereinafter abbreviated as DMOS). In the figure, Q ₉₁ is EMOS, Q ₉₀ , Q ₉₂ , and Q ₉₃ are DMO.
S, and V _CC and V _BB are external power supplies of positive voltage and negative voltage, respectively. The difference in threshold voltage between the EMOS and DMOS becomes the output voltage V _R. The operation of this circuit will be described below.

The currents flowing through Q ₉₀ and Q ₉₁ are I ₉₀ , Q ₉₂ and Q
_The current flowing through ₉₃ is I ₉₁ . Assuming that all four MOSFETs are operating in the saturation region, the following four expressions are established.

[0005] _{I 90 = (β 90/2} ) · (-V TD) 2 ... (1) I 90 = (β 91/2) · (V 99 -V TE) 2 ... (2) I 91 = (β _{92/2) · (V 99} -V R -V TD) 2 ... (3) I 91 = (β 93/2) · (-V TD) 2 ... (4) where V ₉₉ is the voltage at the node 99, V _TE and V _TD are threshold voltages (V _TE > 0, V _TD <of EMOS and DMOS, respectively.
0), β ₉₀ , β ₉₁ , β ₉₂ , β ₉₃ are Q ₉₀ , Q ₉₁ , and
It is a conductance coefficient of Q ₉₂ and Q ₉₃ . (1) ~
(4) from the _{equation, V R = V TE - (} 1+ (β 90 / β 91) - (β 93 / β 92)) · V TD ... (5) where beta ₉₀ and beta ₉₃ Do sufficiently small, Or β ₉₀
If the constants of the respective MOSFETs are determined so that / β ₉₁ = β ₉₃ / β ₉₂ , then V _R = V _TE −V _TD (6) That, EMOS and DM as an output voltage V _R
A voltage having a difference in threshold voltage from OS is obtained, which is a stable voltage that does not depend on the voltage of the external power supply V _CC or V _BB .

In recent years, as the degree of integration of semiconductor devices has increased, there has been a problem that the breakdown voltage is lowered due to the miniaturization of semiconductor elements. This problem can be solved by lowering the power supply voltage of the semiconductor device, but this is not always preferable due to the external interface. Therefore, the power supply voltage applied from the outside remains unchanged (for example, TTL (transistor transistor)).
It has been proposed that the voltage is set to 5V in the case of logic compatibility, and an internal power supply having a voltage lower than that (for example, 3V) is made in the semiconductor device. For example, IEE, Journal of Solid State Circuits, Vol. 22, No. 3, pp. 437-441, June 1987 (IEEE Journal of
Solid-State Circuits, Vol.SC-22, No.3
pp.437-441, June 1987) describes an example in which this method is applied to a DRAM (dynamic random access memory) and a circuit (voltage limiter circuit) for generating an internal power supply from an external power supply.

FIG. 7B shows a circuit diagram of the voltage limiter circuit described in the above document. In the figure, VL is a voltage limiter circuit, which includes a reference voltage generation circuit VR and a drive circuit B. Z is a circuit that operates using the load of the voltage limiter, that is, the output voltage V _L of the voltage limiter as a power supply. The reference voltage generating circuit V _R generates an external power supply voltage V _CC and a stable voltage V _R with little fluctuation due to temperature. Drive circuit B
Is a circuit for generating a voltage V _L having the same voltage value as V _R and a large driving capability, and is a differential amplifier D including Q _{106 to} Q _111.
A and output MOS transistor Q ₁₁₂ . Of the two input terminals of the differential amplifier DA, one side is connected to V _R and the other side is fed back to the output V _L, so that this circuit makes the output V _L follow the input V _R. Operate. Output V
The drivability of _L is determined by the channel width of the output MOS transistor Q ₁₁₂ . Therefore, if you design the channel width of Q ₁₁₂ to match the current consumption of the load,
The stable internal power supply voltage V _L can be supplied to the load.

[0008]

DISCLOSURE OF THE INVENTION Based on the above-mentioned prior art, the present inventors have made a detailed study on a concrete ultra-large-scale integrated circuit (for example, 16 Mbit or more LSI in the case of DRAM). , I found the following problem. This problem is broadly divided into those relating to the reference voltage generating circuit, those relating to the voltage limiter circuit, and those relating to these tests.

First, the problem with the prior art shown in FIG. 7 (a) is that it is difficult to match the characteristics of EMOS and DMOS because they use different devices. In the above explanation, the characteristics are the same for simplification, but in reality, the temperature dependence d of the conductance coefficients β, β
The characteristics such as β / dT and temperature dependence of threshold voltage dV _T / dT are considerably different. This is because of the threshold voltage difference V _TE −V between EMOS and DMOS for the reason described below.
_{This is because the TD} has to be made quite large.

The EMOS must be surely turned off when the gate-source voltage is 0V. For that purpose, the threshold voltage V _TE needs to be set considerably high (for example, V _TE ≧ 0.5 V) in consideration of manufacturing variations and subthreshold characteristics. Also, D
Since the MOS may be used as a current source as shown in the equations (1) and (4), the absolute value of the threshold voltage V _TD is considerably large (for example, in order to suppress the variation in the current value). V _TD ≤-1.5V) must be set. Therefore, V _TE −V _TD becomes considerably large (for example, V _TE −V _TD ≧ 2 V), which means that the impurity profile of the channel region of the MOSFET is significantly different. This allows the MOSFE as described above.
Inconsistency in characteristics as T occurs. An object of the present invention is to solve the above-mentioned problems and to provide a reference voltage generating circuit which does not use a bpletion type FET.

The first problem of the prior art shown in FIG. 7B is that the operation stability of the voltage limiter circuit is not taken into consideration. Generally, an amplifier with feedback such as the drive circuit B of FIG. 7B becomes unstable in operation unless it is designed so as to have a sufficient phase margin. This will be described with reference to FIGS. 2 (a) and 2 (b). Assuming that the relationship between frequency and gain and frequency and phase of the amplifier when feedback is not applied is as shown in the figure, at the frequency where the gain is 0 dB, a numerical value showing how much margin there is in the phase delay of 180 °. However, there is a phase margin. If the phase margin is negative, the feedback amplifier oscillates, and if the phase margin is positive, the operation becomes unstable if the margin is small. It is generally said that a phase margin of 45 ° or more is required for stable operation. For that purpose, of the points (poles) at which the frequency vs. gain characteristics are bent, the second point P ₂ (slope is 6 dB
The gain at the point of changing from / oct to 12 dB / oct) is 0
Must be less than or equal to dB. Since the mission of the voltage limiter circuit is to supply a stable internal power supply voltage to the internal circuit, it goes without saying that it should not oscillate or become unstable in operation.

As a countermeasure against this problem, various methods of compensating for the phase delay are described in, for example, Paul Earl Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, No. 1. Second edition, John Willie and Sons (Paul R. Gray and Robert G. Meyer: Ana
lysys and Design of Analog Intergrated Circuit
s, 2nd Ed., John Wiley and sons Inc. However, applying the phase compensation to the actual voltage limiter circuit of the semiconductor device has the following problems. The circuit serving as a load of the voltage limiter circuit is an internal circuit of an actual semiconductor device, and includes various types such as capacitance, resistance, inductance, non-linear element, and combinations thereof. Moreover, those loads are not constant in time and may change depending on the operation mode of the semiconductor device. For example, the current flowing through the load is significantly different when the semiconductor device is in the operating state and when it is in the standby state. As a result, FIG.
The bias condition of the output stage of the drive circuit B in (b) changes,
As a result, the frequency characteristic of the entire amplifier also changes. In order to operate the voltage limiter circuit stably, it is necessary to ensure that the amplifier having such a complicated property always operates stably. Only the conventional phase compensation method is insufficient for that.

The second problem of the above conventional technique is that no consideration is given to the arrangement and wiring on the semiconductor chip. In particular, when there are a plurality of circuits operating at the internal power supply voltage V _L , the arrangement of the voltage limiter circuit and the output voltage V _L thereof
No consideration was given to the wiring.

The present inventors have discovered that when the above conventional technique is applied to a semiconductor memory, the following problems occur. 3 and 4 show an example in which the above conventional technique is applied to a semiconductor memory. In FIG. 3, 1 is the whole semiconductor memory chip, 3 is a peripheral circuit, 7 is a drive circuit in the voltage limiter circuit (the reference voltage generating circuit in the voltage limiter circuit is omitted here), 14a to
Reference numeral 14d is a pulse generating circuit, and 2a to 2d are memory mats composed of fine MOS transistors.

Since the memory mat uses fine elements, it is operated at the internal power supply voltage V _L. The drive circuit 7 and the pulse generation circuits 14a to 14d are circuits for this purpose. 7
Generates an internal power supply voltage _VL , and 14a to 14d have an amplitude _VL.
Pulse of each of φ _{P1 to} φ _P4 is generated. In this example,
While there are four pulse generation circuits 14a to 14d, only one drive circuit is provided. Therefore, in order to supply the internal power supply voltage V _L generated by the voltage limiter circuit to each pulse generation circuit, a long wiring extending from the upper side to the lower side of the chip is required, and the parasitic impedance of the wiring becomes large, which causes noise generation. Cause. If the wiring width is increased in order to reduce the impedance, then there arises a problem that the area occupied by the wiring on the chip increases.

FIG. 4 corresponds to each pulse generation circuit in order to avoid the problem that the wiring in FIG. 3 becomes long.
This is an example in which drive circuits 7a, 7b, 7c and 7d are provided one by one. By doing so, the wiring length between the voltage limiter circuit and the pulse generating circuit can be shortened, but as many voltage limiter circuits as the number of pulse generating circuits (here, four) are required. Therefore, the area occupied by the voltage limiter circuit on the chip and the current consumption increase compared with the case of FIG. When the number of pulse generation circuits is further increased, the area occupied by the voltage limiter circuit and the power consumption increase
This is a serious problem for semiconductor devices aimed at high integration and low power consumption.

The third problem of the above-mentioned prior art is that CMOS
The operating speed of the circuit is not taken into consideration.
To solve this problem, dynamic random access memory (hereinafter referred to as DRAM) manufactured by making full use of the latest in fine processing technology.
Will be abbreviated).

FIG. 5 shows a part of the circuit block configuration of the N-well type CMOS / DRAM. The memory cell array portion in the figure is on a P-type substrate. The sense amplifier section is composed of N-channel and P-channel MOS transistors, and the N-well corresponding to the substrate of the P-channel MOS transistor is connected to the power supply voltage.

I.S.S.C.C., F.A.M.18.6, 1984, page 282 (ISSC
C, FAM18.6, 1984, p282), when the size of the MOS transistor is reduced to increase the integration degree of the DRAM, problems such as a decrease in stress withstand voltage due to hot carriers of the MOS transistor occur. Occurs. In order to prevent this, it is conceivable to reduce only the power supply voltage used in the memory array, which needs to be miniaturized to improve the degree of integration, in consideration of the stress breakdown voltage. This is because, for example, an external power supply voltage V _CC is applied to the peripheral circuit section (X decoder, Y decoder, etc.) of the DRAM, and an operating voltage V _CC lower than V _CC is applied to the memory cell array section including the sense amplifier.
_L (| V _L | <| V _CC |) is used. That is, the voltage supply line connected to the source of the P-channel MOS transistor of the sense amplifier in FIG. 5 is set to V _L, and the voltage supply line of the peripheral circuit section is set to V _CC .

However, in CMOS / DRAM, it has been found that when the operating voltage of the memory array section is lowered as described above, the operating speed is remarkably reduced. As a result of detailed analysis, it has been clarified that the cause is an increase in threshold voltage due to the back gate bias effect of the P-channel MOS transistor. That is, N in the P-type substrate
When the potential of the source of the P-channel MOS transistor formed in the well is the internal power supply voltage V _L and the potential of the N-well (back gate of the P-channel MOS transistor) is the external power supply voltage V _CC , the P-channel MOS transistor receives V A back gate bias of _CC - _VL is applied, and its threshold voltage rises.

FIG. 6 shows a gate length of 1.2 μm and a gate width of 1
This is a plot of the threshold voltage against the difference (back gate bias) between the back gate (N well) voltage and the source voltage of a 0 μm P-channel MOS transistor. In this example, when a back gate bias of 2V is applied, the threshold voltage of about 0.35V rises. Currently LS
With respect to the power supply voltage V _CC which is often used for I, for example, if V _L = 3 V, the threshold voltage increase of 0.35 V exceeds 10% of the operating voltage, which directly leads to speed deterioration.

Another object of the present invention is to solve the above-mentioned first problem and provide a voltage limiter circuit with stable operation.

Another object of the present invention is to solve the above-mentioned second problem and to provide a voltage limiter circuit with low noise, small occupation area and low power consumption.

Still another object of the present invention is to solve the above-mentioned third problem and to realize a high speed and highly reliable CMOS LSI (la).
rge scale intergrated aircuit).

In addition to the above, it is an object of the present invention to provide an actual configuration of a very large scale integrated circuit.

Yet another object of the present invention is to provide the actual layout of a very large scale integrated circuit.

[0027]

In order to achieve the above object, in the present invention, two enhancement type FETs having different threshold voltages are used, and a potential difference when a constant ratio current is passed through them is taken out. The reference voltage.

In order to solve the first problem described above, in the present invention, when the voltage limiter needs to drive many types of loads, a plurality of drive circuits forming the voltage limiter are provided depending on the type of load. , And phase compensation is applied to each. When the type and size of the load temporally change depending on the operation mode of the semiconductor device, the circuit constants of the drive circuit and the phase compensation circuit are changed according to each operation mode. Alternatively, an individual drive circuit is provided for each operation mode, and those outputs are connected to be the output of the voltage limiter.

The second problem is that a voltage limiter circuit and a load circuit such as a pulse generating circuit that uses its output as a power source are arranged close to each other, and a selection / non-selection relationship is provided by a control signal such as an address signal. This can be solved by sharing one voltage limiter circuit among a plurality of load circuits.

In order to solve the above-mentioned third problem, in the present invention, an M formed in a well in a CMOS LSI.
The back gate (well) voltage of the OS transistor is made equal to the operating voltage supplied to the source terminal.

Since the depletion type FET is not used and two enhancement type FETs having different threshold voltages are used, the difference between the threshold voltages can be made sufficiently small (in principle, no matter how small it is). Good). Therefore, it is easier to match the characteristics of the two FETs as compared with the prior art, and it is possible to obtain a more stable reference voltage than the conventional one.

When the voltage limiter needs to drive many kinds of loads, the drive circuit is divided into a plurality of parts according to the loads, and phase compensation is applied to each of them to obtain the optimum phase according to the kind of the load. Compensation is possible. Also, the circuit constants of the drive circuit and the phase compensation circuit are changed according to the operation mode of the semiconductor device, or a separate drive circuit is provided for each operation mode and the outputs are connected to be the output of the voltage limiter. This makes it possible to perform optimum phase compensation in response to load fluctuations. Thereby, a stable voltage limiter circuit can be created.

By arranging the voltage limiter circuit and the load circuit such as a pulse generating circuit using its output as a power source in close proximity, the impedance of the wiring between them can be reduced and the level of noise generated can be reduced. Can be suppressed. In addition, the number of voltage limiter circuits can be reduced by sharing one voltage limiter circuit among a plurality of load circuits that are in a selection / non-selection relationship by a control signal such as an address signal. Therefore, the area occupied by the circuit and the power consumption can be reduced. Here, the voltage limiter circuit needs to drive only the selected circuit of the load circuits. Therefore, it is not necessary to increase the current drive capability of the voltage limiter circuit by sharing.

In the CMOS / LSI, the MOS transistor formed in the well can prevent the threshold voltage from rising due to the back gate bias effect by setting the well voltage to the internal power supply voltage V _L.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to examples.

In order to facilitate understanding, this description will be divided into first, second and third groups, which will be described in this order.
Therefore, the application to actual very large scale integrated circuits is explained in each group. However, one of ordinary skill in the art will understand that this does not mean that these groups are totally independent. That is,
These groups naturally suggest the combination when it is technically possible to implement the combination. Further, as will be apparent from the following description, the first, second, and third groups are not mutually exclusive technologies, and in most cases, they are more synergistic in combination. Those skilled in the art will understand that this is a technology.

[First Group] An embodiment of the first group of the present invention will be described below with reference to the drawings. In the following description, a case where a positive reference voltage is generated will be described, but a negative reference voltage can be generated by reversing the polarities of the transistors.

FIG. 1A shows a circuit diagram of the first embodiment of the present invention. This circuit uses N-channel MOSFET Q ₆₁
˜Q ₆₃ and P-channel MOSFETs Q ₆₄ and Q ₆₅ , and V _DD is a positive voltage external power supply. N channel MOS
Of the FETs, Q ₆₂ and Q ₆₃ are enhancement type FETs having a standard threshold voltage V _TE (hereinafter abbreviated as EMOS), and Q ₆₁ is an enhancement type FET having a threshold voltage V _TEE higher than V _TE. (Hereinafter abbreviated as EEMOS). The operation of this circuit will be described below.

The P-channel MOSFETs Q ₆₄ and Q ₆₅ share the gate and the source and form a so-called current mirror circuit 70. That is, the ratio between the drain current I ₂ of the drain currents I ₁ and Q ₆₅ of Q ₆₄ operates as a constant. The current ratio (mirror ratio) is Q
_It is determined by the constant ratio of ₆₄ and Q ₆₅ . If the constants of Q _{61 to} Q ₆₃ are equal and all are operating in the saturation region,
The following three equations hold.

I ₁ = (β _EE / 2) · (V ₁ −V _TEE ) ² (7) I ₁ = (β _E / 2) · (V ₁ −V _R −V _TE ) ² (8) _{I 2 = (β E / 2} ) · (V R -V TE) 2 ... (9) where beta _EE conductance coefficient EEMOS (Q _61), conductance coefficient beta _E is EMOS (Q _62, Q ₆₃₎ , V ₁ is the voltage at node 61. From the equations (7) to (9), V ₁ = 2V _R (10) V _R = (V _TEE −xV _TE ) / (2-x) (11) where x = (αβ _E ) / (β _EE ) (12) where α is the mirror ratio of the current mirror circuit 70 (I ₁ :
I ₂ = α: 1). In particular, when the constants of Q ₆₄ and Q ₆₅ are the same, α = 1. At this time, if β _EE ≈β _E, then V _R = V _TEE −V _TE (13). That is, EEMOS and E are used as the reference voltage V _R.
A voltage that is the difference in threshold voltage from the MOS is obtained, which is a stable voltage that does not depend on the voltage of the external power supply V _DD . Incidentally, V ₁ in place of V _R (= 2V _R) may be used as the reference voltage.

The feature of this reference voltage generating circuit is that it is easier to match the characteristics of the MOSFETs as compared with the above-mentioned prior art. In order to operate Q _{61 to} Q ₆₃ in the saturation region, it is sufficient that V _TEE ≧ 2V _TE , that is, V _TEE −V _TE ≧ V _TE . This is because the threshold voltage difference V _TEE −V _TE can be made smaller than in the conventional case (for example, 0.7 V, and the difference in the impurity profile of the channel region can be made smaller than in the conventional case.

In the circuit according to the present invention, the difference in the temperature dependence dV _T / dT of the threshold voltage can be reduced, so that a stable reference voltage can be obtained with respect to the temperature, but the temperature dependence is further reduced. For this purpose, the mirror ratio α may be adjusted. Next, the method will be described. (11) is differentiated by the temperature T of the _{equation, dV R / dT = (1} / (2-x)) · (dV TEE / dT) - (x / (2-x)) · (dV TE / dT) ... (14) Therefore, if the mirror ratio α is set so that dV _TEE / dT = x · dV _TE / dT, the temperature dependence of the reference voltage d
It is possible to make V _R / dT = 0.

The channel length of the MOSFET used in this circuit is preferably long to some extent. For example, in another circuit of a semiconductor device, a MOSFET with a channel length of about 1 μm is used.
Even if T is used, it is preferable to use a MOSFET longer than that, for example, a channel length of 5 μm or more in this circuit. For simplicity of the equations (7) to (9), the drain current in the saturated region depends only on the gate-source voltage, but in reality, it slightly changes depending on the drain-source voltage. The longer the channel length, the smaller the rate of this change (drain conductance), and the better the stability of the reference voltage. Further, in order to suppress the threshold voltage fluctuation due to the short channel effect, it is preferable that the channel length be long.

In the circuits shown in FIGS. 1 (a), 1 (b) and 1 (c), the reference
MOSFET Q for making voltage ₆₁~ Q₆₃Back Gesture
Connected to their respective sources, but with a common
You may make it connect to a board terminal. However, MOSF
The threshold voltage of ET changes depending on the back gate voltage
Therefore, you should connect to the source to avoid the effect.
Is good.

Here, the current mirror circuit used in the present invention will be supplemented. The current mirror circuit is shown in Fig. 1.
The circuit is not limited to the two MOSFETs used in the embodiment (a). For example, the circuit shown in FIG. 1B or 1C may be used. These circuits are known as cascode type and Wilson type, respectively. The characteristic of these circuits is that they have good mirror characteristics. That is, in the current mirror circuit of FIG. 1A, the mirror ratio α changes slightly due to the change of the drain-source voltage of Q ₆₄ and Q ₆₅ , but the circuit of FIG. 1B or FIG. Then, the amount of change is small. Therefore, when applied to the present invention, the mirror ratio can be set more accurately and a more stable reference voltage can be obtained. Also,
As the current mirror circuit, a circuit using a bipolar transistor instead of the MOSFET as shown in FIG. 1D may be used. In the following example, for simplicity,
Although the diagram using the current mirror circuit of FIG. 1A is mainly shown, it goes without saying that the circuits of FIGS. 1B to 1D may be applied to these embodiments.

FIG. 8 shows a second embodiment of the present invention. In this circuit, Q ₆₃ in FIG. 1A is replaced with a resistor R ₆₁ . If the constants of Q ₆₁ and Q ₆₂ are equal and both are operating in the saturation region, the following three equations hold.

[0047] _{I 1 = (β EE / 2} ) · (V 1 -V TEE) 2 ... (15) I 1 = (β E / 2) · (V 1 -V R -V TE) 2 ... (16) I ₂ = V _R / R ₆₁ (17) From these equations, when the mirror ratio α = 1, β _EE ≈β _E is calculated, V _R = V _TEE −V _TE (18) and the reference voltage V _R As a result, the difference voltage between the threshold voltages of EEMOS and EMOS is obtained.

The feature of this embodiment is that EEMOS and EMOS are
That is, the difference in the threshold voltage between and can be made smaller (in principle, it can be smaller) than in the case of FIG. Therefore, it is easier to match the characteristics of the MOSFETs. However, in the normal MOS process, the MOSFET can generally occupy a smaller area than the resistor. Therefore, when the threshold voltage difference may be large to some extent, the embodiment of FIG. 1A is preferable.

FIG. 9A shows another embodiment of the present invention.
The difference from the embodiment of FIG. 1A lies in the method of keeping the ratio of the currents I ₁ and I ₂ constant. In the case of FIG. 1A, the current mirror circuit 70 directly maintains a constant ratio of I ₁ and I ₂ , but in the present embodiment, two sets of current mirror circuits 71 and 72 indirectly realize this. To do. That is, four N
Current mirror circuit 71 composed of channel MOSFET
(This is the above-mentioned cascode type) keeps I ₂ and I ₃ at a constant ratio, and at the same time, a current mirror circuit 72 composed of two P-channel MOSFETs keeps I ₃ and (I ₁ + I ₂ ) constant. Keep to ratio. This keeps the ratio of I ₁ and I ₂ constant. For example, if the mirror ratio of the circuit 71 is I ₂ : I ₃ =
1: 1, the mirror ratio of the circuit 72 is I ₃ : (I ₁ + I ₂ ) =
If it is 1: 2, I ₁ : I ₂ = 1: 1.

The feature of this embodiment is that the drain-source voltage of Q ₆₂ is substantially constant. In the embodiment of FIG. 1A, the voltage at the drain of Q ₆₂ (node 62) is approximately _VDD − | V _TP | (V _TP is the threshold voltage of the P-channel MOSFET), which is the external power supply voltage. _Varies with changes in V _DD . A change in the drain voltage causes a change in the drain current due to the drain conductance, which causes a change in the reference voltage V _R. On the other hand, in this embodiment, Q ₆₂
Since the drain voltage of is kept at 2V _R , a more stable reference voltage can be obtained with respect to V _DD .

This is an embodiment of the same purpose of the circuit of FIG. 9 (b). In this circuit, a current mirror circuit 73 composed of two EEMOSs maintains a constant ratio of I ₂ and I ₄ and a current mirror circuit 7 composed of two P-channel MOSFETs.
2 maintains a constant ratio of I ₄ and (I ₁ + I ₂ ), thereby maintaining a constant ratio of I ₁ and I ₂ .

Although all of the above-described embodiments are circuits that use the threshold voltage difference of the N-channel MOSFET as a reference, the threshold voltage difference of the P-channel MOSFET can also be used as a reference. An example thereof is shown in FIGS. Q ₇₄ is a P-channel MOSFET having a standard threshold voltage V _TP , and Q ₇₃ is a P-channel _MOV having a threshold voltage V _TPE lower than V _TP (negative and large in absolute value).
It is an SFET. _Assuming that both _Q74 and _Q73 are operating in the saturation region, the following two equations hold.

[0053] _{I 1 = (β PE / 2} ) · (-V 3 -V TPE) 2 ... (19) I 2 = (β P / 2) · (V R -V 3 -V TP) 2 ... (20 ) Here, V ₃ is the voltage of the node 63, and β _PE and β _E are Q respectively.
₇₃ and Q ₇₄ are conductance coefficients. From these equations, if I ₁ : I ₂ = 1: 1 and β _PE ≈β _E are calculated, then V _R = V _TP −V _TPE (21), and the threshold of the P-channel MOSFET is set as the reference voltage V _R. A value voltage difference is obtained.

This embodiment is suitable for being incorporated in a semiconductor integrated circuit formed on a P-type substrate that requires a stable reference voltage. As mentioned above, the back gates of the MOSFETs for producing the reference voltage are preferably connected to their respective sources. However, in a semiconductor integrated circuit on a P-type substrate, the N-channel MOSFET is usually formed directly on the substrate, and all of its back gates are connected to a common substrate terminal. Therefore, when the substrate voltage changes, the threshold voltage of the N-channel MOSFET changes. On the other hand, P-channel MOSFET
Is formed in the N-type well, the back gate (well) of each MOSFET can be connected to the source so that it is not affected by the substrate voltage fluctuation. For example, in a DRAM, it is usual to use a P-type substrate and apply a voltage (usually about -3V) generated by a substrate voltage generating circuit provided on the chip to the substrate. However, this substrate voltage is likely to change due to changes in the external power supply voltage and the operation of the memory. In such a case, the circuit of this embodiment is particularly effective. On the contrary, in a semiconductor integrated circuit formed on an N-type substrate, a circuit based on the threshold voltage difference of the N-channel MOSFET is preferable.

Similarly, FIG. 10B also shows a P-channel MOSF.
This circuit is based on the difference in threshold voltage of ET. The difference from the above embodiments is the method of setting the operating point (operating current). The embodiments described so far are so-called self-bias type circuits in which the operating point is automatically determined in the reference voltage generating circuit. However, in this circuit, the circuit 76 for setting the operating point is independently provided. The current I ₅ flowing through the operating point setting circuit 76 is mainly due to the resistance R ₆₂ (MO
It may be replaced by SFET). The operating currents I ₁ and I ₂ of the reference voltage generating circuit are determined by I ₅ and two sets of current mirror circuits 72 and 75. For example, the mirror ratio of the circuit 72 is I ₅ : (I ₁ + I ₂ ) = 1:
2. If the mirror ratio of the circuit 75 is I ₅ : I ₂ = 1: 1,
I ₁ = I ₂ = I ₅ .

Since the operating point setting circuit is independent, this circuit is characterized by less variation in the operating point due to variations in the device than in the self-bias type circuit, and thus less variation in current consumption.

In the self-bias type circuit, it is desirable to add a starting circuit. The start-up circuit is a circuit for preventing the circuit from falling into an undesirable stable point. For example, in the circuit of FIG. 9A, the desirable stable point is the state in which V _R is normally generated as described above. At this time, the voltage V _{3 of the} node 63 = 2V _R ,
Of the voltage V ₄ ≈V _DD − | V _TP |. However, there are other stable points such as I ₁ = I ₂ = 0, and V ₃ =
0, V ₄ = V _DD , VR = 0. In order to prevent the circuit from falling into this stable point, a starting circuit 77 as shown in FIG. 11 may be attached. P-channel MOSFET
Q ₇₅ , Q ₇₆ and resistor R ₆₃ (which may be replaced by a MOSFET) form a current source. Node 60 is charged by the current source because V ₃ = 0 and EEMOS Q ₇₇ is in an emergency state when the circuit is at an undesirable stable point. Q _{78 then} becomes conductive, raising the voltage at node 63 and acting to bring the circuit out of the undesirable stability point. When the circuit reaches the desired stable point, V
₃ exceeds V _TEE and Q ₇₇ becomes conductive, causing the voltage at node 60 to drop. Then, Q ₇₈ becomes non-conductive, and does not affect the operation of the reference voltage generating circuit body.

Next, an example in which the present invention is applied to a DRAM will be shown. FIG. 12 is a configuration diagram of a DRAM provided with an on-chip voltage limiter for operating the memory array at an internal voltage V _L lower than the external power supply voltage V _CC . Internal voltage V
_In order to generate _L , the reference voltage generating circuit according to the present invention is used. In the figure, 6 is a reference voltage generating circuit according to the present invention, 24 is a differential amplifier, 7a and 7b are buffers, 3
Reference numeral 0 is a word line boosting circuit, 2 is a memory array in which memory cells MC are arranged vertically and horizontally, 33 is a sense amplifier, and 31 is a word driver.

Differential amplifier 24 and two resistors R ₂₁ , R
Reference numeral ₂₂ is a circuit for generating the operating voltage V _R ′ of the memory array from the output voltage V _R of the reference voltage generating circuit 6 as in the following equation.

V _R ′ = ((R ₂₁ + R ₂₂ ) / (R ₂₂ )) · V _R (22) Since V _R is based on the threshold voltage difference of the FET as described above, it is not always the memory. It is not always an appropriate voltage as the operating voltage of the array. And performs conversion to V _R 'from V _R by the circuit for that. For example,
If V _R = 1V and V _R ′ = 3V, then R ₂₁ : R ₂₂ = 2: 1. Further, R ₂₁ and R ₂₂ may be variable so that V _R ′ can be finely adjusted, that is, trimming can be performed. As the trimming method, for example, the method described in the above-mentioned US patent can be used.

[0061] buffers 7a and 7b is a circuit for increasing the current driving capability of the V _R '. The buffer is MO
It is composed of a differential amplifier composed of SFETs Q _{21 to} Q ₂₄ and a current source I _25, and an output stage composed of MOSFETs Q ₂₆ and a current source I ₂₇ . Since the configuration of 7b is the same as that of 7a, the illustration is omitted in the figure. Since feedback is applied from the output stage to the input of the differential amplifier, this circuit operates so that the voltages of the outputs V _L1 and V _L2 follow the input voltage V _R ′. That is, it is possible to obtain the outputs V _L1 and V _L2 having a large driving ability without _changing the voltage value. V
_L1 and V _L2 are used to drive the word lines of the sense amplifier and the memory cell, respectively. In this embodiment, a method called word boost is used in which the word line voltage is set higher than the operating voltage (here, V _L1 ) of the memory array. Therefore, the word line boosting circuit 30 is provided.
Therefore, the word line boosting circuit 30 is provided. However, the power source of 30 is not the external power source V _CC but the internal power source V _L2.
Is. Therefore, the word line drive signal φ _X is boosted with reference to V _L2 . The word driver 31 receives φ _X and the decoder output XD and drives the word line WL.

Sense amplifier 3 used in this embodiment
3 is P channel MOSFET Q ₁₂₅, Q₁₂₆And Ncha
Channel MOSFET Q₁₂₇, Q₁₂₈An ordinary commercial consisting of
It is an OS sense amplifier. 33 is φ_STo a high level,
/ Φ_STo low level₁₃₆, Q₁₃₇To
It is activated by making it conductive. However, Q₁₃₇of
Source is external power supply V_CCNot internal power supply V_L1Connected to
Since 33 is activated, the data line
High level side is V_L1In addition, the low level side becomes the installation potential. You
That is, the amplitude of the data line is V_L1Can be suppressed to.

Next, another embodiment in which the present invention is applied to a DRAM
I will introduce an example. FIG. 13 shows a 16M bit to which the present invention is applied.
Circuit diagram of the DRAM, Figure 14 is a layout diagram inside the chip,
FIG. 15 is a detailed layout diagram of the voltage limiter 13.
In addition, in the layout diagram, for simplicity, some times
Roads are omitted. In the figure, 1 is a semiconductor chip, 2
Is a memory array, 31 is a word driver, and 32 is a row driver.
Coder, 33 is a sense amplifier, 34 is a data line precharger
Circuit, 35 is a data line selection circuit, 36L and 36
R is a switch circuit, 37 is a column decoder, and 38 is a main decoder.
Amplifier, 39 is a data output buffer, and 40 is a data input buffer.
Input buffer, 41 a write circuit, 42 a row address buffer
Buffer 43, column address buffer 43, timing
, A sense amplifier drive signal generation circuit 45,
46 is a word line voltage generation circuit, 47 is a data line precharger
And a substrate voltage generating circuit 48. Electric
6 in the pressure limiter circuit 13 is a reference voltage generator according to the present invention.
Raw circuit, 6a is voltage conversion circuit, 7a, 7b, 7c are driving
Circuits 4a, 4b, 4c are ground V_SSBonding pad
External power supply voltage V_CCBonding pad
It is The reference voltage generation circuit 6 uses the external power supply voltage V_CC(This
Stabilized voltage V for 5V here)_R(here
1.1 V), and the voltage conversion circuit 6a generates V_R′
(Here, 3.3V). The drive circuit is V_R′
Based on the power supply voltage V for the memory array _L1For peripheral circuits
Power supply voltage V_L2To occur. In this example, V_L1, V_L2Electric power
Both pressure levels are 3.3V.

The first feature of this embodiment is that the voltage limiter circuit is also applied to the peripheral circuits. V _L1 is 45 and 47, and V _L2 is 32, 37, 38, 40, 41, 4
2, 43, 44, 46 and 48, respectively. That is, the circuits other than the data output buffer 39 operate at the internal power supply voltage V _L1 or V _L2 . By operating the peripheral circuit also at the stabilized voltage V _L1 lower than the external power supply voltage V _CC , the power consumed by the peripheral circuit can be reduced and the operation thereof can be stabilized.

The second feature of this embodiment is that the voltage limiter circuit 13 is arranged in the center of the semiconductor chip. As a result, the wirings 11a and 11 for the internal power supply voltages _VL1 and _VL2 are formed.
The voltage drop due to the impedance of b is reduced. Therefore, operation of the circuit powered by a V _L1, V _L2 is stabilized at high speed.

The third feature of this embodiment is the method of ground wiring. First, a short ground wiring 8 dedicated for the reference voltage generating circuit and the voltage converting circuit is provided. Next, ground wirings 9a and 9b are provided for the drive circuit. The bonding pad 4b for the voltage limiter circuit is
It is provided separately from the bonding pads 4a and 4c for other circuits. This can prevent the noise generated on the ground wiring due to the current flowing when each circuit operates from adversely affecting other circuits. In particular, if noise occurs in the ground wiring of the reference voltage generation circuit and the voltage conversion circuit, the levels of the internal power supply voltages _VL1 and _VL2 fluctuate, affecting almost all circuits in the chip. It is desirable to keep it as short as possible and separate it from other ground wiring. For that purpose, it is most preferable to separate the bonding pad from the bonding pad, but a method in which the bonding pad is shared and separated from the wiring take-out portion may be used. Although not shown in the figure, it is desirable to separate the ground wiring for the memory array from other wirings.
This is because, in a DRAM, when the sense amplifier performs an amplifying operation, a large number of data lines (the capacitances of which are usually several thousand p
This is because F) is charged and discharged at the same time and a large noise is generated in the ground wiring.

The fourth characteristic of this embodiment is the method of wiring the power supply. The bonding pad for the external power supply voltage V _CC is
The memory array 5a and the peripheral circuit 5b are separately provided. The drive circuit 7a for the memory array is arranged close to 5a, and the drive circuits 7b and 7c for the peripheral circuits are arranged close to 5b, respectively. As a result, the voltage drop at the power supply voltages 10a and 10b can be reduced. Of course, this voltage drop is absorbed by each drive circuit, but if the drop is too large, it may not be absorbed and the internal power supply voltage V _L1 or V _L2 may be lowered. In order to prevent this, it is desirable to reduce the impedance of the wirings 10a and 10b as in this embodiment. The separate bonding pads for the peripheral circuit and the memory array are provided so that noise generated on the power supply wire due to the current flowing when the circuit operates may adversely affect other circuits, as in the case of the above-mentioned grounding. This is to prevent giving. The power supplies for the reference voltage generating circuit and the voltage converting circuit are wired from 5b here, but of course, another bonding pad may be provided.

Although not shown in the figure, it is desirable to separate the ground wiring and power supply wiring for the data output buffer from the other ground wiring and power supply wiring. This is because an external load (usually several hundreds of pF) is charged and discharged when the data output buffer operates, so that large noise is generated in the ground wiring and the power supply wiring (the data output buffer operates directly with the external power supply voltage V _CC ). Because it does.

Hereinafter, each part of this embodiment will be described in detail.

First, the reference voltage generating circuit 6 will be described.
It As the reference voltage generating circuit, as shown in FIGS.
The circuits shown in FIGS. 8 to 11 can be used. here
As described above, the influence of substrate potential fluctuation can be reduced.
To achieve this, the back gate of each MOSFET must be
It is desirable to connect to the source. For example, in FIG.
In the circuits of (a) and (b), P-channel MOSFET
Q₇₃And Q₇₄Is the reference voltage V_RBecomes
In this case, Q₇₃And Q₇₄For example, as shown in FIG.
A P-channel MOSFET having the structure shown in (a) and (b) is
You can use it. 16 (a) is a layout diagram, FIG.
(B) is a sectional view. In the figure, 101 is a P-type semiconductor substrate
Plate, 102 N-type well, 103 N + diffusion layer, 10
7 is a P + diffusion layer, 104 is SiO for isolation
₂, 106 are polycrystalline silicon or gold to be a gate
Metal, 113 is an interlayer insulating film, 108 is a wiring layer, and 115 is a protective layer.
The protective film 116 is a contact hole. Source diffusion layer (Figure
(P + diffusion layer on the left side of) and the N well are formed in the wiring layer 108.
Therefore, it is connected. This terminal is shown in Fig. 10 (a),
This corresponds to the node 66 in the circuit diagram of (b). This structure is
It can be made by a conventional CMOS process. FIG. 17
(A) and (b) are examples in which the well has a double structure.
In the figure, 111 is an N-type substrate and 112 is a P-type well.
It In this way, the wells have a double structure and the outer wafer is
By fixing the potential of the module 112 (for example, ground)
Substrate 111 and MOSFET back gate 102
Is electrostatically shielded. Therefore, between them
Interference noise via parasitic capacitance can be prevented, and substrate potential fluctuation
The impact can be eliminated almost completely. The substrate 1
11 is an external power supply V _CCConnect to. This structure
The process is to form a well in a normal CMOS process.
It can be made by adding one, and at a relatively low cost
Great effect can be obtained.

1 (a) to 1 (d), FIG. 8, FIG. 9 (a),
(B) In the circuit of FIG. 11, N-channel MOSFET Q
The threshold voltage difference between ₆₁ and Q ₆₂ becomes the reference voltage. When these circuits are used, N having a structure in which the conductivity types are reversed in FIGS. 16A and 16B or FIGS. 17A and 17B.
A channel MOSFET may be used.

A pair of MOSFs for generating the reference voltage
ET In the case of FIGS. 10 (a) and 10 (b), Q ₇₃ and Q ₇₄ , FIG.
(A) ~ (d), 8, FIG. 7 (a), the layout pattern of (b), Q ₆₁ and Q ₆₂ in the case of FIG. 11) is to geometrically congruent figures, also the direction of placing It is desirable to make them the same in order to reduce the influence of variations in the manufacturing process. For example, the influence of the diffusion layer resistance can be made the same by making the arrangement method of the contact holes on the source / drain diffusion layers the same. Further, by making the channel directions the same, it is possible to eliminate the influence of the difference in mobility depending on the crystal plane direction.

Next, the voltage conversion circuit 6a will be described.
A method of realizing the voltage conversion circuit is shown in FIG. 24 in the figure
Is a differential amplifier, 25 is a trimming circuit, Q _{39 to} Q ₄₇ and Q ₄₉ are P-channel MOSFETs, and F _{4 to} F ₇ are fuses. Examples related to this are shown in FIGS.
9 (a), it will become more apparent with reference to this. This circuit produces a voltage V _R ′ that is a constant multiple of the reference voltage V _R. Also, fine adjustment of the voltage to compensate for variations in V _R due to the manufacturing process (trimming) is possible.

One of the input terminals of the differential amplifier 24 has V
_R is input and V _R ′ is input to the other side of MOSFETs Q _{44 to} Q _47.
And the voltage V _R ″ divided by Q _{39 to} Q ₄₂ is fed back. If the amplification factor of 24 is sufficiently large, the output voltage V _R ′ is given by the following equation.

V _R ′ = ((R _T1 + R _T2 ) / R _T2 ) · V _R Here, R _T1 is a resistance value when a circuit composed of Q _{44 to} Q ₄₇ is equivalently regarded as a resistance, R _T2 Is a resistance value when the circuit composed of Q _{39 to} Q ₄₂ is equivalently regarded as a resistance. Since R _T1 and R _T2 are changed by cutting the fuse, V
_R'can be adjusted. The standard values of V _R and V _R ′ are
As described above, since they are 1.1 V and 3.3 V, respectively, R _T1 : R _T2 = 2: 1 is set when the fuse is not cut. When V _R > 1.1V, R _T2 is increased by cutting F _{4 to} F _6, and when V _R <1.1V, R _T1 is increased by cutting F ₇ and V _R It can be adjusted so that ′ does not deviate significantly from the standard value.

The MOSFETs Q ₄₉ and Q ₅₀ are for setting V _R ′ = 0V in the test mode. In the test mode, the signal T _E becomes V _CC level and the output V _R ′ becomes 0V.

The circuit shown in FIG. 18 is shown in US Pat. No. 410.
Compared to the circuit described in No. 0437, a normal MO
There is an advantage that the occupied area is small when it is manufactured by the S process. That is, in the circuit described in the US patent, the resistor is used as the element for dividing the output voltage V _R ′, whereas in the circuit of FIG. 18, the MOSFET is used.
Is used. In order to reduce the current consumption of the circuit, the equivalent resistance of the voltage dividing element must be quite large (about several hundred kΩ). In a normal MOS process, a device having a smaller area and a larger equivalent resistance can be obtained with a MOSFET than with a resistor. However, if MOSFET is used,
There is a concern that the characteristics of V _R ′ may fluctuate due to the fluctuation of the threshold voltage, but the channel width and channel length of the MOSFET are sufficiently increased to suppress the fluctuation, and the back gate is connected to the source to change the substrate potential. The problem can be solved by avoiding the influence of the above and selecting the fuse cutting method in consideration of the variation in the threshold voltage. The MOSFET used for the trimming is shown in FIGS. 16A and 16B or FIG.
7 (a) and 7 (b) is preferable.

[0078] The reference voltage V _R, the terminals of the V _R 'is desirably to add appropriate capacitor of a large capacitance between the ground. This is to reduce the impedance of V _R and V _R ′ to high frequencies and bypass the high frequency noise. In particular, as shown in FIG. 15, when the wiring 12 a of V _R ′ unavoidably crosses another wiring, it also has the meaning of stabilizing the operation of the voltage limiter circuit (preventing oscillation). The reason for this will be described with reference to FIG.

The drive circuits 7a and 7b generate voltages V _L1 and V _L2 having a large current driving capability from V _R ′, respectively. This V
_L1 , V _L2 itself, or V like the pulse generation circuit 14
The output of the circuit which operates the _L2 as the power supply (the voltage level V _L2) wiring 16 of V _R 'wiring is, V _R' wire 12a of
When it intersects with, a feedback loop is generated via the parasitic capacitance C _C3 between the wirings as shown in 17a to 17c. If the gain of this loop is greater than 1 (0 dB), the circuit will oscillate,
Even if it is smaller than 1, if the margin is small, the circuit operation becomes unstable. In order to prevent this, C is connected between V _R ′ and ground.
_It suffices to insert capacitors C _R1 and C _R2 that are sufficiently larger than _{C1 to} C _C3 to keep the loop gain sufficiently small (for example, -10 dB or less).

An example of a method of realizing the capacitor used here is shown in FIGS. 20 (a) and 20 (b). 20A is a layout diagram and FIG. 20B is a sectional view. In the figure, 101 is a P-type semiconductor substrate, 102 is an N-type well, and 103 is N-type.
+ Diffusion layer, 104 is SiO ₂ for isolation, 1
Reference numeral 05 is a gate insulating film, 106 is polycrystalline silicon or metal to be a gate, 113 is an interlayer insulating film, 108 is a wiring layer, 115 is a protective layer, and 116 is a contact hole. The capacitor is sandwiched between the gate insulating film and the gate 106 and the substrate surface 102, like a normal MOS capacitor.
It is formed between a and. Since a thin gate insulating film is used as the capacitor insulating film, a large capacitance can be obtained in a relatively small area. However, normal M
The difference from the OS capacitor is that the threshold voltage (flat band voltage) is negative because there is an N well under the gate. Therefore, as long as a voltage in one direction is applied so that the gate side becomes positive, the current collecting capacity is almost constant. The steps required to make this capacitor are well formation, isolation region formation, gate insulation film formation, gate formation, diffusion layer formation,
And wiring steps, all of which are included in a normal CMOS process. Therefore, if the semiconductor device is manufactured by the CMOS process,
No additional steps are required to make this capacitor.

FIG. 21 shows a method of realizing the drive circuits 7a and 7b.
It shows in (a). In the figure, 21 is a differential amplifier, which is a MOS
Consisting of FET · Q ₂₁ ~Q _25. 22 is an output stage, M
It is composed of OSFETs Q _{26 to} Q ₂₇ . C _L is a load (memory array or peripheral circuit) of the drive circuit equivalently represented by one capacitor. The reference voltage V _R ′ is input to one of the two input terminals of the differential amplifier 21, and V _L1 (V _L2 ) is fed back from the output stage to the other. Therefore, this circuit operates so that V _L1 (V _L2 ) follows V _R ′. Reference numeral 23 is a so-called position compensation circuit for stabilizing the operation of the feedback amplifier composed of 21 and 22. The MOSFETs Q _{28 to} Q ₃₀ are for setting the output to high impedance when the drive circuit is inactive, and for setting _VL1 ( _VL2 ) to the V _CC level in the test mode. That is, in the inactive state, the test signal TE is at a low level, the activation signal φ ₁ ′ (φ ₂ ′) is at a low level, the gate V _CC level of Q ₂₆ is reached, and the output V
_L1 (V _L2 ) becomes high impedance. Further, at this time, Q ₂₅ and Q ₂₇ are in a non-conducting state, so that the power consumption of the circuit is reduced. In the test mode, TE becomes V _CC level, the gate of Q ₆ becomes low level, and V _CC is directly output. FIG. 21B shows a method of realizing the drive circuit 7c.
Shown in. Also in this circuit, the output becomes high impedance when the activation signal φ ₃ ′ is low level. The phase compensating circuit of this time can be shared by that of 7b (7b and 7c).
Since they are connected in parallel), no phase compensation circuit is provided here.

As described above, the drive circuit 7a sets V _L1 to 7
b and 7c are circuits for generating V _L2 . In the normal state, 7c is always activated, and 7a and 7b are activated only when the memory is in the operating state. Therefore, the activation signal φ ₃ ′ is always at the V _CC level, and φ ₁ ′ and φ ₂ ′ are the operation timings of the memory (details of the timing will be described later in V _CC.
Become a level. In test mode, φ ₁ ′, φ ₂ ′,
φ ₃ ′ becomes all low level and the test signal TE becomes V _CC
Become a level. At this time, both V _L1 and V _L2 become equal to V _CC . This is effective for directly applying the external power supply voltage and examining the operation of the memory (for example, the power supply voltage dependency of access time). Immediately after the power is turned on, it is desirable to activate all φ ₁ ′, φ ₂ ′ and φ ₃ ′ in order to accelerate the rising of V _L1 and V _L2 . Also, as will be described later, V _L2 is used to generate the word line voltage V _CH and the substrate voltage V _BB . Therefore, if φ ₂ ′ is activated when the voltage levels of V _CH and V _BB deviate from the standard values, the stability of these voltages can be improved. The high level of the activation signals φ ₁ ′, φ ₂ ′, φ ₃ ′ and the test signal TE is set to V _CC instead of V _L2 because the P channel MOSFETs Q ₂₈ and Q ₂₉ are surely non-conductive. This is to put it in a state.

The drive circuits 7a and 7b must have a large current drive capability. 7 when the memory is active
This is because a and 7b need to drive a large (hundreds to thousands of pF) load capacitance. In particular, 7a must drive a large number of data lines when the sense amplifier performs an amplifying operation. For example, if the capacity of one data line is 0.3p
F and the number of sense amplifiers operating at the same time is 8192, the total capacitance becomes 2500 pF. Therefore, 7
As the output MOSFETs Q ₂₆ of a and 7b, for example, those having a channel width / channel length of about 3000 μm / 1.2 μm are used. 7c needs to have a current drivability capable of guaranteeing a leak current when the memory is in a standby state, so that the output MOSFET is 100 μm / 1.2 μm.
The degree is enough.

The connection circuit 15 is for preventing the potential difference between V _L1 and V _{L2 from} becoming too large. V _L2
This is because a large potential difference between V _L1 and V _L1 may cause a mismatch in signal transfer between the memory array and the peripheral circuit. An example of this circuit is shown in FIG. In the figure, Q ₁ , Q ₂ ,
Q ₅ is an N channel MOSFET, Q ₄ is a P channel MOS
It is a FET. When the threshold voltage of the N-channel MOSFET is V _TN , Q ₁ is Q ₂ when V _L1 −V _L2 > V _TN.
Respectively conduct when V _L2 −V _L1 > V _TN . Therefore, the potential difference between V _L1 and V _L2 is kept within V _TN . Q
_A signal WK which becomes high level only immediately after the power is turned on is input to the gate of ₅ . This is particularly effective in preventing a potential difference from occurring when the load time constants of V _L1 and V _L2 differ greatly. MOSF with relatively small conductance even when all of Q ₁ , Q ₂ and Q ₅ are non-conducting
ET and Q ₄ are conducting. This serves, for example, so that V _L1 = V _L2 while the memory is idle.

In the memory array 2, the MOSFET Q
_The so-called 1-transistor / 1-capacitor type dynamic memory cell MC _ij composed of ₁₂₁ and the capacitor C ₁₂₂ is
It is arranged at the intersection of the word line WL _i and the data line DL _j . Although only two word lines and one pair of data lines are shown in the figure, a large number are arranged vertically and horizontally. One end PL (plate) of the capacitor C ₁₂₂ is connected to a direct current. The voltage level is arbitrary, but capacitor C ₁₂₂
From the viewpoint of the withstand voltage of
2 or V _L1 / 2 is desirable.

The word driver 31 has a row decoder 32.
Is a circuit for driving the selected word line by receiving the output of. In this embodiment, the word line voltage is set higher than the operating voltage of the memory array (here, V _L1 = 3.3V). A so-called word line boosting method is adopted. The advantage of this method is that the storage voltage of the memory cell can be increased. Therefore, the voltage V _CH (V _CH > V _L1 ) generated by the word line voltage generation circuit 46 is supplied to the selected word line.

The sense amplifier 33 is a circuit for amplifying a minute signal on the data line, and is an N-channel MOSFE.
It is composed of a flip-flop composed of T · Q ₁₂₅ and Q ₁₂₆ and a flip-flop composed of P-channel MOSFETs Q ₁₂₇ and Q ₁₂₈ . The sense amplifier sets MOSFETs Q ₁₃₆ and Q ₁ with φ _S at high level and / φ _S at low level.
It is activated by putting ₃₇ into conduction.

The data line precharge circuit 34 is a circuit for setting each data line to a predetermined voltage V _P before reading the memory cell. By applying the precharge signal φ _P , the MOSFETs Q _{129 to} Q ₁₃₁ are rendered conductive, and the voltage of the data line DL _j / DL _j becomes equal to V _P. The data line precharge voltage V _P may be any voltage, but from the viewpoint of reducing the data line charging / discharging current, it is 1/2 of the operating voltage of the memory array, that is, V _L2 /
It is desirable to set it to 2.

The data line selection circuit 35 receives the output φ _YS of the column decoder 37 and outputs the selected data line pair to MO.
Input and output lines through _{SFET · Q 132, Q 133 I} / O, / I
It is a circuit connected to / O. In the present embodiment, a so-called multi-divided data line is used in which only one column decoder 37 is arranged at the end and its output φ _YS is distributed to a plurality of data line selection circuits. This is effective in reducing the occupied area of the column decoder.

In this embodiment, the sense amplifier 33, the data line precharge circuit 34, and the data line selection circuit 35 are shared by the left and right memory arrays, so-called shared sense,
A method called shared I / O is adopted. This is effective in reducing the occupied area by sharing 33, 34 and 35. Therefore, switch circuits 36L and 36R controlled by switch signals φ _SHL and φ _SHR are provided between the memory array and 33, 34 and 35.

Main amplifier 38, data output buffer 3
A data input buffer 40 and a write circuit 41 are circuits for inputting / outputting data. When reading, the data latched in the sense amplifier 33
Via the main amplifier 38 and the data output buffer 39,
It is output to the data output terminal Dont. For writing,
The data input from the data input terminal Din is set in the input / output line via the data input buffer 40 and the write circuit 41, and is further written in the memory cell through the data line selection circuit 35 and the data line. In this embodiment, as described above, 38, 40, 41 are operated by the internal power supply voltage V _L2 to reduce power consumption and stabilize the operation. Only the data output buffer 39 has an external power supply voltage V _CC for convenience of an external interface (here, TTL compatible).
It is operated at (= 5V).

The row address buffer 42 and the column address buffer 43 are circuits which receive the external address signal A and supply address signals to the row decoder 32 and the column decoder 37, respectively. Timing generation circuit 44
Is a circuit which receives external control signals / RAS, / CAS, / WE and generates a timing signal necessary for the operation of the memory. These circuits are also operated at _VL2 with the internal power supply voltage to reduce power consumption and stabilize the operation.

As described above, the word line voltage generating circuit 46 is a circuit for generating the word line voltage V _CH (here, about 5 V) (this voltage is also used in the switch circuit as described later). Data line precharge voltage generation circuit 47
Is the data line precharge voltage V _P (here, 1.65).
It is a circuit for generating V). The substrate voltage generation circuit 48 is
This is a circuit that generates a voltage V _BB (here, −2 V) applied to the semiconductor substrate. The power supply for these circuits is regulated V _L1 or V _L2 rather than V _CC . for that reason,
Even if V _CC changes, there is an advantage that the fluctuation of the output voltage is small.

Next, the operation of reading from the DRAM will be described with reference to the operation waveform diagram of FIG.

In the standby state (both / RAS and / CAS are at high level), the data line precharge signal φ _P and the switch signals φ _SHL and φ _SHR are both at high level (= V _L2 ).
And the data lines DL, / DL are set to V _P. The sense amplifier drive signals φ _SAN , φ _SAP and the input / output lines I / O, / I / O are also precharged to V _P (these precharge circuits are not shown in FIG. 13). In this state, of the drive circuit activation signals of the voltage limiter, only φ ₃ ′ is high level (= V _CC ), φ ₁ ′,
φ ₂ ′ is low level. Therefore, only the drive circuit 7c for standby, which consumes less power, is activated, and the level of the internal power supply voltage V _L2 is maintained. Further, the level of V _L1 is also held through the connection circuit 15. Large current drive capability but large power consumption 7
a and 7b are inactive. By doing so, the power consumption during standby can be reduced.

When / RAS becomes low level, first, the drive circuit activation signal φ ₂ ′ for the peripheral circuit becomes high level (= V _CC ).
become. As a result, 7b having a large current drive capability is activated, and a large current can be supplied to the peripheral circuit that operates using _VL2 as a power supply. The precharge signal φ _P becomes low level (= 0 V), the selected switch signal on the memory array side (φ _{SHL in} the case of FIG. 23) is boosted to the V _CH level, and the switch signal on the opposite side (see FIG. 23). In this case, φ _SHR ) becomes 0V. The reason why φ _SHL is boosted is as follows. The voltage amplitude of the sense amplifier is V _L1 as described later, but when the level of φ _SHL is V _L2 , the voltage amplitude of the data line decreases to V _L2 −V _TN, and as a result, the storage voltage of the memory cell also increases. V _L2- V _TN (V _TN is N
Channel MOSFETs Q ₁₂₃ and Q ₁₂₄ threshold voltage). This can be prevented by boosting φ _SHL, and the storage voltage of the memory cell can be secured.

Next, when the row address buffer 42 and the row decoder 32 operate, one word line WL _i is selected and its voltage becomes V _CH . The signal charge is read from each memory cell on WL _i to each data line, and the potential of the data line changes. The operation waveform of FIG. 18 is an example in the case where a high potential (≈V _L1 ) has been stored in advance in the capacitor of the memory cell, and the potential of the data line DL _j slightly rises and is between / DL _j. There is a potential difference.

Prior to the operation of the sense amplifier, the drive circuit activation signal φ ₁ ′ for the memory array is set to the high level (=
V _CC ). Thus, the drive circuit 7a is activated, it becomes possible to supply a large current to the sense amplifier driving signal generating circuit 45 which operates the V _L1 as the power source. Then φ
_S becomes high level (= V _L2 ) and / φ _S becomes low level (= 0 V). As a result, the MOSFETs Q ₁₃₆ and Q ₁₃₇ become conductive, φ _SAN is grounded through Q ₁₃₆ , and φ _SAP is connected to V _L1 through Q ₁₃₇ . As a result, a minute potential difference between the data lines DL _j / DL _j is amplified, and one (DL _{j in} the case of FIG. 23) becomes _VL1 and the other (/ in FIG.
DL _j ) becomes 0V.

When / CAS becomes low level, column add
The buffer buffer 43 and the column decoder 37 operate to operate one
The data line of is selected. This enables the data line selection signal.
No. φ _YSIs at a high level (= V_L2), And the data line selection circuit
The data line is connected to the input / output line through 35. sense
The data latched in the amplifier 33 is input / output line,
The data is output via the in-amplifier 38 and the data output buffer 39.
It is output to the data output terminal Dont.

When / RAS returns to the high level, the word line WL _i first becomes the low level, and φ _S , / φ _S , φ _SHL ,
φ _SHR and φ _P return to the original level. The drive circuit activation signal φ ₁ ′ for the memory array is low level (= 0V) here.
Then, the drive circuit 7a becomes inactive. further,/
When CAS returns to the high level, the drive circuit activation signal φ ₂ ′ for the peripheral circuit also becomes the low level (= 0 V), and the drive circuit 7
b becomes inactive.

As is clear from the above description, the activation signals φ ₁ ′ and φ ₂ ′ of the drive circuit attain the high level only when necessary. That is, φ ₁ ′ is from immediately before the start of the operation of the sense amplifier until / RAS returns to the high level.
φ ₂ ′ goes high when / RAS or / CAS is low, respectively. As a result, the drive circuit 7
It is possible to reduce the power consumed by a and 7b.

As described above, according to this embodiment,
It is possible to make a reference voltage generation circuit that uses the threshold voltage difference between enhancement type FETs as a reference, without using depletion type FETs. Enhancement type F
Matching the characteristics of the ETs is easier than matching the characteristics of the depletion-type and enhancement-type FETs, and thus a more stable reference voltage than before can be obtained. Therefore, when applied to the voltage limiter of the memory LSI described above, for example, a more stable internal power supply voltage can be generated.

[Second Group] Hereinafter, an embodiment of the second group of the present invention will be described with reference to the drawings. In the following description, an example in which the present invention is mainly applied to a semiconductor device based on MOS technology is shown, but the present invention can also be applied to other semiconductor devices such as bipolar and BiCMOS technology. Further, the case where the external power supply voltage and the internal power supply voltage are positive will be described, but even when the power supply voltage is negative, the present invention can be applied by reversing the polarities of the transistors.

First, the basic concept of the second group will be described.

FIG. 24 shows this embodiment. In the figure, VL is a voltage limiter circuit, the internal power supply voltage V _L1 ~V _L3 (hereinafter, described as V _Li (i = 1,2,3)) from the external power supply voltage V _CC generates. The voltage limiter circuit VL includes a reference voltage generation circuit VR and drive circuits B _{1 to} B ₃ (hereinafter B _i (i =
1, 2, 3))). The reference voltage generation circuit VR generates a stable voltage V _R that is less affected by the external power supply voltage V _CC and temperature, and each drive circuit B _i (B _{1 to} B ₃ ).
Generates a voltage V _L1 having a large current drive capability based on V _R. Each drive circuit B _i comprises a feedback amplifier A _i and a phase compensation circuit C _i (i = 1, 2, 3). Z ₁ to Z ₃ is a circuit in the semiconductor device as a load of the voltage limiter circuit VL, it operates as a power source V _L1 ~V _L3, respectively. φ ₁ ~
φ ₃ is a timing signal for controlling the load circuits Z _{1 to} Z ₃ , respectively. φ ₁ '~φ _3' is a timing signal synchronized with phi ₁ to [phi] _3, respectively.

The first characteristic of the present embodiment is that the internal circuit which becomes the load of the voltage limiter circuit is divided into three parts Z _{1 to} Z ₃ , and the drive circuit in the voltage limiter circuit is also divided into B _{1 to} B 3 accordingly. _This means that it was divided into 3 parts and the phase compensation was applied to each. Generally, circuits in a semiconductor device include extremely various types such as capacitance, resistance, inductance, non-linear element, and combinations thereof. Moreover, they are distributed on the semiconductor chip (that is, in a distributed constant manner).
Exists. Phase compensation for stable operation of a feedback amplifier having such a complicated load is extremely difficult. If the load circuit is divided into a plurality of types and sizes as in the present embodiment, it becomes relatively easy to design the feedback amplifier and the phase compensation circuit suitable for each load circuit. This makes it possible to stabilize the operation of each drive circuit.

The following method can be considered as a method of dividing the load circuit.

A method of dividing into a resistive load and a capacitive load.

A method of dividing according to the size of the load (current consumption).

A method of dividing the circuit according to the operation timing.

A method of dividing a circuit by a physical position in a semiconductor chip.

When divided by physical position, it is desirable to disperse the drive circuits B _{1 to} B ₃ as needed.

The second characteristic of this embodiment is that each drive circuit B _i
The signal φ _i ′ synchronized with the timing signal φ _i for controlling each load is input to. In general, the current flowing through a circuit in a semiconductor device greatly changes depending on the operation mode. This means that the impedance of the load changes when viewed from the power supply side. In order to cope with such load fluctuation, in this embodiment,
The timing signal φ _i ′ is used. With φ _i ′, the circuit constants of the feedback amplifier A _i and the phase compensation circuit C _i can be changed so that the characteristics can be always adapted to the operation mode of the load. Thereby, the operation of the drive circuit can be always stabilized.

In this embodiment, the operating voltages V _{L1 to} V _L3 of the load circuits Z _{1 to} Z ₃ are assumed to have the same level. Therefore, only one reference voltage generating circuit is provided, and its output V _R is commonly used by the drive circuits B _{1 to} B ₃ . When the operating voltage differs depending on the load circuit, a plurality of reference voltage generating circuits may be provided as shown in FIG. Alternatively, only one reference voltage generation circuit is provided and the drive circuits B ₁ to
A voltage conversion mechanism may be provided in B ₃ .

FIG. 26 shows another embodiment of the present invention. The feature of the present embodiment is that a plurality of (here, two) drive circuits are provided corresponding to the operation mode of the load circuit Z ₁ and the outputs thereof are switched by a switch. Drive circuit B ₁₁ , B
Each timing signal phi _i is synchronized with the operation of the Z ₁ 'and its complement signal / phi _i' is input to the _12.
One of the outputs V _L11 and V _L12 of B ₁₁ and B ₁₂ is selected by the switch SW and supplied to the load Z ₁ . When φ ₁ ′ is high level and φ ₁ ′ is low level, B ₁₁ is activated, B _11
12 is deactivated and the switch SW is connected to the V _L11 side. On the contrary, when φ ₁ ′ is low level and / φ ₁ ′ is high level, B ₁₁ is deactivated and B ₁₂ is activated, and switch SW
Is connected to the V _L12 side. That is, two drive circuits B
Only one of ₁₁ and B ₁₂ is used to supply the internal power supply voltage V _L1 to the load circuit Z ₁ and the other is disconnected.

In the embodiment shown in FIG. 24, the method of changing the circuit constant of the drive circuit is adopted in order to deal with the load fluctuation. However, the impedance of the load changes significantly depending on the operation mode, and it may be difficult to operate stably in a plurality of operation modes simply by changing the circuit constant. In such a case, the method of this embodiment is effective. This is because each drive circuit may be designed only for one operation mode. For example, assume that there is a very large change in current consumption between when Z ₁ is in the operating state and when it is in the standby state. In this case, the feedback amplifier and the phase compensation circuit should be designed so that the drive circuit B ₁₁ operates stably when Z ₁ is in operation, and the drive circuit B ₁₂ operates stably when Z ₁ is in standby. Good.

In this embodiment, the drive circuit which is not used is inactivated, but this is not always necessary.
This is because the unused drive circuit is separated by the switch. However, in order to reduce the power consumption, it is desirable to keep it in the inactive state. Further, although the output of the drive circuit is switched by the switch, if the output is designed to have a high impedance when the drive circuit is in the inactive state, the switch is unnecessary.

[0118] In the embodiment of FIG. 24, for dividing the driving circuit, there is a concern that a difference in potential occurs between the internal power supply voltage V _L1 ~V _L3. And the potential difference between the internal power supply voltage is large, or occurred mismatch when there is exchange of the load circuit Z ₁ to Z ₃ signals therebetween, sometimes elements to destroy. FIG. 27 shows one method of preventing this. For simplification, the case where the load and the drive circuit are divided into two is shown. In this embodiment, two internal power supply voltages are connected by _two N-channel MOS transistors Q ₁ and Q ₂ . Assuming that the threshold voltage of the MOS transistor is V _TH , Q ₁ becomes Q ₂ when V _L1 −V _L2 > V _TH.
Respectively conduct when V _L2 −V _L1 > V _TH . Therefore, the potential difference between V _L1 and V _L2 is kept within V _TH .

The method of connecting the internal power supply voltages to each other is shown in FIG.
It is not limited to that shown in FIG. 28 (a) to (e) show some examples. The simplest method is to connect by a resistance or an element that can be equivalently regarded as a resistance, as shown in FIGS. FIG.
As in FIG. 27, this is a method of preventing the potential difference between the internal power supply voltages from exceeding a certain value. Here, diodes D ₁ and D ₂ are used instead of the MOS transistors. V
The potential difference between _L1 and V _L2 is suppressed within the on-voltage of the diode. FIG. 6E shows a method of connecting V _L1 and V _L2 by using a signal WK which becomes high level only immediately after the power is turned on. This is particularly the case where the time constant of the rise of the load V _L1 and V _L2 are significantly different, it is effective to prevent a potential difference from occurring. Of course, FIG. 27 and FIG.
You may employ | adopt the connection method which combined some among (a)-(e).

The connection method described here is also effective for a voltage limiter without phase compensation.

24 to 27, for simplicity, the load circuit is represented by a single impedance Z _i . However, the load in an actual semiconductor device is often distributed in the semiconductor chip as shown in FIG. In such a case, the feedback may be applied to the amplifier A _i from the distributed load in the middle or at the far end. In the example of the figure, feedback is applied to A ₁ from the near ends of the distributed loads Z _{11 to} Z ₁₉ .
From the A ₂ the central portion of the load Z ₂₁ ~Z _{2 9,} the load to the A ₃ Z ₃₁
~ Returning from the far end of Z ₃₉ respectively. The advantage of doing this is that it is possible to compensate for the drop in the internal power supply voltage due to the impedance of the wiring, and to stabilize the operation of the load far from the drive circuit. When the feedback is applied from the middle of the distributed load or from the far end, it is desirable to take the input of the phase compensation circuit from the same point.

[Feedback Amplifier and Phase Compensation Circuit] Next, the feedback amplifier and phase compensation circuit suitable for use in the present invention will be described.

FIG. 30A shows an embodiment of the feedback amplifier Ai and the phase compensation circuit C _i . In the figure, 21 is a differential amplifier composed of MOS transistors Q ₂₁ to Q _25. 22 is an output stage, which is composed of MOS transistors Q ₂₆ and Q ₂₇ . The reference voltage V _R is input to one of the two input terminals of the differential amplifier 21, and V _L is fed back from the output stage to the other. C _i is a phase compensation circuit, and a resistor R _D and a capacitor C _D are connected in series. FIG. 30B shows a small signal equivalent circuit when the feedback of this circuit is not applied.
For simplicity, the case where the load has a single capacitance C _L is shown. Here, g _{m 1} and g _m2 are differential amplifiers and output stage transfer conductances, r ₁ and r ₂ are differential amplifiers and output stage output resistances, and C _G is output stage input capacitance (Q ₂₆
Gate capacity).

The frequency characteristic of this circuit is shown in FIG.
An explanation will be given using (b). First, the case where phase compensation is not performed will be described. FIG. 31A shows the relationship between frequency and gain when there is no phase compensation circuit. In the figure, a is the gain v _i ′ / v _i of the differential amplifier 21, and b is the gain v _o / v of the output stage 22.
v _i ′, c is the total gain v _o / v _i . a and b start decreasing at a frequency of 6 dB / oct at the frequencies f ₁ and f ₂ , respectively. Here, f ₁ = 1 / (2πC _G r ₁ ) and f ₂ = 1 / (2πC _L r ₂ ). Since f ₁ > f ₂ in this example, the total gain c
= V _o / V _i is 6 dB / oct when the frequency exceeds f _2.
Then, when f ₁ is further exceeded, it decreases at a rate of 12 dB / oct. These points f ₂ and f ₁ are so-called pole frequencies. As described above, in order for the feedback amplifier to operate stably, the point where the feedback amplifier starts to decrease at 12 dB / oct (here, f
The gain in ₁ ) must be 0 dB or less. As is clear from the figure, this condition is often not satisfied when f ₁ and f ₂ are relatively close to each other. FIG. 31 (a)
Is not satisfied with. Therefore, by separating f ₁ and f ₂ sufficiently, the feedback amplifier can be stabilized.

Here, when the phase compensation circuit C _i is added, the frequency characteristic becomes as shown in FIG. 31 (b). That is, the gain of the differential amplifier 21 does not change, but the gain of the output stage has a characteristic of being bent at three points P ₂₁ , Z ₂ , and P ₂₂ .
P ₂₁ and P ₂₂ are poles, and Z ₂ is a point called a zero point.
The frequencies at these points are:

F ₂₁ = 1 / (2π (C _D r ₂ + C _L r ₂ C _D R _D )) f ₂₂ = (C _D r ₂ + C _L r ₂ C _D R _D ) / (2π C _L C _D r _{2) RD} ) f ₂ = 1 / (2πC _{D RD} ) As is clear from this figure, by setting f ₂ near the pole frequency f ₁ of the differential amplifier, that is, C _D
By setting R _D ≈C _G r ₁ , there is no bending at f ₁ of the total gain. As a result, the total gain is
When the frequency exceeds f ₂₁ , it is 6 dB / oct, and further f ₂₂
If it exceeds, it will decrease at a rate of 12 dB / oct. Here, if C _D = nC _G r ₁ / r ₂ and R _D = r ₂ / n and n is made sufficiently large, f ₂₁ and f ₂₂ can be sufficiently separated, so that the feedback amplifier should be stabilized. You can

FIG. 32A shows another embodiment of the feedback amplifier and the phase compensation circuit. In this circuit, phase compensation is performed by inserting a capacitor C _F between the input and output of the output stage 22. FIG. 32B shows a small signal equivalent circuit when the feedback of this circuit is not applied, and FIG. 33 shows its frequency characteristic. In this case, the gain of the differential amplifier has a characteristic that it is bent at three points P ₁₁ , Z ₁ , and P ₁₂ . Also in this case, similarly to the previous embodiment, the feedback amplifier can be stabilized by setting f ₁ ≈f ₂ and separating f ₁₁ and f ₁₂ sufficiently. The feature of the present embodiment is that the capacitor C _F for phase compensation is inserted between the input and the output of the amplification stage, so that the apparent capacitance increases due to the so-called Miller effect. Therefore, phase compensation can be performed even if the actual capacitance is relatively small, and the area occupied by the capacitor can be reduced.

Here, FIG. 30 (a) or FIG. 32 (a)
The capacitor used in the phase compensation circuit will be described.
These capacitors are required to have a considerably large capacitance (usually several hundred to several thousand pF) and a small voltage dependency. FIG. 34 (a) shows one method of realizing this by a normal CMOS process. In the figure, 101 is a P-type semiconductor substrate, 102 is an N-type well, 103 is an N ⁺ diffusion layer, 104 is SiO ₂ for isolation, and 105 is B.
R> gate insulating film, 106 is a gate. The capacitor is sandwiched between the gate insulating film 105 and the gate 106 and the substrate surface 102a, like a normal MOS capacitor.
Formed between and. Since a thin gate insulating film is used as the capacitor insulating film, a large capacitance can be obtained in a relatively small area. However, normal MO
The difference from the S capacitor is that the threshold voltage is negative because of the N well under the gate. This will be described with reference to FIG. The horizontal axis represents the voltage applied to the capacitor (the gate side is positive), and the vertical axis represents the capacitance. The threshold voltage (flat band voltage) is the applied voltage V ₀ when the capacitance changes greatly, and V ₀ <0. Therefore, as long as a voltage in one direction is applied so that the gate side becomes positive, the current collecting capacity is almost constant. When a bidirectional voltage can be applied, two capacitors shown in FIG. 34 (a) may be used and connected in parallel in opposite directions as shown in FIG. 34 (c).

The steps required to manufacture the capacitor of this embodiment are well formation, isolation region formation, gate insulation film formation, gate formation, diffusion layer formation, and wiring, but these are all processes. This is a step included in a normal CMOS process. Therefore, if the semiconductor device is manufactured by the CMOS process, it is not necessary to add any additional steps to manufacture the capacitor.

Depending on the semiconductor device to which the present invention is applied, the laminated capacitance may be available. For example, a DARM using a stacked capacitor as a capacitor of a memory cell
Is so. In such a case, the laminated capacitance may be used as the phase compensation capacitor. D using laminated capacity
Regarding RAM, IEE, Journal of Solid State Circuits, No. 15
Volume 4, Issue 661-666, pp. 1980
Moon (IEEE Journal of Solid-State Circuits,
Vol.SC-22, No. 3, pp. 661-666, Aug.
1980).

[Reference Voltage Generating Circuit] Next, a reference voltage generating circuit suitable for use in the voltage limiter circuit according to the present invention will be described. The reference voltage generation circuit described here can of course be used for a voltage limiter circuit that is not subjected to phase compensation. It goes without saying that the embodiments described in Group 1 can be applied.

The output voltage V _L of the electric limiter is made based on the reference voltage V _R. Therefore, the characteristics of V _R,
The characteristic of _VL can be set arbitrarily. When using a voltage limiter circuit in the semiconductor device, since the external power supply voltage V _CC dependence of V _L is particularly important, it is necessary to design special attention to the V _CC dependency of V _R. Regarding this, examples of characteristics and their generation methods according to various purposes are described in Japanese Patent Application No. 56-
57143, Japanese Patent Application No. 56-168698, Japanese Patent Application No. 57-
220083, Japanese Patent Application 60-261121, Japanese Patent Application 63
-8372, Japanese Patent Application No. 63-125742, US Pat. No. 4
No. 100437 and the like. It goes without saying that these circuits are applicable to the present invention.

In the embodiment shown in FIGS. 24 to 27, the reference voltage V
_R was directly input to the drive circuit. However, the voltage obtained by the reference voltage generation circuit is not always an appropriate value as the internal power supply voltage used in the semiconductor device. In this case, voltage conversion is required. In some cases, fine adjustment of the voltage, so-called trimming, may be required to compensate for variations in the reference voltage due to the manufacturing process. As the voltage conversion and trimming method, the method described in the above-mentioned U.S. Pat. No. 4,100,437 may be used, but here, a method suitable for a semiconductor device manufactured by a normal MOS process is introduced.

FIG. 35 shows a circuit diagram. In the figure, DA is a differential amplifier, Q _{31 to} Q ₄₃ are P-channel MOS transistors,
F ₁ ~F ₈ is a fuse. (Output of the reference voltage generating circuit) V _R is the input voltage is V _R 'is the output voltage (the input of the drive circuit). While the the DA input terminal, V _R is input, MOS transistors Q ₃₁ to V _R 'to the other ~Q
_The V _R ″ divided by ₄₂ is fed back. If the amplification factor of DA is sufficiently large, the output voltage V _R ′ is given by the following equation.

V _R ′ = ((R ₁ + R ₂ ) / R ₂ ) · V _R Here, R ₁ is the resistance value when the circuit consisting of Q _{31 to} Q ₃₈ is equivalently regarded as a resistance, R ₂ Is a resistance value when the circuit composed of Q _{39 to} Q ₄₂ is equivalently regarded as a resistance. Since R ₁ and R ₂ are changed by cutting the fuse,
It is possible to adjust the V _R '.

A specific trimming method will be described with reference to FIG. This figure shows the relationship between the input V _R and output V _R '. In the figure, d is the characteristic when the fuse is not cut at all. When the fuses F ₁ , F ₂ and F ₃ are blown in order, the above R ₁ becomes large, so that V _R ′ becomes high as indicated by c, b and a. When the fuses F ₄ , F ₅ , and F ₆ are cut in order, the above R ₂ becomes large, so that e, f, and g
As shown by, V _R ′ becomes low. Therefore, first observe the V _R, as V _R from FIG 13 'is most target value V _R0' close to, it may be selected method of cutting a fuse. Our goal is, also vary in the V _R is a wide range, V _R '
To be within a certain range V _R0 ′ ± ΔV _R ′. For this purpose, as shown by a broken line in FIG, V _R 'to the case of employing some trimming method (e.g., a)
= V _R0 ′ + ΔV _R ′, if a trimming method adjacent to it (for example, b) is adopted, then V _R ′ = V _R0 ′
The circuit constant (channel width / channel length of each MOS transistor) may be selected so as to be −ΔV _R ′.

FIG. 37 shows another embodiment of the trimming circuit. When lowering the output voltage V _R ′, the fuses F ₄ , F ₅ , and F ₆ may be cut in order, as in FIG. The difference from FIG. 35 lies in the method of increasing the output voltage V _R ′. In this case, the fuse F ₇ is first blown (at this time, the circuit constants are selected so that the input / output characteristics are as shown in h of FIG. 36), and then F ₄ , F ₅ , F ₆ are blown in order. You can do it. This circuit has the advantage that the number of fuses is smaller than that of the circuit of FIG. 35 and therefore the occupied area can be reduced.

The circuit shown in FIGS. 35 and 37 has a conventional MOS structure as compared with the circuit described in the above-mentioned US patent.
There is an advantage that the occupied area is small when it is made by the process. That is, in the circuit described in the US patent,
While a resistor was used as an element for dividing the output voltage V _R ′, in the circuits of FIGS. 35 and 37, MO is used.
An S transistor is used. In order to reduce the current consumption of the circuit, the equivalent resistance of the voltage dividing element must be quite large (about several hundred kπ). In a normal MOS process, a MOS transistor has a smaller area and a larger equivalent resistance than a resistor. However, MO
When S transistors are used, there is a concern that the characteristics of V _R ′ may fluctuate due to fluctuations in the threshold voltage. However, the channel width and channel length of each transistor are made sufficiently large to suppress fluctuations, and the back gate is the source. It is possible to solve the problem by connecting to the device to avoid the influence of the substrate potential fluctuation and selecting the fuse cutting method in consideration of the variation in the threshold voltage.

Next, a MOS transistor used in the trimming circuit will be described with reference to FIGS. 38 (a) and 38 (b). As described above, it is desirable to connect the back gate of each transistor to its source in order to suppress the influence of substrate potential fluctuations. For example, when the substrate is a P type, a P channel MOS as shown in FIG.
A transistor may be used. When the substrate is N-type, an N-channel MOS transistor in which all conductivity types are reversed in FIG. 38A may be used. Also, FIG.
By forming a double well structure and fixing the potential of the outer well 112 (here, it is grounded) as in (b), it is possible to further strengthen against the substrate potential fluctuation.

Next, the fuse used in the trimming circuit will be described. As the fuse, for example, the same one used for defect repair of a semiconductor memory such as polycrystalline silicon can be used. Therefore, in the case of a semiconductor memory having a defect relief circuit, it is not necessary to add any additional steps to make a fuse. The method of cutting the fuse may be a method using laser light or an electrical method. The method using laser light has an advantage that an occupied area can be reduced because a cutting transistor is unnecessary, and the electrical method has an advantage that an expensive laser light irradiation device is not required. is there.

FIG. 39A shows another embodiment of the V _R to V _R ′ conversion circuit. The difference from the circuit of FIG. 35 or FIG. 37 is that a P-channel MOS transistor Q ₄₈ is added. As a result, the maximum value of the output voltage V _R ′ is suppressed to V _CC − | V _TP | (V _TP is the threshold voltage of the P-channel MOS transistor). This will be described with reference to FIG. This figure shows the V _CC dependency of V _R and V _R ′. In the circuit of FIG. 35 or FIG. 37, V _R ′ ≈V _CC when V _CC is low. However, in the circuit of FIG. 39 (a), the addition of Q ₄₈ causes V _R ′ = V when V _CC is low.
_CC- | _VTP | and | _VTP |

The advantage of this embodiment is that when V _CC is significantly lower than the normal operating state (eg 5V) (eg 3V).
V), the voltage stability of the internal power supply voltage V _L is good. This will be described with reference to FIG. This figure is
In the drive circuit of FIG. 30 (a) or FIG. 32 (a), it is an example of the relationship between the power voltage V _L and the current I _L when V _CC is low. 35 or FIG to generate V _R '37
When the circuit of is used, V _L ≈V _R ′ ≈when V _CC is low
Since it is V _CC , the drain-source voltage of the output MOS transistor (Q _{26 in} FIG. 30A or FIG. 32A) of the drive circuit is almost 0, and the current drive capability is small. Therefore, when the output current (load consumption current) I _L increases, V _L decreases. On the other hand, when the circuit of FIG. 39 (a) is used to generate V _R ′, V _L ≈V _R ′ ≈V _CC − | V _TP | The drain-source voltage is approximately equal to | V _TP | (0.5 V in this example). Therefore, its current driving capability is relatively large, and the amount of decrease in V _L is small. That is, by setting V _L to be slightly lower in advance, the operation of the circuit in the semiconductor device that operates the amount of voltage fluctuation becomes more stable when V _CC is low, and
_The operation margin for _CC becomes large.

Note that the circuit Q ₄₈ of FIG. 39A also has the structure shown in FIGS. 38A and 38B in order to suppress the influence of the substrate potential fluctuation, like the MOS transistor of the trimming circuit described above. It is desirable to put it.

[In-Chip Arrangement / Wiring] Next, a circuit arrangement method for mounting the present invention in an actual semiconductor chip,
In addition, a wiring method of the reference voltage V _R and the internal power supply voltage VL will be described. A DRAM is taken as an example of a semiconductor device to which the present invention is applied, but the present invention can be applied to other semiconductor devices, as a matter of course. The arrangement / wiring method described here is also effective for a voltage limiter circuit that is not subjected to phase compensation.

FIG. 40 shows an example of a desirable circuit arrangement and wiring when the voltage limiter circuit is applied to a DRAM. In the figure, 1 is a semiconductor chip, 2a and 2b are fine MOSs.
Memory array composed of transistors, 3a, 3
Reference numerals b and 3c are peripheral circuits. 4 and 5 are ground V respectively
_GND , a bonding pad for the external power supply voltage V _CC , 6 is a reference voltage generation circuit, and 7a, 7b, 7c and 7d are drive circuits. 6 and 7a to 7d form a voltage limiter circuit. 7a, 7b and 7c are peripheral circuits 3 respectively.
Internal power supply voltages _VL1 , _VL2 , V for driving a, 3b, 3c
Generates _L3 . 7d generates an internal power supply voltage V _L4 for driving the memory arrays 2a and 2b.

The feature of this embodiment is that the reference voltage generating circuit 6 and the driving circuits 7a to 7d are separated, the reference voltage generating circuit is near the ground potential input bonding pad, and the driving circuit is near each load circuit. It has been placed in. Therefore, the ground wiring 8 from the ground potential input bonding pad to the reference voltage generating circuit and the internal power supply voltage wirings 11a to 11d from each drive circuit to each load circuit are shortened and their impedances are reduced. Thus, the noise on the wire 8 is reduced, the ground level of the reference voltage generating circuit is stabilized, stable reference voltage V _R is obtained. Further, since the voltage drop of the internal power supply voltage V _L1 ~V _L4 due to the impedance of the wiring 11a~11d decreases, V
Level _L1 ~V _L4 is stabilized, the operation of the load circuit is stabilized.

Another feature of the present embodiment is the method of ground wiring. First, a dedicated short wiring 8 is provided for the reference voltage generating circuit. For other circuits, wiring 9a
~ 9d is provided. That is, each drive circuit and its load circuit are wired on a common line, but separated from other drive circuits and load circuits. The advantage of this wiring system is that the noise generated on the ground wiring due to the current flowing when each circuit operates can be prevented from adversely affecting other circuits. In particular, the reference voltage noise to the ground wiring of the generator occurs, all the level of the internal power supply voltage V _L1 ~V _L4 varies, only a ground wire for the reference voltage generating circuit is necessarily other ground wiring is separated It is desirable to keep it. It is also desirable to separate the ground wiring for the memory array from other ground wiring. This is because in the DRAM, when the sense amplifier performs an amplifying operation, a large number of data lines (whose capacitance is usually several thousand pF) are charged and discharged at the same time, and a large noise is generated in the ground wiring.

FIG. 41 shows another embodiment of circuit arrangement and wiring. In this embodiment, the peripheral circuits 3 are arranged centrally in the center of the chip, and the bonding pads 4 and 5 for grounding and the external power supply voltage V _CC are also arranged in the center of the chip. Also in this embodiment, the reference voltage generating circuit 6 is provided in the vicinity of the bonding pad for inputting the ground potential, and the driving circuits 7a, 7a
d is arranged near each load circuit.

The advantage of this embodiment is that the wiring length is shortened, as is apparent from FIG. As a result, it is resistant to fluctuations in the external power supply voltage V _CC and fluctuations in the current flowing through the load circuit. That is, in the previous embodiment, since the wiring 10 between the V _CC bonding pad and each drive circuit is long, its impedance is large and the level of V _CC decreases due to the consumption current of the load circuit. Of course, this decrease is absorbed by each drive circuit, but if the decrease is too large, it will not be absorbed and the internal power supply voltage V
_This may cause a decrease in the level of _L. On the other hand, in this embodiment, since the impedance of the V _CC wiring 10 is small, a large load current can be flown accordingly. Also V
Strong against _CC decline.

In FIG. 40 or FIG. 41, the noise of the ground wiring is a particular problem because the reference voltage V _R and the internal power supply voltage V _Li are generated with reference to the ground potential. Conversely, if V _R, V _Li is generating an external power supply voltage V _CC as a reference, towards the noise of V _{C C} wiring becomes a problem. In this case, the reference voltage generating circuit may be arranged near the V _CC bonding pad and the V _CC wiring may be separated for each circuit.

In the arrangement / wiring method shown in FIG. 40 or FIG. 41, the reference voltage V _R is wired from the reference voltage generating circuit to each drive circuit, but the wiring 12 is shielded. Is desirable. This is to prevent V _R from fluctuating due to noise from other circuits in the semiconductor chip. An example of a shielding method that can be realized by a normal semiconductor manufacturing process will be described below.

42 (a) and 42 (b) are a plan view and a sectional view, respectively, of one embodiment of the shielded wiring. In the figure, 101 is a semiconductor substrate, 104 is SiO ₂ , 1
Reference numeral 08 is a first wiring layer, 109a, 109b and 109c are second wiring layers, 113 and 114 are interlayer insulating films, and 115 is a protective film. Reference numeral 109b is a wiring for the reference voltage V _R.
Wirings for shielding 108, 109, and 109c around it are fixed to a constant potential (here, ground). Substrate 1 is provided by providing 108 below 109b.
Noise due to capacitive coupling with 01 can be prevented and 109
By providing a and 109c, noise due to capacitive coupling with an adjacent wiring (not shown) can be prevented. FIG. 42
(C) and (d) are other examples of the shielded wiring. In this embodiment, the V _R first wiring layer 108
Wiring is performed at b, and shield wirings are provided on the left and right (108a, 108c), lower (106) and upper (109) of the wiring. By providing the shield wiring also above, noise due to capacitive coupling through the space above can also be prevented, and the shield becomes more effective.

Further, as shown in FIGS. 61A and 61B, the contact holes 116a and 116c and the through hole 1 are formed.
If the shield wirings are connected by providing 17a and 117c, the shield becomes complete. 61 (c) and 61 (d) show another embodiment of the shielded wiring. In this embodiment, the polycrystalline silicon layer 106 is the wiring of V _R. A well 112 is formed below the well 112, and the P-type diffusion layer 107 is formed.
a, 107c and contact holes 116a, 116c
Is connected to the first wiring layer 108 above. That is, the circumference of 106 is 112, 107a, 11
It is shielded by being surrounded by 6a, 108, 116c and 107c. The advantage of this embodiment is that the second wiring layer is not used for the shield.
09, it can be used for other purposes.
This is, for example, the wiring and the other wiring V _R is effective for use in the intersection.

By the shield as described above, V _R
There is a parasitic capacitance between the and ground, which rather has the positive effect. This parasitic capacitance acts as a so-called decoupling capacitor that reduces the impedance of the V _R wiring with respect to high frequencies and bypasses high frequency noise. If the capacitance of the decoupling capacitor is insufficient only with the shield line, it is of course possible to load it with another capacitor.

In the above example, the potential for fixing the shield wire is the ground potential, but it is not necessarily the ground potential as long as it is a stable potential. However, it is preferable to set it to the ground potential because it is the simplest and the parasitic capacitance acts as a decoupling capacitor as described above. In particular,
Connecting to the ground wiring for the reference voltage generating circuit (portion 8 shown in FIGS. 40 and 41) may be for the purpose of avoiding noise generated by the operation of other circuits. As mentioned above, VR _is V
If generated with respect to _CC , the shield line should be fixed to V _CC .

FIG. 43 shows another embodiment of the circuit layout and wiring. In the figure, 1 is a semiconductor memory chip, 3 is a peripheral circuit, 7a, 7b and 7c are drive circuits that generate internal power supply voltage V _L , and 14a, 14b, 14c and 14d are voltages that use the outputs of the drive circuits as power supplies. A pulse generation circuit that generates pulses φ _P1 , φ _P2 , φ _P3 , and φ _P4 of amplitude V _L , 2
a, 2b, 2c and 2d are φ _P1 , φ _P2 , φ _P3 and φ, respectively.
It is a memory array using a fine MOS transistor operated by _P4 . The reference voltage generating circuit is omitted here. FIG. 44 shows the operation timing of these circuits.

A single external power supply voltage V _CC (for example, 5 V) is applied to the semiconductor memory chip 1 of this embodiment. Drive circuits 7a, 7b, 7c output internal power supply voltage VL (for example, 3V) lowered from V _CC , and are input to pulse generation circuits 14a, 14b, 14c, 14d, respectively. Then, the timing pulse phi _T shown in FIG. 44 to the pulse generation circuit, an address signal a _i and reverse phase / a _i is inputted.

Peripheral circuit 3 receives external address signal A _i and outputs internal address signals a _i and / a _i to external control signals (here, row address strobe signal / RAS, column address strobe / CAS, and write enable signal). / WE) to generate an internal timing pulse φ _T. The peripheral circuit does not have a great influence on the degree of integration of the chip, so that it is not necessary to use fine elements, and due to the convenience of the jumping interface, the external power supply voltage V _CC
Although it is operated directly in, the operation may be performed with the internal power supply voltage.

In the memory, only the array selected by the address operates. In this example, a _i = “0” (/ a _i =
When “1”), the arrays 2a and 2c are selected (2b and 2d are not selected), and when a _i = “1” (/ a _i = “0”), the arrays 2b and 2d are selected (2a and 2c are not selected). It becomes the state of (selection). Therefore, only the pulses for the selected array are output. That is, as shown in FIG. 44, a _i =
When it is "0", the pulse generation circuits 14a and 14c output φ _P1 and φ _P3 in response to the timing pulse φ _T to output the array 2
a and 2c, when the a _i = "1" Conversely, the pulse generating circuit 14b and 14d is the timing pulse phi _T phi _P2,
Output φ _P4 to operate the arrays 2b and 2d.

The feature of this embodiment is that each drive circuit is arranged close to each pulse generation circuit, and the pulse generation circuit 14 is used.
That is, the drive circuit 7b is shared by b and 14c. Therefore, the wiring becomes shorter and the impedance of the wiring becomes smaller than that in FIG. 3, and the level of noise generated thereby can be suppressed. Also, compared to FIG.
The number of drive circuits is reduced by one, which can reduce the chip occupation area and power consumption. Moreover, since the pulse generation circuits 14b and 14c do not operate at the same time, the drive circuit 7b needs to drive only one pulse generation circuit.
It is not necessary to double the current drive capacity.

The pulse generation circuits 14a-14d can be realized by the circuits shown in FIGS. 45 (a) and 45 (b), for example. In FIG. 45A, reference numeral 51 is a two-input NAND circuit composed of P-channel MOS transistors Q ₅₁ and Q ₅₂ and N-channel MOS transistors Q ₅₃ and Q ₅₄ . The power supply for this circuit is V _CC and the inputs are the timing pulse and the address signal a _i (or / a _i ). 52 is an inverter composed of a P-channel MOS transistor Q ₅₅ and an N-channel MOS transistor Q ₅₆ , and its power supply is V _L. If a _i is "1" phi _T when the (potential V _CC) is input, the amplitude of the pulse phi _P of the internal power supply V _L is input. Although the NAND circuit is operated by the external power supply voltage V _{C C} here, it may be operated by the internal power supply voltage V _L.

FIG. 46 shows an example in which the number of drive circuits is further reduced by one as compared with the embodiment of FIG. Address signals a _i , / a _i , timing pulse φ _T , and pulse φ _P1
˜φ _{P 4} is the same as that described in FIG. 43.

In this embodiment, the pulse generating circuits 14a and 14a
The driving circuit 7a is shared with 4b, and 7b is shared with 14c and 14d. Therefore, as compared with the embodiment of FIG. 43, the number of drive circuits is reduced by one, and thereby the chip area and power consumption can be reduced. Here, as shown in FIG.
a and 14b and 14c and 14d do not operate simultaneously. Therefore, each of the drive circuits 7a and 7b needs to drive only one pulse generation circuit, and it is not necessary to double the drive capability.

FIG. 47 shows an embodiment to which the present invention is applied when the memory array is divided into eight. 1 in the figure
Is a semiconductor chip, 3 is a peripheral circuit, 2a to 2h are memory arrays, 7a and 7b are drive circuits, and 14a to 14h are pulse generation circuits. In this example, 2 out of 8 arrays
Are selected by the address signals a _i and a _j , and only the selected array operates. That is, a _i a _j = “00”
2a and 2e, a _i a _j = 2b and 2f when the "01", 2c and 2g is when a _i a _j = "10" when the, a _i a _j =
When it is "11", 2d and 2h are selected. Therefore, the pulse for the selected array φ _Pk (k = 1 to
Only 8) is output. That is, as shown in FIG. 48, when the address signal a _i a _j = “00”, the pulse φ _P
When φ _1P5 and a _i a _j = “01”, the pulses φ _P2 and φ _P6 ,
When a _i a _j = “10”, pulses φ _P3 and φ _P7 , a _i a _j =
When it is "11", the pulses φ _P4 and φ _P are output respectively. These pulses φ _Pk (k = 1 to 8) are pulses output at the timing of φ _T , and their amplitude is the internal power supply voltage V _L.

In this embodiment, two driving circuits 7a and 7a are provided with eight pulse generating circuits for operating the memory array.
share b. By doing so, the number of drive circuits can be significantly reduced, and the occupied area and power consumption can be reduced.

[Example of Application to DRAM] Finally, an example in which the present invention is applied to a DRAM will be described. FIG. 49 is a block diagram of a DRAM to which the present invention is applied. In the figure, 201 is a bonding pad for supplying a power supply voltage (V _CC ) which is connected to an external power supply. Reference numeral 202 is a differential amplifier, 203 is a supply line of an internally stepped down power supply voltage ( _VL ), 204 is a drive MOS transistor of a P-channel MOS sense amplifier, 2
Reference numeral 05 is a start-up MOS transistor of the N channel MOS sense amplifier, 206 is a P channel MOS sense amplifier, 2
Reference numeral 07 is an N-channel MOS sense amplifier, 208 is a memory cell, 209 is an N-type well portion of a P-channel MOS sense amplifier, 210 is a memory block including a cell array portion and a sense amplifier portion, 211 is an X decoder, 212 is a Y decoder, 213 Is a short precharge signal line, 214
Is a power supply line V _L / 2. The power supply voltage V _CC is used in peripheral circuits such as an X decoder, a Y decoder, gate protection and a signal generation circuit. In the case of the present embodiment, the internally reduced power supply voltage V _L is the sense amplifier driving MOS transistor 2
It is used as a back gate (well) of the P-channel MOS transistor connected to 04 and a part of the Y decoder.

In the case of a so-called CMOS circuit such as a sense amplifier, when a P type substrate is used, a P channel MOS transistor is usually formed in an N type well. In this case, as shown in the sectional view of FIG. 50, the potential of the N well (back gate of the P-channel MOS transistor) is not the external power supply voltage V _CC but the operating voltage ( _{VL in} this case) supplied to its source. Is desirable. The reason for this will be described below.

For example, V_CC= 5V, V_L1= 3V
And whether the data line precharge level is 1.5V
P-channel MOS transistor before the sense amplifier is activated.
Back gate bias of 1.5V is applied to
After that, it becomes 0V. Referring to FIG. 6, sense amplifier activation
The previous threshold voltage (absolute value) is about 0.86V,
It is about 0.57V. If N well voltage is V_CC(= 5
V), it becomes 1.1V and 0.92V respectively. This
This is V_L1Too big compared to the case. FIG. 51
Is the operating speed of the sensing system of the above DRAM, P channel
Plot against threshold voltage of MOS transistor
It is a figure. As can be seen from the figure, the threshold of 0.1V
In this case, the value voltage rise corresponds to a delay of about 2 ns.
N well voltage is V _L1By setting (= 3V), about 5ns or less
It can be seen that the above speedup can be realized. Age of ultra-high integration
CMOS LSI has a lower operating voltage,
Increase the concentration (greater back gate bias effect)
Therefore, the effect of the present invention is more important.
become.

Here, the N well voltage is set to the P channel MOS.
In making the voltage equal to the internal power supply voltage V _L supplied to the transistor, there is concern that the N well voltage may change due to capacitive coupling or the like. In the embodiment shown in FIG. 49, the data line is V _L.
Since it is precharged to / 2, when the P-channel MOS transistor operates, it is paired with the drain voltage rising and falling, and the noise is extremely small.
Therefore, problems such as latch-up due to fluctuations in the N-well voltage do not occur.

The sense amplifier has been described above as an example, but the same method can be applied to other CMOS circuits. Further, not limited to the DRAM, any CMOS / LSI having two or more different operating voltages can be applied.
Further, in the embodiment of the present invention, it is clear that the present invention can be realized even if all of the conductivity type and potential relationship of the semiconductor are reversed.

As described above, according to the present invention, it is necessary for the voltage limiter circuit to drive many types of loads, and even when the type and size of the load vary depending on the operation mode, the type of load is changed. Optimum phase compensation according to the operation mode can be performed, and the operation of the voltage limiter can be stabilized.

When there are a plurality of load circuits using the internal voltage as a power source in the semiconductor chip, the wiring from each drive circuit to each load circuit can be shortened, so that the noise level can be suppressed to a low level. Moreover, since the number of circuits can be reduced without increasing the drive capability of the drive circuit, the occupied area and power consumption can be reduced.

Also, C using the internally lowered operating voltage is used.
In the MOS circuit, by making the voltage of the back gate (well) of the transistor formed in the well equal to the stepped-down voltage, the circuit can be speeded up, and the reliability of the ultra-high integration LSI can be improved. High speed can also be realized.

[Third Group] A problem with the above technique is that no consideration is given to a method of externally testing the internal voltage. For example, a memory L having a voltage limiter
In the case of SI, if the internal voltage value generated by the voltage limiter deviates from the design value, the operation margin of the internal circuit becomes narrow or malfunction occurs. However, when the memory LSI is inspected by a memory tester or the like, the above problems cannot be easily confirmed unless the internal voltage value can be known.

If a pad is provided at the internal voltage terminal and the memory tester is connected to the pad, the internal voltage value can be known from the outside. However, this method has the following problems.

First, the noise received by the wiring from the pad to the memory tester causes an error in the measured value.

Second, the voltage value may change depending on the input impedance of the memory tester.

Third, since the memory tester measures an analog voltage, it takes a longer time to measure than a digital signal.

An object of this embodiment is to solve the above problems and to provide a semiconductor device in which the internal voltage can be easily inspected from the outside by a memory tester or the like.

In order to achieve the above object, in this embodiment,
Means for comparing the voltage specified from the outside with the internal voltage and means for outputting the comparison result are provided.

By comparing the voltage designated from the outside with the internal voltage and outputting the comparison result, the signal taken out to the outside becomes a digital signal. Therefore, as compared with the case where the voltage is directly taken out from the internal voltage terminal described above, it is less affected by noise and the input impedance of the measuring instrument, and the inspection with a memory tester or the like becomes easier.

This embodiment will be described below with reference to the drawings. Although the following description shows an example in which the present invention is applied to a DRAM, the present invention is not limited to DRAM and can be applied to other semiconductor devices.

FIG. 52 shows this embodiment. This is a DARM with a voltage limiter. In the figure, 1 is a semiconductor chip, 2 is a DRAM memory array, 3 is a DARM peripheral circuit, 4 is a voltage limiter, 5 is a comparison circuit, 6 is a multiplexer and an output buffer, and 8 is a test enable signal generation circuit. The voltage limiter 4 generates an internal power supply V _L lower than V _CC based on the external power supply V _CC . DRA
The peripheral circuit 3 of M operates by the external power supply V _CC , while the memory array 2 operates by the voltage of the internal power supply V _L.

A method of inspecting the voltage of the internal power supply V _L in this embodiment will be described.

The comparison circuit 5 compares V _L with the comparison voltage V _S. In this embodiment, the terminal for inputting the V _S is, DRA
Although it is also used as the M data terminal D _in , it may be used as a dedicated terminal or as another terminal, for example, one of the address terminals. The output C of the comparison circuit is output via the multiplexer and the output buffer 6. In this embodiment, C
The terminal for outputting is also used as the data output terminal D _out of the DRAM, but it may be a dedicated terminal.

The comparison output C becomes high level when V _L > V _S , and becomes low level when V _L <V _S. Therefore, D
_The internal voltage V _L can be known by changing the comparison voltage V _S applied to _in and observing D _out .

[0187] For example, the external power supply V _CC is, in the range of _{V CCmin ≦ V CC ≦ V CCmax} ... (1), and V _L must be less than the higher V _Lmax than V _Lmin. To check this, first D
_Apply V _Lmin to _in to _vary V _CC from V _CCmin to V _CCmax and verify that D _out is always high.
Next, V _{CCm ax} is applied to D _in to _change V _CC from V _CCmin to V
Until _CCmax varied, it may be confirmed that D _out is always low level.

It is a feature of the present invention that the signal output from the D _out terminal is a digital signal of high level or low level. Therefore, as compared with the case where the analog voltage is directly output, noise and an error due to the input impedance of the memory tester can be avoided, and inspection by the memory tester becomes easier.

The test enable signal TE is a signal indicating whether the mode is for checking V _L or the normal read / write mode. This signal is used to enable the comparison circuit 5 and to switch the multiplexer and the output buffer 6. Although a dedicated terminal for inputting TE may be provided, in this embodiment, TE is used.
There is provided a circuit 8 for generating This circuit is
TE is generated by the combination of the timings at which the row address strobe signal (/ RAS) of the RAM, the column address strobe signal (/ CAS), and the write enable signal (/ WE) are applied.

This will be described with reference to FIGS. 53 (a) and 53 (b).

In the DRAM, in the normal read / write mode, / RAS is / CA as shown in FIG. 53 (a).
It is applied before S. Conversely, as shown in FIG. 53 (b),
/ CAS is applied before the / RAS, moreover at that time / W _E was low, circuit 8 is determined to be a specified V _L inspection mode, generates a TE. In addition,
For the method of designating a special operation mode by the combination of the timings of / RAS, / CAS and / WE, see, for example, ISSC, Digest of Technical Papers, pages 18 to 19. page,
February 1987 (ISSCC Digest of Technical
Papers, pp. 18-19, Feb. 1987) or
I S S C C, Digest of
Technical Papers, pages 286-287,
February 1987 (ISSCC Digest of Technical
Papers, pp. 286-287, Feb. 1987).

Here, a supplemental description will be made regarding the input / output method of the dedicated signals (V _S , C, and TE) used for the inspection of V _L.

As described above, dedicated terminals for these signals may be provided. However, in the embodiment of FIG. 1, the V _S input terminal is D _in and the C output terminal is D _out.
TE and / RAS, / CAS, /
Made by a combination of WE timings. The advantage of this method is that _VL can be inspected using only the original terminals of the DRAM. Therefore, not only inspection in a wafer state but also inspection after assembling into a package becomes possible.

FIG. 54 shows an example of the comparison circuit 5.

In FIG. 54, 20 is a differential amplifier which receives V _L and V _S as inputs and outputs the node 27 as an output.
It is composed of channel MOS transistors 21, 22, 23 and P-channel MOS transistors 24, 25. Reference numeral 30 denotes an inverter that inputs the node 27 and outputs C,
N-channel MOS transistor 31 and P-channel MOS
It consists of a transistor 32. When V _L is higher than V _S, node 27 goes low and output C goes high. _VL
Is lower than V _S, node 27 is high and output C
Becomes a low level.

A single differential amplifier may be used as the comparison circuit, but if the output of the differential amplifier is further amplified by an inverter as in this embodiment, the level of the output C is surely high (≈). V _CC ) and low level (≈0 V), which is desirable.

Since TE is input to the gate of the MOS transistor 21 in this circuit, no current flows in the differential amplifier except in the V _L inspection mode (when TE is at a high level). This can prevent an increase in power consumption during normal operation. Further, since the P-channel MOS transistor 26 is conducting during the normal operation, the node 27 is fixed at the high level.

Next, a method of implementing the multiplexer and output buffer 6 used in the present invention will be described.

FIG. 55 shows an example of the multiplexer and the output buffer. In FIG. 55, 41, 42, and 49-
52 is an inverter, 43 to 48 are NAMD gates, 53
And 54 are N-channel MOS transistors. This circuit is a circuit that selects one of the data output d _out of the DRAM and the output C of the comparison circuit and outputs it to the output terminal D _out . Which is selected is determined by TE (the above-described test enable signal) and OE (the output enable signal of the DRAM). TE is high level, O
When E is at a low level (in the _VL inspection mode), C is
When TE low level and OE are high level (in the read mode), d _out is selected and output, respectively. T
When both E and OE are at a low level (in the write mode or the standby state), the output terminal D _out has a high impedance.

FIG. 56 shows another embodiment of the present invention. The difference from the previous embodiment is that two comparison voltages, V _S1 and V _S2 , are input and two comparison circuits 5-1 and 5-2 are provided.

The comparison circuit 5-1 compares the internal voltages V _L and V _S1, and the comparison circuit 5-2 compares V _L and V _S2 . The comparison output C ₁ becomes high level when V _L > V _S1 and low level when V _L > V _S2 . The comparison output C ₂ has a low level when V _L > V _S2 and has a high level when V _L <V _S2 . The signal C output to the outside is the result of logical product of C ₁ and C ₂ by the AND gate 9.

In this embodiment, the data input terminal and the output terminal are shared, and 4 bits are read / written simultaneously. This is a so-called x4 bit DRAM. Therefore, three of the four data input / output terminals I / O _{0 to} I / O ₃ are used for inputting the comparison voltages V _S1 and V _S2 and outputting the comparison result C. In the case of the x1 bit structure DRAM as in the previous embodiment, for example, the output of C is D _out , and V _out
For input of _S1 and V _S2 , D _in or 2 of address terminals
You can use individual pieces.

The advantage of this embodiment is that it is possible to know whether or not V _L is within a certain range by a single inspection. For example,
_{Suppose VL} must be higher than _VLmin and lower than _VLmax . To check this, V _S1 = V _Lmin , V _S2
= V _Lmax . C goes high only when V _{Lm in} <V _L <V _Lmax .

FIG. 57 shows another embodiment of the present invention.

The difference from the above-described two embodiments is that the comparison voltage V _S is specified by a digital signal and DA conversion is performed to generate the comparison voltage V _S by the DAC. In this embodiment, the input terminals for the digital signals S _{0 to} S ₃ are also used as the address terminals A _i .

The input digital signal is converted into the analog voltage V _S by the DA converter 10. The reference voltage applied to the DA converter may be V _CC , but the dedicated voltage V _R is preferable. This is because the V _CC dependency of the internal voltage V _L can be measured. Input terminal of the V _R In this example,
It also serves as the data input terminal D _{in of the} DRAM.

The feature of this embodiment is that it is an input digital signal as well as an output. Therefore, the test by the memory tester becomes easier than in the previous embodiment. In this embodiment, the comparison voltage is only one V _S ,
As a matter of course, the number may be two as in the previous embodiment.

Next, the DA converter used in this embodiment will be described.

FIG. 58 (a) shows an example of a DA converter. In the figure, 61 and 62 are inverters, R and 2R
Is resistance. Here, the power source of the inverter 62 is the reference voltage V _R. When the digital signal from the terminal S ₀ to S ₃ are input, the output voltage of the inverter 62 becomes V _R or 0V according to the input signal. Voltage output V _S is given by _{V 8 = (V R / 16} ) · (8S 3 + 4S 2 + 2S 1 + 1S 0) ... (2). However, it is assumed that the output impedance of the inverter 62 is sufficiently smaller than the resistors R and 2R.

FIG. 58 (b) shows another embodiment of the DA converter. In the figure, 71 is a decoder, 72 is a MOS transistor, and R is a resistor. This circuit selects one of the voltages V _i = (i / 16) · V _r (i = 0 to 15) (3) obtained by resistance-dividing the reference voltage V _R as the output V _S. This choice is
A signal T obtained by decoding the input signals S _{0 to} S ₃ by the decoder 71.
It is carried out by ₀ ~T _15. The characteristic of this circuit is that if the impedance of the load (the input impedance of the comparison circuit 5 of FIG. 57) is sufficiently large (the circuit of FIG. 54 satisfies this condition), the output voltage V _S is the MOS transistor 7
2 is not affected by the on-resistance.

58 (a) and (b) are both 4
It is a bit DA converter. However, it goes without saying that the number of bits may be increased or decreased depending on how accurately the internal voltage V _L needs to be set.

FIG. 59 shows still another embodiment of the present invention.
The feature of this embodiment is that the internal voltage V _L is AD-converted and output. Therefore, a register 80 for storing the digital signals S _{0 to} S ₃ is provided. The operation of this embodiment will be described below with reference to the timing chart of FIG.

The generation of the test enable signal TE by the combination of the timings of / RAS, / CAS and / WE is the same as in the previous embodiment. At this point, the content of the register 80 is set to the state in which only the most significant bit S ₃ is "1" and the others are "0". At this time, the comparison voltage V _S is V _R
Equal to / 2. As a result of comparing V _S with the internal voltage V _L , if C = 1, that is, V _L > V _R / 2, the most significant bit S ₃ is maintained at “1” as it is, C = 0, that is, V _L <V
_R / 2 if S ₃ is reset to "0".

Next, S _{2 of the} register is set to "1". At this time, the comparison voltage V _S is V _R / 4 or 3V _R /
It is 4. As a result of comparing the _VS with the internal voltage _VL , C
When = 1, S ₂ is kept at “1” as it is, and when C = 0, S ₂ is reset to “0”. And so on
S ₁ and S ₀ are sequentially determined.

The above operation is performed in synchronization with the clock. In this embodiment, / CAS is used as a clock. That is, first, / CAS is set to a low level before / RAS to specify the _VL inspection mode. This makes TE
Becomes a high level. Next, by raising / lowering / CAS while keeping / RAS at a low level, the above AD
The conversion is done. During this period, the comparison result of each time appears at the output terminal D _out in order, and the result of AD conversion can be known by observing D _out .

[0216]

According to the present invention, since the inspection result of the internal voltage is output to the outside as a digital signal, it becomes easy to inspect the internal voltage from the outside by a memory tester or the like.

As described above, according to the present invention, it is possible to actually provide an ultra-large-scale semiconductor integrated circuit, and
Stable operation and the like can also be achieved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an example of a first group of the present invention.

FIG. 2 is a diagram illustrating a problem discovered by the present inventors.

FIG. 3 is a diagram illustrating a problem discovered by the present inventors.

FIG. 4 is a diagram illustrating a problem discovered by the present inventors.

FIG. 5 is a diagram illustrating a problem discovered by the present inventors.

FIG. 6 is a diagram illustrating a problem discovered by the present inventors.

7A and 7B are circuit diagrams illustrating a conventional technique.

FIG. 8 is a diagram for explaining an example of the first group of the present invention.

FIG. 9 is a diagram for explaining an example of the first group of the present invention.

FIG. 10 is a diagram for explaining an example of the first group of the present invention.

FIG. 11 is a diagram illustrating an example of the first group of the present invention.

FIG. 12 is a diagram for explaining an example of the first group of the present invention.

FIG. 13 is a diagram for explaining an example of the first group of the present invention.

FIG. 14 is a diagram illustrating an embodiment of the first group of the present invention.

FIG. 15 is a diagram illustrating an example of the first group of the present invention.

FIG. 16 is a diagram for explaining an example of the first group of the present invention.

FIG. 17 is a diagram for explaining an example of the first group of the present invention.

FIG. 18 is a view for explaining an example of the first group of the present invention.

FIG. 19 is a diagram illustrating an embodiment of the first group of the present invention.

FIG. 20 is a diagram for explaining an example of the first group of the present invention.

FIG. 21 is a diagram for explaining an example of the first group of the present invention.

FIG. 22 is a diagram for explaining an example of the first group of the present invention.

FIG. 23 is a diagram for explaining an example of the first group of the present invention.

FIG. 24 is a diagram for explaining an example of the second group of the present invention.

FIG. 25 is a view for explaining an example of the second group of the present invention.

FIG. 26 is a diagram for explaining an example of the second group of the present invention.

FIG. 27 is a diagram for explaining an example of the second group of the present invention.

FIG. 28 is a view for explaining an example of the second group of the present invention.

FIG. 29 is a diagram for explaining an example of the second group of the present invention.

FIG. 30 is a diagram for explaining an example of the second group of the present invention.

FIG. 31 is a diagram for explaining an example of the second group of the present invention.

FIG. 32 is a view for explaining an example of the second group of the present invention.

FIG. 33 is a diagram for explaining an example of the second group of the present invention.

FIG. 34 is a view for explaining an example of the second group of the present invention.

FIG. 35 is a diagram for explaining an example of the second group of the present invention.

FIG. 36 is a diagram for explaining an example of the second group of the present invention.

FIG. 37 is a view for explaining an example of the second group of the present invention.

FIG. 38 is a view for explaining an example of the second group of the present invention.

FIG. 39 is a view for explaining an example of the second group of the present invention.

FIG. 40 is a view for explaining an example of the second group of the present invention.

FIG. 41 is a view for explaining an example of the second group of the present invention.

FIG. 42 is a diagram for explaining an example of the second group of the present invention.

FIG. 43 is a diagram for explaining an example of the second group of the present invention.

FIG. 44 is a diagram for explaining an example of the second group of the present invention.

FIG. 45 is a diagram for explaining a second group example of the present invention.

FIG. 46 is a view for explaining an example of the second group of the present invention.

FIG. 47 is a view for explaining an example of the second group of the present invention.

FIG. 48 is a view for explaining an example of the second group of the present invention.

FIG. 49 is a diagram for explaining an example of the second group of the present invention.

FIG. 50 is a view for explaining an example of the second group of the present invention.

FIG. 51 is a view for explaining an example of the second group of the present invention.

FIG. 52 is a view for explaining an example of the third group of the present invention.

FIG. 53 is a diagram for explaining an example of the third group of the present invention.

FIG. 54 is a diagram for explaining an example of the third group of the present invention.

FIG. 55 is a diagram for explaining an example of the third group of the present invention.

FIG. 56 is a view for explaining an example of the third group of the present invention.

FIG. 57 is a diagram for explaining an example of the third group of the present invention.

FIG. 58 is a view for explaining an example of the third group of the present invention.

FIG. 59 is a diagram for explaining an example of the third group of the present invention.

FIG. 60 is a diagram for explaining an example of the third group of the present invention.

FIG. 61 is a diagram for explaining an example of the second group of the present invention.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyoo Ito 1-280 Higashi-Kengokubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Yoshinobu Nakagome 1-280 Higashi-Kengokubo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory (72) Inventor Shinichi Ikenaga 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Central Research Institute Co., Ltd. (72) Inventor Jun Eto 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Central Research Co., Ltd. In-house (72) Norio Miyake 1450, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Musashi Plant, Hitachi Ltd. (72) Inventor Takaaki Noda 1450, Kamimizu-honcho, Kodaira-shi, Tokyo Inside Hitachi Ltd. Musashi Plant ( 72) Inventor Hitoshi Tanaka 5-22-1 Kamisuihonmachi, Kodaira-shi, Tokyo Co., Ltd. Within Hitachi Ultra LSI Systems (56) Reference JP-A-63-95653 (JP, A) JP-A-61-20291 (JP, A) JP-A-2-245810 (JP, A) Kaihei 2-224267 (JP, A) JP-A-2-172268 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/407

Claims (7)

(57) [Claims] 1. A first power supply terminal for receiving a first potential, a second power supply terminal for receiving a second potential higher than the first potential, and an internal potential for receiving the first and second potentials. An internal potential generating circuit for generating the internal potential; and first and second internal circuits using the internal potential and the first potential as operating power supplies. The internal potential generating circuit includes the first power supply terminal and the first wiring. A reference potential generating circuit that is connected via the first power supply terminal and generates a reference potential that is formed with reference to the first potential, and that receives the reference potential and the first potential. And a first drive circuit for supplying the internal potential to the first internal circuit, which is formed by receiving the reference potential and the first potential. Is supplied to the second internal circuit. A second driving circuit for connecting the reference potential generating circuit and the first driving circuit to each other, and a wiring for connecting the reference potential generating circuit and the first driving circuit is longer than the first wiring. The length of the wiring for connecting the drive circuit is longer than the wiring for connecting the first drive circuit and the first internal circuit, and for connecting the reference potential generation circuit and the second drive circuit. Is longer than the first wiring, and the length of the wiring for connecting the reference potential generating circuit and the second driving circuit is the same as that of the second driving circuit and the second internal circuit. It is longer than a wire for connection, the first wire and the second wire are separated from a wire takeout portion of the first power supply terminal, and the first wire and the third wire are connected to the first power supply terminal. A semiconductor characterized by being separated from the wiring take-out portion Location. 2. The differential amplifier according to claim 1, wherein each of the first and second drive circuits has a differential amplifier that receives the reference voltage at one input terminal and a gate based on a signal output from the differential amplifier. An output MOSFET controlled to output the internal voltage; and the output MOSFET
And a feedback means for inputting a signal based on the output of the differential amplifier to the other input terminal of the differential amplifier. 3. The memory cell according to claim 1, wherein the first internal circuit has memory cells respectively provided at intersections of a plurality of word lines and a plurality of data lines, and each of the plurality of data lines. And a plurality of sense amplifiers provided corresponding to the internal potential and the first sense amplifier.
A semiconductor device, which is supplied with an electric potential. 4. In any one of claims 2 3, wherein the first respective second power supply terminal, a semiconductor device which is a bonding pad. 5. In any one of claims 3 4, wherein the second internal circuit, and each provided are memory cells at intersections of a plurality of word lines and a plurality of data lines, the plurality of data lines respectively A semiconductor device comprising a plurality of sense amplifiers provided corresponding to. 6. In any one of claims 1 5, wherein the first potential, and wherein a is a ground potential. 7. The semiconductor device according to claim 1, wherein the semiconductor device is a dynamic memory.