JP2006310871A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stabilize an output voltage of an internal voltage generating circuit. <P>SOLUTION: The internal voltage generating circuit has a reference voltage generating circuit which generates a reference voltage, a drive circuit which outputs an internal voltage based on the reference voltage, and a phase compensating circuit which changes frequency characteristics of the drive circuit. The phase compensating circuit comprises a well region having a second conductivity type which is formed at a semiconductor substrate, a first region having the second conductivity type which is formed in the well region, and a capacitor which has a layer which is composed of a polycrystalline silicon or a metal formed above the well region through an insulating film. At this time, the capacitor is an MOS capacitor in which a threshold voltage is negative, and the capacitor is connected to the output of the internal voltage generating circuit. By the internal voltage generating circuit, current collection capacitance is stable without being dependent on the amount of the applied voltage, and its formation is consistent with a process of manufacturing an MOSFET and can be performed simply and easily. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a very large scale integrated circuit such as a dynamic memory having a storage capacity of 16 Mbits or more.

  In a semiconductor integrated circuit, a stable reference voltage with little fluctuation due to an external power supply voltage or temperature may be required. The LSI voltage limiter is described in, for example, ISSC Digest of Technical Papers, pages 272 to 273, February 1986 (ISSCC Digital of Papers, pp.272). -273, Feb. 1986). As described in the last paper, in a memory LSI such as a DRAM (Dynamic Random Access Memory), a voltage lower than the external power supply voltage is generated by a circuit (voltage limiter) provided on the LSI chip. Sometimes used as a power source. This internal power supply voltage needs to be a stable voltage with little fluctuation due to the external power supply voltage and temperature in order to stabilize the memory operation, and for this purpose, a stable reference voltage is required. An LSI incorporating an analog circuit often requires a stable reference voltage as a reference voltage.

As a reference voltage generating circuit that meets such requirements, there are circuits proposed in, for example, US Pat. Nos. 3,975,648 and 4,100,347. FIG. 7 shows a circuit diagram thereof. This is a circuit that obtains a stable voltage by utilizing a difference in threshold voltage between an H channel enhancement type MOSFET (hereinafter abbreviated as EMOS) and a depletion type MOSFET (hereinafter abbreviated as DMOS). In the figure, Q ₉₁ is an EMOS, Q ₉₀ , Q ₉₂ and Q ₉₃ are DMOSs, and V _CC and V _BB are positive and negative external power supplies, respectively. The difference in threshold voltage between EMOS and DMOS is the output voltage V _R. The operation of this circuit will be described below.

The current flowing through Q ₉₀ and Q ₉₁ is I ₉₀ , and the current flowing through Q ₉₂ and Q ₉₃ is I ₉₁ . If all four MOSFETs are operating in the saturation region, the following four equations hold.

_{I 90 = (β 90/2} ) · (-V TD) 2 ... (1)
I ₉₀ = (β _91/2 ) · (V ₉₉ −V _TE ) ² (2)
I ₉₁ = (β _92/2 ) · (V ₉₉ −V _R −V _TD ) ² (3)
I ₉₁ = (β _93/2 ) · (−V _TD ) ² (4)
Here, V ₉₉ is the voltage of the node 99, V _TE and V _TD are threshold voltages of EMOS and DMOS (V _TE > 0, V _TD <0), respectively, β ₉₀ , β ₉₁ , β ₉₂ , and β ₉₃ are respectively It is a conductance coefficient of Q ₉₀ , Q ₉₁ , Q ₉₂ , Q ₉₃ . From equations (1) to (4),
V _R = V _TE − (1+ (β ₉₀ / β ₉₁ ) − (β ₉₃ / β ₉₂ )) · V _TD (5)
Here, if β ₉₀ and β ₉₃ are sufficiently small, or if the constants of each MOSFET are determined so that β ₉₀ / β ₉₁ = β ₉₃ / β ₉₂ ,
V _R = V _TE −V _TD (6)
It becomes. That is, as the output voltage V _R , a difference voltage between the EMOS and the DMOS is obtained, which is a stable voltage that does not depend on the voltages of the external power sources V _CC and V _BB .

  In recent years, with the progress of high integration of semiconductor devices, a decrease in breakdown voltage due to miniaturization of semiconductor elements has become a problem. This problem can be solved by lowering the power supply voltage of the semiconductor device, but this is not always preferable because of the external interface. Therefore, the power supply voltage applied from outside is kept as it is (for example, 5 V in the case of TTL (transistor transistor logic) compatible), and an internal power supply having a lower voltage (for example, 3 V) is created in the semiconductor device. Proposed. For example, IEE, Journal of Solid State Circuits, Vol. 22, No. 3, pages 437 to 441, June 1987 (IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 3, pp. 437-441, June 1987), an example in which this method is applied to a DRAM (dynamic random access memory), and a circuit (voltage limiter) for generating an internal power supply from an external power supply. Circuit).

FIG. 7B shows a circuit diagram of the voltage limiter circuit described in the above document. In the figure, VL is a voltage limiter circuit, which comprises a reference voltage generation circuit VR and a drive circuit B. Z is a circuit that operates using a load of the voltage limiter, that is, the output voltage V _L of the voltage limiter as a power source. The reference voltage generation circuit V _R generates a stable voltage V _R with little fluctuation due to the external power supply voltage V _CC and temperature. The drive circuit B is a circuit that generates a voltage V _L having the same voltage value as V _R and a large driving capability, and includes a differential amplifier DA composed of Q _{106 to} Q ₁₁₁ and an output MOS transistor Q ₁₁₂ . Since V _R is connected to one of the two input terminals of the differential amplifier DA and the output V _L is fed back to the other, this circuit ensures that the output V _L follows the input V _R. Operate. Driving capability of the output V _L is determined by the channel width of the output MOS transistor Q _112. Therefore, if the channel width of Q ₁₁₂ is designed to match the current consumption of the load, a stable internal power supply voltage V _L can be supplied to the load.

ISS SC Digest of Technical Papers, 272-273, February 1986 (ISSCC Digest of Technical Papers, pp.272-273, Feb. 1986)

  Based on the above-described prior art, the present inventors have examined in detail a specific ultra-large scale integrated circuit (for example, an LSI of 16 Mbit or more in the case of DRAM), and found the problem described in detail below. did. This problem is broadly related to the reference voltage generation circuit, the voltage limiter circuit, and these tests.

First, the problem of the prior art shown in FIG. 7A is that it is difficult to match the characteristics of EMOS and DMOS because they use different devices. In the above description, the characteristics are the same for the sake of simplicity. Actually, however, the characteristics such as the temperature dependence dβ / dT of the conductance coefficients β and β and the temperature dependence dV _T / dT of the threshold voltage are considerably different. This is because the threshold voltage difference V _TE -V _TD between EMOS and DMOS must be considerably increased for the reasons described below.

The EMOS must be surely turned off when the gate-source voltage is 0V. For that purpose, the threshold voltage V _TE needs to be set considerably high (for example, V _TE ≧ 0.5 V) in consideration of manufacturing variations and subthreshold characteristics. In addition, since the DMOS may be used as a current source as shown by the equations (1) and (4), the absolute value of the threshold voltage V _TD is considerably large in order to suppress the variation in the current value. (For example, V _TD ≤-1.5 V) must be set. Therefore, V _TE −V _TD is quite large (eg, V _TE −V _TD ≧ 2V), which means that the impurity profile of the MOSFET channel region is significantly different. This causes a mismatch in characteristics as a MOSFET as described above. One object of the present invention is to solve the above problems and provide a reference voltage generation circuit that does not use a pleat type FET.

The first problem of the prior art shown in FIG. 7B is that the stability of the operation of the voltage limiter circuit is not considered. In general, an amplifier with feedback, such as the drive circuit B in FIG. 7B, becomes unstable unless it is designed to have a sufficient phase margin. This will be described with reference to FIGS. Assuming that the relationship between the frequency vs. gain and the frequency vs. phase of the amplifier when feedback is not applied is as shown in the figure, a numerical value indicating how much the phase delay has a margin of 180 ° at the frequency at which the gain becomes 0 dB. Is the phase margin. If the phase margin is negative, the feedback amplifier oscillates. If the phase margin is positive, the operation becomes unstable if the margin is small. In general, it is said that a phase margin of 45 ° or more is necessary for stable operation. For this purpose, the gain at the second point P ₂ (the point at which the slope changes from 6 dB / oct to 12 dB / oct) among the points (poles) at which the frequency vs. gain characteristic bends must be 0 dB or less. The voltage limiter circuit has a mission to supply a stable internal power supply voltage to the internal circuit, and of course must not oscillate or become unstable.

  As countermeasures against this problem, various methods for compensating the phase delay are, for example, written by Paul Earl Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition, John Willie and Sons (Paul R. Gray and Robert G. Meyer: Analysys and Design of Analog Integrated Circuits, 2nd Ed., John Wiley and sons Inc. Application to a voltage limiter circuit of a semiconductor device has the following problems: A circuit that is a load of the voltage limiter circuit is an internal circuit of an actual semiconductor device, and includes a capacitance, resistance, inductance, It includes a wide variety of elements such as non-linear elements or combinations of these elements, and their load is temporally For example, the current flowing through the load differs greatly between when the semiconductor device is in an operating state and when it is in a standby state, whereby FIG. As a result, the bias condition of the output stage of the drive circuit B in FIG.b) changes, and as a result, the frequency characteristics of the entire amplifier also change, and in order to operate the voltage limiter circuit stably, an amplifier having such complicated properties is required. It is necessary to ensure stable operation at all times, and only the conventional phase compensation method is insufficient.

The second problem of the prior art is that no consideration is given to the arrangement and wiring on the semiconductor chip. In particular, when there are a plurality of circuits that operate with the internal power supply voltage V _L , the arrangement of the voltage limiter circuit and the wiring of the output voltage V _L are not considered.

  The present inventors have found that the following problems arise when the above-described prior art is applied to a semiconductor memory. 3 and 4 show an example in which the above-described prior art is applied to a semiconductor memory. In FIG. 3, 1 is the entire semiconductor memory chip, 3 is a peripheral circuit, 7 is a drive circuit of the voltage limiter circuit (reference voltage generation circuit of the voltage limiter circuit is omitted here), 14a to Reference numeral 14d denotes a pulse generating circuit, and 2a to 2d are memory mats formed of fine MOS transistors.

Since the memory mat uses fine elements, the memory mat is operated with the internal power supply voltage _VL . The drive circuit 7 and the pulse generation circuits 14a to 14d are circuits for this purpose. 7 generates an internal power supply voltage V _L , and 14a to 14d generate pulses φ _{P1 to} φ _P4 of amplitude V _L , respectively. In this example, there are four pulse generation circuits 14a to 14d, while only one drive circuit is seven. Therefore, in order to supply the internal power supply voltage _VL generated by this voltage limiter circuit to each pulse generation circuit, a long wiring from the upper side to the lower side of the chip is required, and the parasitic impedance of the wiring increases, resulting in noise generation. Cause. If the wiring width is increased in order to reduce this impedance, there arises a problem that the occupied area of the wiring on the chip increases.

  FIG. 4 shows an example in which one drive circuit 7a, 7b, 7c, 7d is provided for each pulse generation circuit in order to avoid the problem that the wiring in FIG. 3 becomes long. In this way, the wiring length between the voltage limiter circuit and the pulse generation circuit can be shortened, but the same number (four in this case) of voltage limiter circuits as the number of pulse generation circuits are required. Therefore, the occupied area and current consumption on the chip of the voltage limiter circuit increase compared to the case of FIG. When the number of pulse generation circuits is further increased, the increase in the area occupied by the voltage limiter circuit and the power consumption becomes a serious problem for a semiconductor device aiming at high integration and low power consumption.

  The third problem of the prior art is that the operation speed of the CMOS circuit is not considered. This problem will be described using a dynamic random access memory (hereinafter abbreviated as DRAM) manufactured by making full use of the most advanced microfabrication technology.

  FIG. 5 shows a part of the circuit block configuration of an N-well CMOS DRAM. The memory cell array portion in the figure is on a P-type substrate. The sense amplifier section is composed of N-channel and P-channel MOS transistors, and an N-well corresponding to the substrate of the P-channel MOS transistor is connected to the power supply voltage.

As discussed in ISMSC, FAM 18.6, 1984, p.282 (ISSCC, FAM18.6, 1984, p282), the size of MOS transistors is reduced. As the degree of integration of the DRAM increases, problems such as a reduction in stress breakdown voltage due to hot carriers in the MOS transistor arise. In order to prevent this, it is conceivable that only the power supply voltage used in the memory array that needs to be miniaturized to improve the degree of integration is lowered in consideration of the stress breakdown voltage. For example, the external power supply voltage V _CC is applied to the peripheral circuit portion (X decoder, Y decoder, etc.) of the DRAM, and the operating voltage V _L (| V _L | <| V _CC lower than V _CC is applied to the memory cell array portion including the sense amplifier. |). That is, the voltage supply line connected to the source of the P channel MOS transistor of the sense amplifier in FIG. 5 is set to V _L, and the voltage supply line of the peripheral circuit section is set to V _CC .

However, it has been found that in CMOS / DRAM, when the operating voltage of the memory array section is lowered as described above, the operating speed is significantly reduced. As a result of detailed analysis, it has been clarified that the cause is an increase in threshold voltage due to the back gate bias effect of the P-channel MOS transistor. That is, the potential of the source of the P channel MOS transistor formed in the N well in the P type substrate is the internal power supply voltage V _L , and the potential of the N well (back gate of the P channel MOS transistor) is the external power supply voltage V _CC . Then, a back gate bias of V _CC -V _L is applied to the P channel MOS transistor, and the threshold voltage rises.

FIG. 6 is a plot of the threshold voltage against the difference (back gate bias) between the back gate (N well) voltage and the source voltage of a P-channel MOS transistor having a gate length of 1.2 μm and a gate width of 10 μm. . In this example, when a back gate bias of 2V is applied, the threshold voltage of about 0.35V increases. If V _L = 3V, for example, with respect to the power supply voltage V _CC that is currently widely used in LSIs, the threshold voltage rise of 0.35V exceeds 10% of the operating voltage, which directly leads to speed degradation. .

  Another object of the present invention is to solve the first problem and to provide a voltage limiter circuit that is stable in operation.

  Another object of the present invention is to solve the second problem and provide a voltage limiter circuit with low noise, a small occupied area, and low power consumption.

  Still another object of the present invention is to solve the third problem and to provide a high speed and high reliability CMOS large scale integrated circuit (LSI).

  In addition to the above, an object of the present invention is to provide an actual configuration of an ultra-large scale integrated circuit.

  Still another object of the present invention is to provide an actual layout of a very large scale integrated circuit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  In order to achieve the above object, in the present invention, two FETs having different threshold voltages are used in the enhancement type, and a potential difference when a current of a constant ratio is passed through them is taken as a reference voltage.

  In order to solve the first problem, in the present invention, when the voltage limiter needs to drive many types of loads, the drive circuit constituting the voltage limiter is divided into a plurality according to the type of load. Each is subjected to phase compensation. When the type and size of the load change with time depending on the operation mode of the semiconductor device, the circuit constants of the drive circuit and the phase compensation circuit are changed according to each operation mode. Alternatively, a separate drive circuit is provided for each operation mode, and these outputs are connected to provide an output of the voltage limiter.

  The second problem is that a voltage limiter circuit and a load circuit such as a pulse generation circuit that uses its output as a power supply are arranged close to each other, and a plurality of loads are selected / unselected by a control signal such as an address signal. This is solved by sharing one voltage limiter circuit in the circuit.

  In order to solve the third problem, in the present invention, the back gate (well) voltage of the MOS transistor formed in the well in the CMOS LSI is made equal to the operating voltage supplied to the source terminal.

  Since two FETs with different threshold voltages are used without using a depletion type FET, the difference between the threshold voltages can be made sufficiently small (in principle, it can be as small as possible). Therefore, it is easy to match the characteristics of the two FETs as compared with the prior art, and a reference voltage that is more stable than the prior art can be obtained.

  When the voltage limiter needs to drive many types of loads, the drive circuit can be divided into multiple parts according to the load, and phase compensation can be applied to each to optimize the phase compensation according to the type of load. become. Also, depending on the operation mode of the semiconductor device, the circuit constants of the drive circuit and phase compensation circuit can be changed, or individual drive circuits can be provided for each operation mode, and their outputs can be connected to become the output of the voltage limiter. This makes it possible to perform optimal phase compensation corresponding to load fluctuations. Thereby, a stable voltage limiter circuit can be formed.

  By placing the voltage limiter circuit close to the load circuit such as a pulse generation circuit that uses its output as a power supply, the impedance of the wiring between them can be reduced, and the level of generated noise can be suppressed. it can. In addition, the number of voltage limiter circuits can be reduced by sharing one voltage limiter circuit among a plurality of load circuits having a selection / non-selection relationship based on a control signal such as an address signal. Therefore, the area occupied by the circuit and the power consumption can be reduced. Here, the voltage limiter circuit need only drive the circuit in the selected state among the load circuits. Therefore, it is not necessary to increase the current drive capability of the voltage limiter circuit by sharing.

In the CMOS LSI, the MOS transistor formed in the well can prevent the threshold voltage from rising due to the back gate bias effect by setting the well voltage to the internal power supply voltage _VL .

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  According to the present invention, since the internal voltage inspection result is output to the outside as a digital signal, it is easy to inspect the internal voltage from the outside with a memory tester or the like.

  As described above, according to the present invention, an ultra large-scale semiconductor integrated circuit can be actually provided, and these characteristics, stable operation, and the like can be achieved.

  Hereinafter, the present invention will be described using examples.

  This description is divided into first, second, and third groups to facilitate understanding, and will be described in this order. Therefore, application to actual ultra-large scale integrated circuits is explained in each group. However, this will be understood by those skilled in the art that these groups are not meant to be completely independent. In other words, these groups naturally suggest the combination when it is technically possible to perform the combination in combination. Furthermore, as will become apparent from the following description, the first, second, and third groups are not mutually exclusive technologies, and in most cases they are more effective when combined. Those skilled in the art will understand that this is a technology.

[First group]
Embodiments of the first group of the present invention will be described below with reference to the drawings. In the following description, a case where a positive reference voltage is generated will be described, but a negative reference voltage can also be generated by reversing the polarity of the transistor.

FIG. 1A shows a circuit diagram of a first embodiment of the present invention. This circuit comprises N-channel MOSFETs Q _{61 to} Q ₆₃ and P-channel MOSFETs Q ₆₄ and Q ₆₅ , and V _DD is a positive external power source. Among N-channel MOSFETs, Q ₆₂ and Q ₆₃ are enhancement type FETs (hereinafter referred to as EMOS) having a standard threshold voltage V _TE , and Q ₆₁ is an enhancement having a threshold voltage V _TEE higher than V _TE. FET (hereinafter abbreviated as EEMOS). The operation of this circuit will be described below.

The P-channel MOSFETs Q ₆₄ and Q ₆₅ share a gate and a source and constitute a so-called current mirror circuit 70. That is, the ratio between the drain current I ₂ of the drain currents I ₁ and Q ₆₅ of Q ₆₄ operates as a constant. Its current ratio (mirror ratio) is determined by a constant ratio between Q ₆₄ and Q _65. If the constants of Q _{61 to} Q ₆₃ are equal and all operate in the saturation region, the following three equations are established.

I ₁ = (β _EE / 2) · (V ₁ −V _TEE ) ² (7)
I ₁ = (β _E / 2) · (V ₁ −V _R −V _TE ) ² (8)
I ₂ = (β _E / 2) · (V _R −V _TE ) ² (9)
Here, β _EE is the conductance coefficient of EEMOS (Q ₆₁ ), β _E is the conductance coefficient of EMOS (Q ₆₂ , Q ₆₃ ), and V ₁ is the voltage of node 61. From the equations (7) to (9),
V ₁ = 2V _R (10)
V _R = (V _TEE −xV _TE ) / (2-x) (11)
However,
x = (αβ _E ) / (β _EE ) (12)
Here, α is the mirror ratio of the current mirror circuit 70 (I ₁ : I ₂ = α: 1). In particular, α = 1 when the constants of Q ₆₄ and Q ₆₅ are the same. At this time, if β _EE ≈ β _E , V _R = V _TEE −V _TE (13)
It becomes. That is, as the reference voltage V _R , a difference voltage between the EEMOS and the EMOS is obtained, which is a stable voltage that does not depend on the voltage of the external power supply V _DD . Incidentally, V ₁ in place of V _R (= 2V _R) may be used as the reference voltage.

The characteristic of this reference voltage generation circuit is that it is easy to match the characteristics of the MOSFET as compared with the prior art. In order to operate Q _{61 to} Q ₆₃ in the saturation region, V _TEE ≧ 2 V _TE , that is, V _TEE −V _TE ≧ V _TE suffices. This is because the threshold voltage difference V _TEE −V _TE is smaller than that in the prior art (for example, 0.7 V, and the difference in the impurity profile of the channel region can be reduced as compared with the conventional case).

In the circuit according to the present invention, since the difference in temperature dependency dV _T / dT of the threshold voltage can be reduced, a stable reference voltage can be obtained even with respect to temperature. The ratio α may be adjusted. Next, the method will be described. When the equation (11) is differentiated by the temperature T,
dV _R / dT = (1 / (2-x)) · (dV _TEE / dT)
-(X / (2-x)) ・ (dV _TE / dT) (14)
Therefore, if the mirror ratio α is set so that dV _TEE / dT = x · dV _TE / dT, the temperature dependence of the reference voltage can be made dV _R / dT = 0.

  Note that it is desirable that the channel length of the MOSFET used in this circuit be somewhat long. For example, even if a MOSFET having a channel length of about 1 μm is used in another circuit of the semiconductor device, it is preferable to use a MOSFET having a channel length longer than that, for example, 5 μm or more. In the equations (7) to (9), for the sake of simplicity, the drain current in the saturation region depends only on the gate-source voltage. However, in practice, it slightly changes depending on the drain-source voltage. The longer the channel length, the smaller the rate of change (drain conductance), and the better the stability of the reference voltage. Also, a longer channel length is better in order to suppress threshold voltage fluctuations due to the short channel effect.

In the circuits of FIGS. 1A, 1B, and 1C, the back gates of MOSFETs Q _{61 to} Q ₆₃ for generating a reference voltage are connected to their respective sources, but are connected to a common substrate terminal. You may make it do. However, since the threshold voltage of the MOSFET varies depending on the back gate voltage, it is better to connect it to the source in order to avoid the influence.

Here, the current mirror circuit used in the present invention will be supplemented. The current mirror circuit is not limited to a circuit composed of two MOSFETs used in the embodiment of FIG. For example, the circuit of FIG. 1 (b) or (c) may be used. These circuits are known as cascode type and Wilson type, respectively. These circuits are characterized by good mirror characteristics. That is, in the current mirror circuit shown in FIG. 1 (a) may vary slightly mirror ratio α by a change in the drain-source voltage of Q ₆₄ and Q _65, FIG. 1 (b) or the circuit of FIG. 1 (c) Then the amount of change is small. Therefore, when applied to the present invention, the mirror ratio can be set more accurately, and a more stable reference voltage can be obtained. The current mirror circuit may be a circuit using a bipolar transistor instead of the MOSFET as shown in FIG. In the following embodiments, for the sake of simplicity, a diagram using the current mirror circuit of FIG. 1A is mainly shown. However, the circuits of FIGS. 1B to 1D are applied to these embodiments. It goes without saying.

FIG. 8 shows a second embodiment of the present invention. This circuit is obtained by replacing Q ₆₃ in FIG. 1A with a resistor R ₆₁ . If the constants of Q ₆₁ and Q ₆₂ are equal and both are operating in the saturation region, the following three equations are established.

I ₁ = (β _EE / 2) · (V ₁ −V _TEE ) ² (15)
I ₁ = (β _E / 2) · (V ₁ −V _R −V _TE ) ² (16)
I ₂ = V _R / R ₆₁ (17)
From these equations, the mirror ratio α = 1, β _EE ≒ β _E
V _R = V _TEE −V _TE (18)
Thus, the difference voltage between the EEMOS and the EMOS is obtained as the reference voltage V _R.

  The feature of this embodiment is that the difference in threshold voltage between EEMOS and EMOS can be made smaller than in the case of FIG. Therefore, it is easier to match the characteristics of the MOSFET. However, in the normal MOS process, the MOSFET can generally occupy a smaller area than the resistor. Therefore, when the threshold voltage difference may be large to some extent, the embodiment of FIG.

FIG. 9A shows another embodiment of the present invention. The difference from the embodiment of FIG. 1 (a) is in the method of keeping the ratio of currents I ₁ and I ₂ constant. In the case of FIG. 1A, the current mirror circuit 70 directly kept the ratio of I ₁ and I ₂ constant, but in this embodiment, two sets of current mirror circuits 71 and 72 indirectly realize this. To do. That is, a current mirror circuit 71 composed of four N-channel MOSFETs (which is the cascode type described above) keeps I ₂ and I ₃ at a constant ratio, and at the same time, a current mirror circuit composed of two P-channel MOSFETs. 72 keeps I ₃ and (I ₁ + I ₂ ) at a constant ratio. This keeps the ratio of I ₁ and I ₂ constant. For example, if the mirror ratio of the circuit 71 is I ₂ : I ₃ = 1: 1 and the mirror ratio of the circuit 72 is I ₃ : (I ₁ + I ₂ ) = 1: 2, I ₁ : I ₂ = 1: 1. It becomes.

The feature of this embodiment, the drain-source voltage of Q ₆₂ is that substantially constant. In the embodiment of FIG. 1 (a), approximately V _DD voltage of the drain (node 62) of _{Q 62 - | V TP | (} V TP is the threshold voltage of the P-channel MOSFET) is, this external supply voltage _Varies with V _DD variation. The change in the drain voltage causes a change in the drain current due to the drain conductance, resulting in a change in the reference voltage V _R. In this embodiment contrast, the drain voltage of Q ₆₂ is because it is kept at 2V _R, it is possible to obtain a more stable reference voltage with respect to V _DD.

This is an embodiment having a similar purpose to the circuit of FIG. In this circuit, a current mirror circuit 73 made up of two EEMOSs keeps I ₂ and I ₄ at a fixed ratio, and a current mirror circuit 72 made up of two P-channel MOSFETs makes up I ₄ and (I ₁ + I ₂ ). Is kept constant, the ratio of I ₁ and I ₂ is kept constant.

Although all of the embodiments so far have been based on the threshold voltage difference of the N-channel MOSFET, the threshold voltage difference of the P-channel MOSFET can also be used as a reference. Examples are shown in FIGS. 10 (a) and 10 (b). Q ₇₄ is a P-channel MOSFET having a standard threshold voltage V _TP , and Q ₇₃ is a P-channel MOSFET having a threshold voltage V _TPE lower than V _TP (negative and large in absolute value). _Assuming that both Q ₇₄ and Q ₇₃ are operating in the saturation region, the following two equations hold.

I ₁ = (β _PE / 2) · (−V ₃ −V _TPE ) ² (19)
I ₂ = (β _P / 2) · (V _R −V ₃ −V _TP ) ² (20)
Here, V ₃ is the voltage of the node 63, and β _PE and β _E are the conductance coefficients of Q ₇₃ and Q ₇₄ , respectively. From these equations, I ₁ : I ₂ = 1: 1, β _PE ≈β _E
V _R = V _TP −V _TPE (21)
Thus, the threshold voltage difference of the P-channel MOSFET is obtained as the reference voltage V _R.

  This embodiment is suitable for incorporation in a semiconductor integrated circuit formed on a P-type substrate and requiring a stable reference voltage. As described above, the back gate of the MOSFET for generating the reference voltage is preferably connected to each source. However, in a semiconductor integrated circuit on a P-type substrate, the N-channel MOSFET is usually formed directly on the substrate, and all of its back gates are connected to a common substrate terminal. Therefore, when the substrate voltage varies, the threshold voltage of the N-channel MOSFET changes. On the other hand, since the P-channel MOSFET is formed in an N-type well, the back gate (well) of each MOSFET can be connected to the source so as not to be affected by fluctuations in the substrate voltage. For example, in a DRAM, it is common to use a P-type substrate and apply a voltage (usually about −3 V) generated by a substrate voltage generating circuit provided on the chip to the substrate. However, this substrate voltage tends to fluctuate due to fluctuations in the external power supply voltage and memory operation. In such a case, the circuit of this embodiment is particularly effective. Conversely, in a semiconductor integrated circuit formed on an N-type substrate, a circuit based on the threshold voltage difference of the N-channel MOSFET is better.

FIG. 10B is also a circuit based on the threshold voltage difference of the P-channel MOSFET. The difference from the previous embodiments is the method of setting the operating point (operating current). The embodiments so far have been so-called self-bias type circuits in which the operating point is automatically determined in the reference voltage generation circuit. However, in this circuit, a circuit 76 for setting the operating point is provided independently. The current I ₅ flowing through the operating point setting circuit 76 is mainly determined by the resistor R ₆₂ (which may be replaced with a MOSFET). The operating currents I ₁ and I ₂ of the reference voltage generating circuit are determined by I ₅ and two sets of current mirror circuits 72 and 75. For example, if the mirror ratio of the circuit 72 is I ₅ : (I ₁ + I ₂ ) = 1: 2, and the mirror ratio of the circuit 75 is I ₅ : I ₂ = 1: 1, then I ₁ = I ₂ = I ₅ Become.

  Since this circuit is independent of the operating point setting circuit, it has a feature that the operating point varies less due to device variations than the self-bias type circuit, and therefore the current consumption varies less.

In the self-bias type circuit, it is desirable to add a starting circuit. The starting circuit is a circuit for preventing the circuit from falling into an undesirable stable point. For example, in the circuit of FIG. 9A, the desirable stable point is a state in which V _R is normally generated as described above. At this time, the voltage V ₃ = 2V _{R at} the node 63 and the voltage V _{4 at the} node 64 ≈ V _DD − | V _TP |. However, in addition to this, there is a stable point of I ₁ = I ₂ = 0. At this time, V ₃ = 0, V ₄ = V _DD , and VR = 0. In order to prevent the circuit from falling into this stable point, for example, a starting circuit 77 as shown in FIG. 11 may be added. P-channel MOSFETs Q ₇₅ and Q ₇₆ and a resistor R ₆₃ (which may be replaced by a MOSFET) constitute a current source. When the circuit is at an undesired stable point, V ₃ = 0 and the EEMOS Q ₇₇ is in an emergency state, so node 60 is charged by the current source. Q _{78 then} becomes conductive and raises the voltage at node 63, causing the circuit to escape from an undesired stable point. When the circuit reaches the desired stable point, V ₃ exceeds V _TEE , Q ₇₇ becomes conductive, and the voltage at node 60 drops. Then, Q ₇₈ becomes non-conducting and does not affect the operation of the reference voltage generating circuit body.

Next, an example in which the present invention is applied to a DRAM will be described. FIG. 12 is a configuration diagram of a DRAM provided with an on-chip voltage limiter for operating the memory array at an internal voltage V _L lower than the external power supply voltage V _CC . In order to generate the internal voltage V _L , the reference voltage generation circuit according to the present invention is used. In the figure, 6 is a reference voltage generating circuit according to the present invention, 24 is a differential amplifier, 7a and 7b are buffers, 30 is a word line booster circuit, 2 is a memory array in which memory cells MC are arranged vertically and horizontally, 33 is a sense amplifier, 31 is a word driver.

The differential amplifier 24 and the two resistors R ₂₁ and R ₂₂ are circuits for generating a memory array operating voltage V _R ′ from the output voltage V _R of the reference voltage generating circuit 6 as shown in the following equation.

V _R '= ((R ₂₁ + R ₂₂ ) / (R ₂₂ )) · V _R (22)
V _R is since the reference is the threshold voltage difference of the FET, as described above, not necessarily the appropriate voltage as the operating voltage of the memory array. And performs conversion to V _R 'from V _R by the circuit for that. For example, if V _R = 1V and V _R ′ = 3V, R ₂₁ : R ₂₂ = 2: 1 may be set. Also, R ₂₁ and R ₂₂ may be made variable so that V _R ′ can be finely adjusted, so-called trimming. As a trimming method, for example, the method described in the aforementioned US patent can be used.

The buffers 7a and 7b are circuits for increasing the current drive capability of V _R ′. The buffer is constituted by a differential amplifier composed of MOSFETs Q _{21 to} Q ₂₄ and a current source I ₂₅ and an output stage composed of MOSFET Q ₂₆ and a current source I ₂₇ . Since the configuration of 7b is the same as that of 7a, the illustration is omitted in the figure. This circuit operates so that the voltages of the outputs V _L1 and V _L2 follow the input voltage V _R ′ because feedback is applied from the output stage to the input of the differential amplifier. That is, it is possible to obtain outputs V _L1 and V _L2 having a large driving capability while keeping the voltage value as it is. V _L1 and V _L2 are used to drive the sense amplifier and the word line of the memory cell, respectively. In the present embodiment, a technique called word boost is used in which the word line voltage is made higher than the operating voltage of the memory array (here, V _L1 ). For this purpose, a word line booster circuit 30 is provided. For this purpose, a word line booster circuit 30 is provided. However, the power source 30 is not the external power source V _CC but the internal power source V _L2 . Therefore, the word line drive signal φ _X is boosted with reference to V _L2 . The word driver 31 receives the φ _X and the decoder output XD and drives the word line WL.

The sense amplifier 33 used in this embodiment is a normal CMOS sense amplifier composed of P channel MOSFETs Q ₁₂₅ and Q ₁₂₆ and N channel MOSFETs Q ₁₂₇ and Q ₁₂₈ . 33 is started by turning on the MOSFETs Q ₁₃₆ and Q _{137 by} setting φ _S to a high level and / φ _S to a low level. However, since the source of Q ₁₃₇ is connected not to the external power supply V _CC but to the internal power supply V _L1 , 33 operates so that the high level side of the data line is set to V _L1 and the low level side is set to the installation potential. Become. That is, the amplitude of the data line is suppressed to V _L1 .

Next, another embodiment in which the present invention is applied to a DRAM will be introduced. FIG. 13 is a circuit diagram of a 16 Mbit DRAM to which the present invention is applied, FIG. 14 is an in-chip layout diagram, and FIG. 15 is a detailed layout diagram of the voltage limiter 13. In the layout diagram, some circuits are omitted for simplicity. In the figure, 1 is a semiconductor chip, 2 is a memory array, 31 is a word driver, 32 is a row decoder, 33 is a sense amplifier, 34 is a data line precharge circuit, 35 is a data line selection circuit, 36L and 36R are switch circuits, 37 is a column decoder, 38 is a main amplifier, 39 is a data output buffer, 40 is a data input buffer, 41 is a write circuit, 42 is a row address buffer, 43 is a column address buffer, 44 is a timing generation circuit, and 45 is a sense amplifier drive. A signal generation circuit, 46 is a word line voltage generation circuit, 47 is a data line precharge line pressure generation circuit, and 48 is a substrate voltage generation circuit. Reference voltage generating circuit 6 according to the invention in the voltage limiter circuit 13, 6a voltage conversion circuit, 7a, 7b, 7c are drive circuit, 4a, 4b, 4c the bonding pads of the ground V _SS, 5a, 5b external This is a bonding pad for the power supply voltage V _CC . The reference voltage generation circuit 6 generates a stabilized voltage V _R (here, 1.1 V) with respect to the external power supply voltage V _CC (here, 5 V), and each of the voltage conversion circuits 6 a is V _R ′ (here, 3 V). .3V). Based on V _R ′, the drive circuit generates a power supply voltage V _L1 for the memory array and a power supply voltage V _L2 for the peripheral circuit. In this example, the voltage levels of V _L1 and V _L2 are both 3.3V.

The first feature of this embodiment is that the voltage limiter circuit is also applied to the peripheral circuit. V _L1 is supplied to 45 and 47, and V _L2 is supplied to 32, 37, 38, 40, 41, 42, 43, 44, 46, and 48, respectively. That is, circuits other than the data output buffer 39 operate with the internal power supply voltage V _L1 or V _L2 . By operating the peripheral circuit with the stabilized voltage V _L1 lower than the external power supply voltage V _CC , the power consumed in the peripheral circuit can be reduced and the operation can be stabilized.

The second feature of the present embodiment is that the voltage limiter circuit 13 is arranged at the center of the semiconductor chip. Thereby, the voltage drop due to the impedance of the wirings 11a and 11b of the internal power supply voltages V _L1 and V _L2 is reduced. As a result, the operation of the circuit using V _L1 and V _L2 as a power source becomes stable and fast.

The third feature of this embodiment is the ground wiring method. First, a dedicated short ground wiring 8 is provided for the reference voltage generation circuit and the voltage conversion circuit. Next, ground wirings 9a and 9b are provided for the drive circuit. The bonding pad 4b for the voltage limiter circuit is provided separately from the bonding pads 4a and 4c for the other circuits. Thereby, it is possible to prevent the noise generated on the ground wiring due to the current flowing when each circuit operates from adversely affecting other circuits. In particular, if noise occurs in the ground wiring of the reference voltage generation circuit and the voltage conversion circuit, the levels of the internal power supply voltages V _L1 and V _L2 fluctuate and affect almost all circuits in the chip. It is desirable to keep it as short as possible and separate from other ground wiring. For this purpose, it is most desirable to separate the bonding pads from the bonding pads. However, the bonding pads may be separated from the wiring take-out portion in common. Further, although not shown in the figure, it is desirable that the ground wiring for the memory array is also separated from other wiring. This is because, in a DRAM, when a sense amplifier performs an amplification operation, a large number of data lines (whose capacities are generally several thousand pF in total) are charged and discharged simultaneously, and a large noise is generated in the ground wiring.

A fourth feature of the present embodiment is a method for power supply wiring. Bonding pads for the external power supply voltage V _CC are provided separately for the memory array 5a and the peripheral circuit 5b. The memory array drive circuit 7a is disposed close to 5a, and the peripheral circuit drive circuits 7b and 7c are disposed close to 5b. Thereby, the voltage drop in power supply voltage 10a, 10b can be reduced. Of course, this voltage drop is absorbed by each drive circuit, but if the drop is too large, it cannot be absorbed and the internal power supply voltage V _L1 or V _L2 may be lowered. In order to prevent this, it is desirable to reduce the impedance of the wirings 10a and 10b as in this embodiment. The reason for providing separate bonding pads for the peripheral circuit and the memory array is that, as in the case of the above-mentioned grounding, noise generated on the power supply cable due to the current that flows when the circuit operates will adversely affect other circuits. This is to prevent giving. The power supply for the reference voltage generation circuit and the voltage conversion circuit is wired from 5b here, but of course, another bonding pad may be provided.

Although not shown in the drawing, it is desirable that the ground wiring and power supply wiring for the data output buffer are also separated from the other ground wiring and power supply wiring. This is because the external load (usually several hundred pF) is charged / discharged when the data output buffer operates, so that large noise is generated in the ground wiring and the power supply wiring (the data output buffer operates directly at the external power supply voltage V _CC ). Because it does.

  Hereafter, each part of a present Example is demonstrated in detail.

First, the reference voltage generation circuit 6 will be described. As the reference voltage generating circuit, the circuits shown in FIGS. 1A to 1D and FIGS. 8 to 11 can be used. Here, as described above, in order to reduce the influence of the substrate potential fluctuation, it is desirable to connect the back gate of each MOSFET to the respective source. For example, in the circuits of FIGS. 10A and 10B, the threshold voltage difference between the P-channel MOSFETs Q ₇₃ and Q ₇₄ is the reference voltage V _R. In this case, as Q ₇₃ and Q ₇₄ , for example, P-channel MOSFETs having a structure shown in FIGS. 16A and 16B may be used. FIG. 16A is a layout view, and FIG. 16B is a cross-sectional view. In the figure, 101 is a P-type semiconductor substrate, 102 is an N-type well, 103 is an N + diffusion layer, 107 is a P + diffusion layer, 104 is SiO ₂ for isolation, 106 is polycrystalline silicon or metal serving as a gate, Reference numeral 113 denotes an interlayer insulating film, 108 denotes a wiring layer, 115 denotes a protective film, and 116 denotes a contact hole. The source diffusion layer (P + diffusion layer on the left side of the figure) and the N well are connected by the wiring layer 108. This terminal corresponds to the node 66 in the circuit diagrams of FIGS. This structure can be made by a normal CMOS process. FIGS. 17A and 17B are examples in which the well has a double structure. In the figure, 111 is an N-type substrate, and 112 is a P-type well. In this manner, the substrate 111 and the back gate 102 of the MOSFET are electrostatically shielded by making the well have a double structure and fixing the potential of the outer well 112 (for example, grounding). Therefore, interference noise through the parasitic capacitance between them can be prevented, and the influence of substrate potential fluctuation can be almost completely eliminated. Note that the substrate 111 may be connected to an external power supply V _CC , for example. This structure can be formed by adding only one step of forming a well to a normal CMOS process, and a great effect can be obtained at a relatively low cost.

In the circuits of FIGS. 1A to 1D, FIG. 8, FIG. 9A, and FIG. 11B, the threshold voltage difference between the N-channel MOSFETs Q ₆₁ and Q ₆₂ is the reference voltage. When these circuits are used, an N-channel MOSFET having a structure in which the conductivity type is reversed in FIGS. 16A and 16B or FIGS. 17A and 17B may be used.

A pair of MOSFETs for generating a reference voltage In the case of FIGS. 10A and 10B, Q ₇₃ and Q ₇₄ , FIGS. 1A to 1D, FIGS. 8, 7A and 7B are used. In the case of FIG. 11, it is desirable that the layout patterns of Q ₆₁ and Q ₆₂ ) are geometrically congruent figures and arranged in the same direction in order to reduce the influence of manufacturing process variations. For example, by making the contact hole arrangement method on the source / drain diffusion layer the same, the influence of the diffusion layer resistance can be made the same. Further, by making the channel directions the same, it is possible to eliminate the influence of the difference in mobility depending on the crystal plane direction.

Next, the voltage conversion circuit 6a will be described. FIG. 18 shows a method for realizing the voltage conversion circuit. In the figure, 24 is a differential amplifier, 25 is a trimming circuit, Q _{39 to} Q ₄₇ and Q ₄₉ are P-channel MOSFETs, and F _{4 to} F ₇ are fuses. A related embodiment will be described with reference to FIGS. 35, 37, and 39 (a). This circuit generates a voltage V _R 'that is a constant multiple of the reference voltage V _R. Also, fine adjustment of the voltage to compensate for variations in V _R due to the manufacturing process (trimming) is possible.

V _R is input to one input terminal of the differential amplifier 24, and a voltage V _R ″ obtained by dividing V _R ′ by MOSFETs Q _{44 to} Q ₄₇ and Q _{39 to} Q ₄₂ is fed back to the other input terminal. Is sufficiently large, the output voltage V _R ′ is given by the following equation.

V _R '= ((R _T1 + R _T2 ) / R _T2 ) · V _R
Here, R _T1 is a resistance value when a circuit composed of Q _{44 to} Q ₄₇ is regarded as equivalent resistance, and R _T2 is a resistance value when a circuit composed of Q _{39 to} Q ₄₂ is regarded as equivalent resistance. It is. Since R _T1 and R _T2 are changed by cutting the fuse, V _R ′ can be adjusted. Since the standard values of V _R and V _R ′ are 1.1 V and 3.3 V, respectively, as described above, R _T1 : R _T2 = 2: 1 is set when the fuse is not blown. When V _R > 1.1 V, R _T2 is increased by cutting F _{4 to} F _6, and when V _R <1.1 V, R _T1 is increased by cutting F ₇ , and V _R It can be adjusted so that ′ does not deviate significantly from the standard value.

The MOSFET · Q ₄₉ and Q ₅₀ is for the V _R '= 0V when the test mode. In the test mode, the signal T _E becomes V _CC level, and the output V _R ′ becomes 0V.

The circuit shown in FIG. 18 has an advantage that the occupied area is small when manufactured by a normal MOS process as compared with the circuit described in US Pat. No. 4,100,347. That is, in the circuit described in the US patent, a resistor is used as an element for dividing the output voltage V _R ′, whereas in the circuit of FIG. 18, a MOSFET is used. In order to reduce the current consumption of the circuit, the equivalent resistance of the voltage dividing element must be considerably large (about several hundred kΩ). In a normal MOS process, an element with a smaller area and a larger equivalent resistance can be obtained with a MOSFET than with a resistor. However, if MOSFETs are used, there is a concern that the characteristics of V _R ′ may fluctuate due to fluctuations in the threshold voltage. This can be solved by selecting the fuse cutting method while avoiding the influence of the substrate potential fluctuation by connecting to the capacitor and further considering the variation of the threshold voltage. Note that the MOSFET used for this trimming desirably has the structure shown in FIGS. 16A and 16B or FIGS. 17A and 17B in order to reduce the influence of substrate potential fluctuation.

It is desirable to add a capacitor having a large capacity between the terminals of the reference voltages V _R and V _R ′ and the ground. This is to reduce the impedance of V _R and V _R ′ with respect to the high frequency and to bypass the high frequency noise. In particular, as shown in FIG. 15, when the V _R ′ wiring 12a inevitably intersects with another wiring, it also has the meaning of stabilizing the operation of the voltage limiter circuit (preventing oscillation). The reason for this will be described with reference to FIG.

The drive circuits 7a and 7b generate voltages V _L1 and V _L2 having a large current drive capability from V _R ′, respectively. The V _L1 , V _L2 itself, or the output 16 of the circuit operating with V _L2 as the power source such as the pulse generation circuit 14 (its voltage level is V _L2 ) is the wiring line V _R ′, the wiring line V _R ′ When crossing 12a, as shown in 17a to 17c, a feedback loop is formed via a parasitic capacitance C _C3 between the wirings. If the gain of this loop is larger than 1 (0 dB), the circuit oscillates, and if it is smaller than 1, the circuit operation becomes unstable if there is little margin. In order to prevent this, capacitors C _R1 and C _R2 sufficiently larger than C _{C1 to} C _C3 are inserted between V _R ′ and the ground, and the gain of the loop is made sufficiently small (for example, −10 dB or less). Just keep it.

An example of a method for realizing the capacitor used here is shown in FIGS. 20A is a layout diagram, and FIG. 20B is a cross-sectional view. In the figure, 101 is a P-type semiconductor substrate, 102 is an N-type well, 103 is an N + diffusion layer, 104 is an SiO ₂ for isolation, 105 is a gate insulating film, 106 is a polycrystalline silicon or metal serving as a gate, Reference numeral 113 denotes an interlayer insulating film, 108 denotes a wiring layer, 115 denotes a protective layer, and 116 denotes a contact hole. The capacitor is formed between the gate 106 and the substrate surface 102a with the gate insulating film interposed therebetween, as in a normal MOS capacitor. Since a thin gate insulating film is used as the capacitor insulating film, a large capacitance can be obtained with a relatively small area. However, the difference from a normal MOS capacitor is that the threshold voltage (flat band voltage) is negative because of the N well under the gate. Therefore, as long as a unidirectional voltage is applied so that the gate side becomes positive, the power collection capacity is almost constant. The steps required to make this capacitor are well formation, isolation region formation, gate insulating film formation, gate formation, diffusion layer formation, and wiring steps, all of which are included in the normal CMOS process. This is a process. Therefore, in the case of a semiconductor device manufactured by a CMOS process, it is not necessary to add a special process to make this capacitor.

One implementation method of the drive circuits 7a and 7b is shown in FIG. In the figure, 21 is a differential amplifier, consisting of MOSFET · Q ₂₁ ~Q _25. Reference numeral 22 denotes an output stage comprising MOSFETs Q _{26 to} Q ₂₇ . C _L is an equivalent representation of the load (memory array or peripheral circuit) of the drive circuit with a single capacitor. Of the two input terminals of the differential amplifier 21, the reference voltage V _R ′ is input to one, and V _L1 (V _L2 ) is fed back from the output stage to the other. Therefore, this circuit operates so that V _L1 (V _L2 ) follows V _R ′. Reference numeral 23 denotes a so-called position compensation circuit for stabilizing the operation of the feedback amplifier composed of 21 and 22. The MOSFETs Q _{28 to} Q ₃₀ are for setting the output to a high impedance when the drive circuit is in an inactive state and for setting V _L1 (V _L2 ) to the V _CC level in the test mode. That is, in the inactive state, the test signal TE is at a low level, the activation signal φ ₁ ′ (φ ₂ ′) is at a low level, the gate V _CC level of Q ₂₆ is reached, and the output V _L1 (V _L2 ) is High impedance. At this time, since Q ₂₅ and Q ₂₇ are in a non-conductive state, the power consumption of the circuit is reduced. In the test mode, TE becomes V _CC level, the gate of Q ₆ becomes low level, and V _CC is directly output. One implementation method of the drive circuit 7c is shown in FIG. Even in this circuit, when the activation signal φ ₃ ′ is at a low level, the output has a high impedance. Since the phase compensation circuit of this time can be shared with that of 7b (because 7b and 7c are connected in parallel), no phase compensation circuit is particularly provided here.

As described above, the drive circuit 7a is a circuit for generating V _L1 , and 7b and 7c are circuits for generating V _L2 . In the normal state, 7c is always activated, and 7a and 7b are activated only when the memory is in operation. Therefore, the activation signal φ ₃ ′ is always at the V _CC level, φ ₁ ′ and φ ₂ ′ are at the memory operation timing (details of timing will be at the V _CC level as described later. In the test mode, φ ₁ ′, φ ₂ ′ and φ ₃ ′ are all at a low level, and the test signal TE is at the V _CC level, where V _L1 and V _L2 are both equal to V _CC , which is obtained by directly applying an external power supply voltage. is effective to examine the operation of the memory (for example, the power supply voltage dependency of the access time). immediately after the power is turned on in order to speed up the rise of V _L1 and _{V L2, φ 1 ', φ} 2', φ 3 ' In addition, as described later, V _L2 is used to generate the word line voltage V _CH and the substrate voltage V _{BB, so} that the voltage levels of V _CH and V _BB are standard values. If you to activate phi ₂ 'when deviated from, It is possible to improve the stability of these voltages. Note that the activation signal _{φ 1 ', φ 2',} φ 3 ' and of the high level of the test signal TE is set to V _CC without a V _L2 is This is to ensure that the P-channel MOSFETs Q ₂₈ and Q ₂₉ are in a non-conductive state.

The drive circuits 7a and 7b must have a large current drive capability. This is because when the memory is in an operating state, 7a and 7b need to drive a large load load (several hundred to several thousand pF). In particular, 7a has to drive a large number of data lines when the sense amplifier performs an amplification operation. For example, if the capacity of one data line is 0.3 pF and the number of sense amplifiers operating simultaneously is 8192, the total capacity is 2500 pF. Therefore, as the output MOSFETs Q ₂₆ of 7a and 7b, for example, those having a channel width / channel length of about 3000 μm / 1.2 μm are used. 7c only needs to have a current drive capability sufficient to guarantee a leakage current when the memory is in a standby state, and therefore its output MOSFET may be about 100 μm / 1.2 μm.

The connection circuit 15 is for preventing the potential difference between V _L1 and V _{L2 from} becoming too large. This is because if the potential difference between V _L2 and V _L1 is large, a mismatch in signal exchange between the memory array and the peripheral circuit may occur. An example of this circuit is shown in FIG. In the figure, Q ₁ , Q ₂ and Q ₅ are N-channel MOSFETs, and Q ₄ is a P-channel MOSFET. Assuming that the threshold voltage of the N-channel MOSFET is V _TN , Q ₁ is conductive when V _L1 −V _L2 > V _TN and Q ₂ is conductive when V _L2 −V _L1 > V _TN . Therefore, the potential difference between V _L1 and V _L2 is kept within V _TN . A signal WK that becomes high only immediately after power-on is input to the gate of Q ₅ . This is particularly effective in preventing the potential difference from occurring when the load time constants of V _L1 and V _L2 are greatly different. Even when all of Q ₁ , Q ₂ , and Q ₅ are non-conductive, MOSFET Q ₄ having a relatively small conductance is conductive. This serves for example to make V _L1 = V _L2 while the memory is in standby.

In the memory array 2, a so-called one-transistor / one-capacitor dynamic memory cell MC _ij comprising a MOSFET Q ₁₂₁ and a capacitor C ₁₂₂ is disposed at the intersection of the word line WL _i and the data line DL _j . Although only two word lines and one pair of data lines are shown in the figure, a large number are actually arranged vertically and horizontally. One end PL (plate) of the capacitor C ₁₂₂ is connected to a direct current. The voltage level is arbitrary, but from the viewpoint of the withstand voltage of the capacitor C ₁₂₂ , 1/2 of the operating voltage of the memory array, that is, V _L1 / 2 is desirable.

The word driver 31 is a circuit that receives the output of the row decoder 32 and drives a selected word line. In this embodiment, the word line voltage is set higher than the operating voltage of the memory array (here, V _L1 = 3.3 V). A so-called word line boosting method is employed. The advantage of this method is that the storage voltage of the memory cell can be increased. Therefore, the voltage V _CH (V _CH > V _L1 ) generated by the word line voltage generation circuit 46 is supplied to the selected word line.

The sense amplifier 33 is a circuit for amplifying a minute signal on the data line, and includes a flip-flop composed of N-channel MOSFETs Q ₁₂₅ and Q ₁₂₆ and a flip-flop composed of P-channel MOSFETs Q ₁₂₇ and Q ₁₂₈ . . The sense amplifier is activated by turning on the MOSFETs Q ₁₃₆ and Q ₁₃₇ by setting φ _S to a high level and / φ _S to a low level.

Data line precharge circuit 34 is a circuit for prior to reading a memory cell sets each data line to a predetermined voltage V _P. By applying the precharge signal φ _P , the MOSFETs Q _{129 to} Q ₁₃₁ are turned on, and the voltage of the data line DL _j / DL _j becomes equal to V _P. The data line precharge voltage V _P may be any voltage, but from the viewpoint of reducing the data line charge / discharge current, it is desirable to set it to ½ of the operating voltage of the memory array, that is, V _L2 / 2.

The data line selection circuit 35 receives the output φ _YS of the column decoder 37 and connects the selected data line pair to the input / output lines I / O and / I / O through the MOSFETs Q ₁₃₂ and Q _133. . In the present embodiment, only one column decoder 37 is arranged at the end, and a so-called multi-division data line method is used in which the output φ _YS is distributed to a plurality of data line selection circuits. This is effective in reducing the area occupied by the column decoder.

In this embodiment, a so-called shared sense / shared I / O method is employed in which the sense amplifier 33, the data line precharge circuit 34, and the data line selection circuit 35 are shared by the left and right memory arrays. This is effective in reducing the occupation area by sharing 33, 34, and 35. Therefore, switch circuits 36L and 36R controlled by switch signals φ _SHL and φ _SHR are provided between the memory array and 33, 34, 35.

The main amplifier 38, data output buffer 39, data input buffer 40, and write circuit 41 are circuits for inputting and outputting data. In the case of reading, the data latched in the sense amplifier 33 is output to the data output terminal Dont via the input / output line, the main amplifier 38, and the data output buffer 39. In the case of writing, data input from the data input terminal Din is set to the input / output line via the data input buffer 40 and the write circuit 41, and further written to the memory cell via the data line selection circuit 35 and the data line. In this embodiment, as described above, 38, 40, and 41 are operated by the internal power supply voltage V _L2 to reduce power consumption and stabilize the operation. Only the data output buffer 39 is operated at the external power supply voltage V _CC (= 5 V) for the convenience of an external interface (here, TTL compatible).

The row address buffer 42 and the column address buffer 43 are circuits that receive the external address signal A and supply address signals to the row decoder 32 and the column decoder 37, respectively. The timing generation circuit 44 is a circuit that receives external control signals / RAS, / CAS, / WE and generates timing signals necessary for the operation of the memory. These circuits are also operated at V _L2 with the internal power supply voltage to reduce power consumption and stabilize the operation.

The word line voltage generation circuit 46 is a circuit that generates the word line voltage V _CH (about 5 V here) as described above (this voltage is also used in the switch circuit as described later). The data line precharge voltage generation circuit 47 is a circuit that generates the data line precharge voltage V _P ) (here, 1.65 V). The substrate voltage generation circuit 48 is a circuit that generates a voltage V _BB (here, −2 V) to be applied to the semiconductor substrate. The power supply for these circuits is not V _CC but the stabilized V _L1 or V _L2 . Therefore, there is an advantage that even if V _CC changes, the fluctuation of the output voltage is small.

  Next, the operation in the case of reading from the DRAM will be described with reference to the operation waveform diagram of FIG.

In a standby state (both / RAS and / CAS are high), both the data line precharge signal φ _P and the switch signals φ _SHL and φ _SHR are at a high level (= V _L2 ), and the data lines DL and / DL are _VP is set. The sense amplifier drive signals φ _SAN and φ _SAP and the input / output lines I / O and / I / O are also precharged to V _P (these precharge circuits are not shown in FIG. 13). In this state, only φ ₃ ′ of the voltage limiter drive circuit activation signal is at the high level (= V _CC ), and φ ₁ ′ and φ ₂ ′ are at the low level. Therefore, only the standby driving circuit 7c with low power consumption is activated, and thereby the level of the internal power supply voltage V _L2 is maintained. Further, the level of V _L1 is also held through the connection circuit 15. 7a and 7b which have a large current driving capability but a large power consumption are inactive. By so doing, power consumption during standby can be reduced.

When / RAS goes low, the peripheral circuit drive circuit activation signal φ ₂ ′ goes high (= V _CC ). As a result, 7b having a large current driving capability is activated, and a large current can be supplied to a peripheral circuit operating with _VL2 as a power source. The precharge signal φ _P becomes a low level (= 0 V), the selected memory array side switch signal (φ _{SHL in} the case of FIG. 23) is boosted to the V _CH level, and the opposite side switch signal (FIG. 23). In this case, φ _SHR ) becomes 0V. The reason for boosting _φSHL is as follows. The voltage amplitude of the sense amplifier is V _L1 as described below, the level of phi _SHL is at V _L2, the voltage amplitude of the data line is lowered to V _L2 -V _TN, also the accumulation and the resulting voltage memory cell The voltage drops to V _L2 −V _TN (V _TN is the threshold voltage of the N-channel MOSFETs Q ₁₂₃ and Q ₁₂₄ ). This can be prevented by boosting _φSHL, and the storage voltage of the memory cell can be secured.

Next, when the row address buffer 42 and the row decoder 32 operate, one word line WL _i is selected and its voltage becomes V _CH . A signal charge is read from each memory cell on WL _i to each data line, and the potential of the data line changes. The operation waveform of FIG. 18 is an example in the case where a high potential (≈V _L1 ) is stored in advance in the capacitor of the memory cell, and the potential of the data line DL _j slightly rises between / DL _j. A potential difference is generated.

Prior to the operation of the sense amplifier, the drive circuit activation signal φ ₁ ′ for the memory array becomes high level (= V _CC ). Thus, the drive circuit 7a is activated, it becomes possible to supply a large current to the sense amplifier driving signal generating circuit 45 which operates the V _L1 as the power source. Next, φ _S becomes a high level (= V _L2 ), and / φ _S becomes a low level (= 0 V). As a result, the MOSFETs Q ₁₃₆ and Q ₁₃₇ become conductive, φ _SAN is grounded through Q ₁₃₆ , and φ _SAP is connected to V _L1 through Q ₁₃₇ . Thereby, a minute potential difference between the data lines DL _j / DL _j is amplified, and one (DL _{j in} the case of FIG. 23) becomes V _L1 and the other (/ DL _{j in} FIG. 23) becomes 0V.

When / CAS goes low, the column address buffer 43 and the column decoder 37 operate to select one data line. As a result, the data line selection signal φ _YS becomes a high level (= V _L2 ), and the data lines are connected to the input / output lines through the data line selection circuit 35. The data latched in the sense amplifier 33 is output to the data output terminal Dont via the input / output lines, the main amplifier 38, and the data output buffer 39.

When / RAS returns to a high level, the word line WL _i first goes to a low level, and φ _S , / φ _S , φ _SHL , φ _SHR , and φ _P return to their original levels. The drive circuit activation signal φ ₁ ′ for the memory array becomes low level (= 0V) here, and the drive circuit 7a is deactivated. Further, when / CAS returns to the high level, the drive circuit activation signal φ ₂ ′ for the peripheral circuit also becomes the low level (= 0V), and the drive circuit 7b becomes inactive.

As is clear from the above description, the activation signals φ ₁ ′ and φ ₂ ′ of the drive circuit are at a high level only when necessary. That, phi ₁ 'until the operation immediately before the start of the sense amplifier / RAS is returned to a high level, phi _2' when the the / RAS or / CAS is at a low level, respectively to a high level. Thereby, reduction of the electric power consumed by drive circuit 7a, 7b is realizable.

  As described above, according to the present embodiment, a reference voltage generation circuit based on a threshold voltage difference between enhancement type FETs can be formed without using a depletion type FET. Since it is easier to match the characteristics of enhancement-type FETs than to match the characteristics of depletion-type and enhancement-type FETs, a reference voltage that is more stable than the conventional one can be obtained. Therefore, for example, when applied to the voltage limiter of the memory LSI described above, a more stable internal power supply voltage can be generated.

[Second group]
Embodiments of the second group of the present invention will be described below with reference to the drawings. In the following description, an example in which the present invention is mainly applied to a semiconductor device using MOS technology is shown, but the present invention can also be applied to other semiconductor devices, for example, semiconductor devices using bipolar or BiCMOS technology. Although the case where the external power supply voltage and the internal power supply voltage are positive will be described, the present invention can be applied by reversing the polarity of the transistor even when the external power supply voltage and the internal power supply voltage are negative.

  First, the basic concept of the second group will be described.

FIG. 24 shows this embodiment. In the figure, VL is a voltage limiter circuit, which generates internal power supply voltages V _{L1 to} V _L3 (hereinafter described as V _Li (i = 1, 2, 3)) from the external power supply voltage V _CC . The voltage limiter circuit VL includes a reference voltage generation circuit VR and drive circuits B _{1 to} B ₃ (hereinafter described as B _i (i = 1, 2, 3)). The reference voltage generation circuit VR generates a stable voltage V _R with little fluctuation due to the external power supply voltage V _CC and temperature, and each drive circuit B _i (B _{1 to} B ₃ ) has a current drive capability based on V _R. A large voltage V _L1 is generated. Each drive circuit B _i includes a feedback amplifier A _i and a phase compensation circuit C _i (i = 1, 2, 3). Z _{1 to} Z ₃ are circuits in the semiconductor device serving as a load of the voltage limiter circuit VL, and operate using V _{L1 to} V _L3 as power sources, respectively. φ _{1 to} φ ₃ are timing signals for controlling the load circuits Z _{1 to} Z ₃ , respectively. φ ₁ '~φ _3' is a timing signal synchronized with phi ₁ to [phi] _3, respectively.

The first feature of the present embodiment is that the internal circuit serving as a load of the voltage limiter circuit is divided into three parts Z _{1 to} Z ₃ , and the drive circuit in the voltage limiter circuit is also divided into three parts B _{1 to} B _{3 accordingly} . It is divided into pieces and each phase-compensated. In general, circuits in a semiconductor device include a wide variety of circuits such as capacitors, resistors, inductances, nonlinear elements, or combinations thereof. Moreover, they exist dispersedly on the semiconductor chip (that is, in a distributed constant manner). Phase compensation for stable operation of a feedback amplifier having such a complicated load is extremely difficult. If the load circuit is divided into a plurality of types and sizes as in this embodiment, the design of the feedback amplifier and the phase compensation circuit suitable for each load circuit becomes relatively easy. Thereby, the operation of each drive circuit can be stabilized.

As a method for dividing the load circuit, for example, the following method can be considered.
[1] A method of dividing into a resistive load and a capacitive load.
[2] A method of dividing by load size (current consumption).
[3] A method of dividing according to the operation timing of the circuit.
[4] A method of dividing a circuit according to a physical position in a semiconductor chip.

When divided according to physical positions, it is desirable to disperse the drive circuits B _{1 to} B ₃ as necessary.

The second feature of this embodiment is that a signal φ _i ′ synchronized with a timing signal φ _i for controlling each load is input to each drive circuit B _i . In general, a current flowing through a circuit in a semiconductor device varies greatly depending on an operation mode. This means that the load impedance changes from the power source side. In this embodiment, the timing signal φ _i ′ is used to cope with such load fluctuations. The circuit constants of the feedback amplifier A _i and the phase compensation circuit C _i can be changed by φ _i ′, so that the characteristic always adapted to the operation mode of the load can be obtained. Thereby, the operation of the drive circuit can always be stabilized.

In this embodiment, the levels of the operating voltages V _{L1 to} V _L3 of the load circuits Z _{1 to} Z ₃ are all equal. Therefore, the reference voltage generating circuit is only one provided, and commonly use the output V _R by the drive circuit B ₁ .about.B _3. If the operating voltage varies depending on the load circuit, a plurality of reference voltage generating circuits may be provided as shown in FIG. Alternatively, only one reference voltage generation circuit may be provided, and a voltage conversion mechanism may be provided in the drive circuits B _{1 to} B ₃ .

FIG. 26 shows another embodiment of the present invention. A feature of the present embodiment is that a plurality (two in this case) of drive circuits are provided corresponding to the operation mode of the load circuit Z ₁ and their outputs are switched by switches. Each of the drive circuits B ₁₁ and B ₁₂ is supplied with a timing signal φ _i ′ synchronized with the operation of Z ₁ and its complementary signal / φ _i ′. One of the outputs V _L11 and V _L12 of B ₁₁ and B ₁₂ is selected by the switch SW and supplied to the load Z ₁ . When φ ₁ ′ is high and φ ₁ ′ is low, B ₁₁ is activated and B ₁₂ is deactivated, and the switch SW is connected to the V _L11 side. Conversely, when φ ₁ ′ is at a low level and / φ ₁ ′ is at a high level, B ₁₁ is deactivated, B ₁₂ is activated, and the switch SW is connected to the V _L12 side. That is, only one of the two drive circuits B ₁₁ and B ₁₂ is used to supply the internal power supply voltage V _L1 to the load circuit Z ₁ , and the other is disconnected.

In the embodiment of FIG. 24, a method of changing the circuit constants of the drive circuit is adopted in order to cope with the load fluctuation. However, the impedance of the load varies greatly depending on the operation mode, and it may be difficult to stably operate in a plurality of operation modes by simply changing the circuit constant. In such a case, the method of this embodiment is effective. This is because each drive circuit may be designed exclusively for one operation mode. For example, it is assumed that there is a very large change in current consumption between when Z ₁ is in an operating state and when it is in a standby state. In this case, the driving circuit B ₁₁ when the Z ₁ is in operation, B ₁₂ is to operate stably respectively when Z ₁ is in the standby state, Oke design the feedback amplifier and phase compensation circuit That's fine.

  In this embodiment, the drive circuit that is not used is deactivated, but this is not always necessary. This is because the drive circuit that is not used is separated by a switch. However, in order to reduce power consumption, it is desirable to leave it in an inactive state. Further, the output of the drive circuit is switched by a switch. However, if the output is designed to have a high impedance when the drive circuit is in an inactive state, the switch is not necessary.

In the embodiment of FIG. 24, since the drive circuit is divided, there is a concern that a potential difference may occur between the internal power supply voltages V _{L1 to} V _L3 . If the potential difference between the internal power supply voltages is large, a mismatch may occur or the element may be destroyed when signals are exchanged between the load circuits Z _{1 to} Z ₃ . FIG. 27 shows one method for preventing this. For simplicity, the case where the load and the drive circuit are divided into two parts is shown. In this embodiment, two internal power supply voltages are connected by _two N-channel MOS transistors Q ₁ and Q ₂ . Assuming that the threshold voltage of the MOS transistor is V _TH , Q ₁ becomes conductive when V _L1 −V _L2 > V _TH , and Q ₂ becomes conductive when V _L2 −V _L1 > V _TH . Therefore, the potential difference between V _L1 and V _L2 is kept within V _TH .

The method of connecting internal power supply voltages is not limited to that shown in FIG. 28A to 28E show some examples. The simplest method is a method of connection by a resistor or an element that can be regarded as a resistor equivalently, as shown in FIGS. FIG. 4D is a method for preventing the potential difference between the internal power supply voltages from exceeding a certain value, as in FIG. Here, diodes D ₁ and D ₂ are used in place of the MOS transistors. The potential difference between V _L1 and V _L2 is suppressed within the on-voltage of the diode. FIG. 5E shows a method of connecting V _L1 and V _L2 using a signal WK that becomes a high level only immediately after the power is turned on. This is particularly effective in preventing the potential difference from occurring when the rise time constants of the loads V _L1 and V _L2 are greatly different. Of course, a connection method combining some of FIGS. 27 and 28A to 28E may be adopted.

  The connection method described here is also effective for a voltage limiter that is not subjected to phase compensation.

24 to 27, the load circuit is represented by a single impedance Z _i for simplicity. However, the load in an actual semiconductor device is often distributed in the semiconductor chip as shown in FIG. In such a case, feedback may be applied to the amplifier A _i from the middle of the distributed load or from the far end. In the example shown in the figure, feedback is applied to the A ₁ from the near end of the distributed loads Z _{11 to} Z ₁₉ , but to the A ₂ from the center of the loads Z _{21 to} Z ₂₉ and to the A ₃ to the load Z ₃₁ ~ Z ₃₉ are each returning from the far end. The advantage of this is that it is possible to compensate for the reduced portion of the internal power supply voltage due to the impedance of the wiring and to stabilize the operation of the load far from the drive circuit. When feedback is applied in the middle of the distributed load or from the far end, it is desirable to take the input of the phase compensation circuit from the same location.

[Feedback amplifier and phase compensation circuit]
Next, a feedback amplifier and a phase compensation circuit suitable for use in the present invention will be described.

FIG. 30A shows an embodiment of the feedback amplifier Ai and the phase compensation circuit C _i . In the figure, reference numeral 21 denotes a differential amplifier, which comprises MOS transistors Q _{21 to} Q ₂₅ . An output stage 22 comprises MOS transistors Q ₂₆ and Q ₂₇ . Of the two input terminals of the differential amplifier 21, the reference voltage V _R is input to one, and V _L is fed back from the output stage to the other. C _i is a phase compensation circuit, and a resistor R _D and a capacitor C _D are connected in series. FIG. 30B shows a small signal equivalent circuit when this circuit is not fed back. For simplicity, the case where the load is a single capacity _CL is shown. Here, g _m1, g _{m @ 2} each differential amplifier, the transconductance of the output stage, r _1, r _2, respectively differential amplifier, the output resistance of the output stage, C _G is the gate input capacitance (Q ₂₆ of the output stage Capacity).

The frequency characteristics of this circuit will be described with reference to FIGS. 31 (a) and 31 (b). First, the case where phase compensation is not performed will be described. FIG. 31A shows the relationship between frequency and gain when there is no phase compensation circuit. In the figure, a is the gain v _i '/ v _i, b is the output stage 22 gain v _o / v _i', the gain of the c Overall v _o / v _i of the differential amplifier 21. a and b begin to decrease at a rate of 6 dB / oct at frequencies of f ₁ and f ₂ , respectively. here,
f ₁ = 1 / (2πC _G r ₁ ), f ₂ = 1 / (2πC _L r ₂ )
It is. In this example, since f ₁ > f ₂ , the total gain c = V _o / V _i decreases at a rate of 6 dB / oct when the frequency exceeds f ₂ and further decreases at a rate of 12 dB / oct when the frequency exceeds f _1. . These points f ₂ and f ₁ are so-called pole frequencies. As described above, in order for the feedback amplifier to operate stably, the gain at a point (here, f ₁ ) that starts to decrease at 12 dB / oct must be 0 dB or less. As is apparent from the figure, this condition is often not satisfied when f ₁ and f ₂ are relatively close to each other. It is not satisfied in FIG. Therefore, the feedback amplifier can be stabilized by sufficiently separating f ₁ and f ₂ .

Here, when the phase compensation circuit C _i is added, the frequency characteristics are as shown in FIG. That is, the gain of the differential amplifier 21 does not change, but the gain of the output stage is bent at three points P ₂₁ , Z ₂ , and P ₂₂ . P ₂₁ and P ₂₂ are poles, and Z ₂ is a point called zero. The frequency of these points is as follows.

f ₂₁ = 1 / (2π (C _D r ₂ + C _L r ₂ C _D R _D ))
f ₂₂ = (C _D r ₂ + C _L r ₂ C _D R _D ) / (2πC _L C _D r ₂ R _D )
f ₂ = 1 / (2πC _D R _D )
As is apparent from this figure, by setting f ₂ in the vicinity of the pole frequency f ₁ of the differential amplifier, i.e. by the _{C D R D ≒ C G r} 1, bent in the f ₁ of the total gain Disappears. As a result, the total gain decreases at a rate of 6 dB / oct when the frequency exceeds f ₂₁ and further decreases at a rate of 12 dB / oct when it exceeds f ₂₂ . Here, if n is sufficiently large with C _D = nC _G r ₁ / r ₂ and R _D = r ₂ / n, f ₂₁ and f ₂₂ can be sufficiently separated, so that the feedback amplifier is stabilized. Can do.

FIG. 32A shows another embodiment of the feedback amplifier and the phase compensation circuit. In this circuit, by inserting a capacitor C _F between the input and the output of the output stage 22, which performs phase compensation. FIG. 32B shows a small signal equivalent circuit when the feedback of this circuit is not applied, and FIG. 33 shows its frequency characteristic. In this case, the gain of the differential amplifier is bent at three points P ₁₁ , Z ₁ , and P ₁₂ . Also in this case, the feedback amplifier can be stabilized by setting f ₁ ≈f ₂ and sufficiently separating f ₁₁ and f ₁₂ as in the previous embodiment. The feature of this embodiment is that the apparent capacitance increases due to the so-called Miller effect because the phase compensation capacitor _CF is inserted between the input and output of the amplification stage. Therefore, phase compensation can be performed even if the actual capacitance is relatively small, so that the area occupied by the capacitor can be reduced.

Here, a capacitor used in the phase compensation circuit of FIG. 30A or FIG. 32A will be described. These capacitors are required to have a considerably large capacitance (usually several hundred to several thousand pF) and a small voltage dependency. FIG. 34 (a) shows one method for realizing this in a normal CMOS process. In the figure, 101 is a P-type semiconductor substrate, 102 is an N-type well, 103 is an N ⁺ diffusion layer, 104 is SiO ₂ for isolation, 105 is a gate insulating film, and 106 is a gate. The capacitor is formed between the gate 106 and the substrate surface 102a with the gate insulating film 105 interposed therebetween, like a normal MOS capacitor. Since a thin gate insulating film is used as the capacitor insulating film, a large capacitance can be obtained with a relatively small area. However, the difference from a normal MOS capacitor is that the threshold voltage is negative because there is an N well under the gate. This will be described with reference to FIG. The horizontal axis is the voltage applied to the capacitor (the gate side is positive), and the vertical axis is the capacitance. The threshold voltage (flat band voltage) is the applied voltage V ₀ when the capacitance changes greatly, but V ₀ <0. Therefore, as long as a unidirectional voltage is applied so that the gate side becomes positive, the power collection capacity is almost constant. When a bidirectional voltage can be applied, two capacitors shown in FIG. 34 (a) may be used and connected in parallel in opposite directions as shown in FIG. 34 (c).

  The steps necessary to make the capacitor of this embodiment are well formation, isolation region formation, gate insulating film formation, gate formation, diffusion layer formation, and wiring steps, all of which are ordinary CMOS. It is a process included in the process. Therefore, in the case of a semiconductor device manufactured by a CMOS process, it is not necessary to add a special process for manufacturing this capacitor.

  Further, depending on the semiconductor device to which the present invention is applied, a stacked capacitor may be used. For example, DARM using a stacked capacitor as a capacitor of a memory cell. In such a case, the multilayer capacitor may be used as a phase compensation capacitor. Regarding DRAMs using stacked capacitors, IEE, Journal of Solid State Circuits, Vol. 15, No. 4, pages 661 to 666, August 1980 (IEEE Journal) of Solid-State Circuits, Vol. SC-22, No. 3, pp. 661-666, Aug. 1980).

[Reference voltage generator]
Next, a reference voltage generation circuit suitable for use in the voltage limiter circuit according to the present invention will be described. The reference voltage generation circuit described here can of course be used for a voltage limiter circuit that is not subjected to phase compensation. Needless to say, the embodiment described in the group 1 can be applied.

The output voltage V _L of the electric limiter is generated based on the reference voltage V _R. Therefore, the V _L characteristic can be arbitrarily set according to the V _R characteristic. When a voltage limiter circuit is used in a semiconductor device, the dependency of V _{L on} the external power supply voltage V _CC is particularly important, and therefore it is necessary to design with particular attention to the V _CC dependency of V _R. In this regard, characteristic examples according to various purposes and generation methods thereof are described in Japanese Patent Application No. 56-57143, Japanese Patent Application No. 56-168698, Japanese Patent Application No. 57-220083, Japanese Patent Application No. 60-2611213, Japanese Patent Application No. 63. No. 8372, Japanese Patent Application No. 63-125742, US Pat. No. 4,100,347, and the like. Needless to say, these circuits are applicable to the present invention.

24 to 27, the reference voltage V _R is directly input to the drive circuit. However, the voltage obtained by the reference voltage generation circuit is not necessarily an appropriate value as the internal power supply voltage used in the semiconductor device. In this case, voltage conversion is required. In some cases, fine adjustment of the voltage, so-called trimming, may be necessary to compensate for variations in the reference voltage due to the manufacturing process. As a method for voltage conversion and trimming, the method described in the aforementioned US Pat. No. 4,100,347 may be used. Here, a method suitable for a semiconductor device manufactured by a normal MOS process is introduced.

FIG. 35 shows a circuit diagram. In the figure, DA is a differential amplifier, Q _{31 to} Q ₄₃ are P-channel MOS transistors, and F _{1 to} F ₈ are fuses. V _R is the input voltage (output of the reference voltage generation circuit), and V _R ′ is the output voltage (input of the drive circuit). V _R is input to one of the input terminals of DA, and V _R ″ obtained by dividing V _R ′ by MOS transistors Q _{31 to} Q ₄₂ is fed back to the other. If the amplification factor of DA is sufficiently large, For example, the output voltage V _R ′ is given by the following equation.

V _R '= ((R ₁ + R ₂ ) / R ₂ ) · V _R
Here, R ₁ is a resistance value when a circuit composed of Q _{31 to} Q ₃₈ is regarded as equivalently a resistance, and R ₂ is a resistance value when a circuit composed of Q _{39 to} Q ₄₂ is regarded as a resistance equivalently. It is. Since R ₁ and R ₂ are changed by cutting the fuse, V _R ′ can be adjusted.

A specific trimming method will be described with reference to FIG. This figure shows the relationship between the input V _R and the output V _R ′. In the figure, d is a characteristic when the fuse is not cut at all. When the fuses F ₁ , F ₂ , and F ₃ are cut in order, R ₁ increases, so that V _R ′ increases as indicated by c, b, and a. When the fuses F ₄ , F ₅ , and F ₆ are cut in order, R ₂ increases, so that V _R ′ decreases as indicated by e, f, and g. Therefore, first, V _R is observed, and the fuse cutting method may be selected so that V _R ′ is closest to the target value V _R0 ′ by _referring to FIG. Our goal is to V _R is also varied in a wide range, to enter the V _R 'is a range in V _R0 with' ± ΔV _R '. For this purpose, as shown by a broken line in the figure, when a certain trimming method (for example, a) is adopted, when V _R ′ = V _R0 ′ + ΔV _R ′, the adjacent trimming method (for example, b) The circuit constant (channel width / channel length of each MOS transistor) may be selected so that V _R ′ = V _R0 ′ −ΔV _R ′.

FIG. 37 shows another embodiment of the trimming circuit. When lowering the output voltage V _R ′, the fuses F ₄ , F ₅ , and F ₆ may be cut in order as in FIG. The difference from FIG. 35 is in the method of increasing the output voltage V _R ′. In this case, the fuse F ₇ is first cut (circuit constants are selected so that the input / output characteristics are as shown in h in FIG. 36), and then F ₄ , F ₅ , and F ₆ are cut sequentially. Do it. This circuit has an advantage that the number of fuses is smaller than that of the circuit of FIG.

The circuits shown in FIGS. 35 and 37 have an advantage that the occupied area is small when manufactured by a normal MOS process as compared with the circuit described in the above-mentioned US patent. That is, in the circuit described in the US patent, a resistor is used as an element for dividing the output voltage V _R ′, whereas in the circuits of FIGS. 35 and 37, a MOS transistor is used. In order to reduce the current consumption of the circuit, the equivalent resistance of the voltage dividing element must be considerably large (about several hundred kπ). In a normal MOS process, an element having a smaller area and a larger equivalent resistance can be obtained with a MOS transistor than with a resistor. However, when MOS transistors are used, there is a concern that the characteristics of V _R ′ may fluctuate due to fluctuations in the threshold voltage. However, the channel width and channel length of each transistor are sufficiently increased to suppress variations, and back gates This can be solved by connecting the source to the source to avoid the influence of the substrate potential fluctuation and further selecting the method for cutting the fuse in consideration of the variation of the threshold voltage.

  Next, MOS transistors used in the trimming circuit will be described with reference to FIGS. As described above, the back gate of each transistor is preferably connected to each source in order to suppress the influence of substrate potential fluctuation. For example, when the substrate is P-type, a P-channel MOS transistor as shown in FIG. In the case where the substrate is N-type, an N-channel MOS transistor in which all conductivity types are reversed in FIG. Further, as shown in FIG. 38B, by making a double well structure and fixing the potential of the outer well 112 (here, grounded), the substrate potential can be further enhanced.

  Next, the fuse used for the trimming circuit will be described. As the fuse, for example, the same one as used for defect repair of a semiconductor memory, such as polycrystalline silicon, can be used. Therefore, in the case of a semiconductor memory having a defect relieving circuit, it is not necessary to add a special process for making a fuse. The method for cutting the fuse may be a method using laser light or an electrical method. Since the method using laser light does not require a transistor for cutting, there is an advantage that the occupied area can be reduced, and the electric method has an advantage that an expensive laser light irradiation device need not be used. is there.

FIG. 39A shows another embodiment of the conversion circuit from V _R to V _R ′. A difference from the circuit of FIG. 35 or FIG. 37 is that a P-channel MOS transistor Q ₄₈ is added. Thereby, the maximum value of the output voltage V _R ′ is suppressed to V _CC − | V _TP | (V _TP is the threshold voltage of the P-channel MOS transistor). This will be described with reference to FIG. This figure shows the V _CC dependency of V _R and V _R ′. In the circuit of FIG. 35 or FIG. 37, V _R ′ ≈V _CC when V _CC is low. However, the circuit of FIG. 39 (a) is the addition of Q _48, when V _CC is lower V _R '= V _CC - | a, | | V _TP V _TP | amount corresponding lower the.

The advantage of this embodiment is that the voltage stability of the internal power supply voltage V _L is good when V _CC is considerably lower (eg, 3 V) than the normal operating state (eg, 5 V). This will be described with reference to FIG. This figure is an example of the relationship between the power voltage V _L and the current I _L when V _CC is low in the drive circuit of FIG. 30 (a) or FIG. 32 (a). When the circuit of FIG. 35 or FIG. 37 is used to generate V _R ′, when V _CC is low, V _L ≈V _R ′ ≈V _CC , so that the output MOS transistor (FIG. The drain-source voltage in a) or Q ₂₆ ) of FIG. 32A is almost zero, and the current driving capability is small. Therefore, when the output current (load consumption current) I _L increases, V _L decreases. On the other hand, when the circuit of FIG. 39A is used to generate V _R ′, V _L ≈V _R ′ ≈V _CC − | V _TP |, so that the output MOS transistor of the drive circuit The drain-source voltage is approximately equal to | V _TP | (0.5 V in this example). Therefore, the current drive capability is relatively large and the amount of decrease in V _L is small. That is, by setting _VL slightly lower in advance, the operation of the circuit in the semiconductor device that operates the amount of voltage fluctuation is more stable when V _CC is low, and the operation margin with respect to V _CC is increased.

Note that the circuit Q ₄₈ in FIG. 39 (a) also has the structure shown in FIGS. 38 (a) and 38 (b) in order to suppress the influence of substrate potential fluctuations, like the MOS transistor in the trimming circuit described above. desirable.

[In-chip placement / wiring]
Then, when implementing the present invention in actual semiconductor chip, circuit layout method, and describes how to wire the reference voltage V _R and the internal power supply voltage VL. Here, a DRAM is taken as an example of a semiconductor device to which the present invention is applied, but the present invention is naturally applicable to other semiconductor devices. The arrangement / wiring method described here is also effective for a voltage limiter circuit that is not subjected to phase compensation.

FIG. 40 shows an example of a desirable circuit arrangement and wiring when the voltage limiter circuit is applied to a DRAM. In the figure, 1 is a semiconductor chip, 2a and 2b are memory arrays formed of fine MOS transistors, and 3a, 3b and 3c are peripheral circuits. 4 and 5 are ground V _GND and a bonding pad for the external power supply voltage V _CC , 6 is a reference voltage generating circuit, and 7a, 7b, 7c and 7d are drive circuits. 6 and 7a to 7d constitute a voltage limiter circuit. 7a, 7b and 7c generate internal power supply voltages V _L1 , V _L2 and V _L3 for driving the peripheral circuits 3a, 3b and 3c, respectively. 7d generates an internal power supply voltage V _L4 for driving the memory arrays 2a and 2b.

The feature of this embodiment is that the reference voltage generation circuit 6 and the drive circuits 7a to 7d are separated, the reference voltage generation circuit is arranged in the vicinity of the ground potential input bonding pad, and the drive circuit is arranged in the vicinity of each load circuit. That is. Therefore, the ground wiring 8 from the ground potential input bonding pad to the reference voltage generation circuit and the internal power supply voltage wirings 11a to 11d from each drive circuit to each load circuit are shortened, and their impedances are reduced. Thus, the noise on the wire 8 is reduced, the ground level of the reference voltage generating circuit is stabilized, stable reference voltage V _R is obtained. Further, since the voltage drop of the internal power supply voltages V _{L1 to} V _L4 due to the impedance of the wirings 11a to 11d is reduced, the levels of V _{L1 to} V _L4 are stabilized, and the operation of the load circuit is stabilized.

Another feature of this embodiment is the ground wiring method. First, a dedicated short wiring 8 is provided for the reference voltage generation circuit. For other circuits, wirings 9a to 9d are provided. That is, each drive circuit and its load circuit are wired with a common line, but are separated from other drive circuits and load circuits. The advantage of this wiring system is that it is possible to prevent noise generated on the ground wiring due to the current flowing when each circuit operates from adversely affecting other circuits. In particular, if noise occurs in the ground wiring of the reference voltage generation circuit, the levels of all internal power supply voltages V _{L1 to} V _L4 will fluctuate, so only the ground wiring for the reference voltage generation circuit must be separated from other ground wirings. It is desirable to keep it. Also, it is desirable to separate the ground wiring for the memory array from other ground wiring. This is because, in a DRAM, when a sense amplifier performs an amplification operation, a large number of data lines (whose capacity is usually several thousand pF) are charged and discharged simultaneously, and a large noise is generated in the ground wiring.

FIG. 41 shows another embodiment of circuit arrangement and wiring. In this embodiment, the peripheral circuit 3 is concentrated in the center of the chip, and the bonding pads 4 and 5 for grounding and external power supply voltage V _CC are also disposed in the center of the chip. Also in this embodiment, the reference voltage generating circuit 6 is disposed in the vicinity of the ground potential input bonding pad, and the drive circuits 7a and 7d are disposed in the vicinity of the respective load circuits.

The advantage of this embodiment is that the wiring length is shortened, as is apparent from FIG. Thereby, it becomes strong against the fluctuation of the external power supply voltage V _{CC and} the fluctuation of the current flowing through the load circuit. That is, in the previous embodiment, since the wiring 10 between the V _CC bonding pad and each drive circuit is long, the impedance thereof is large, and the level of V _CC decreases due to the consumption current of the load circuit. Of course, this decrease is absorbed by each drive circuit. However, if the decrease is too large, it cannot be absorbed and the level of the internal power supply voltage _VL may be decreased. On the other hand, in the present embodiment, since the impedance of the V _CC wiring 10 is small, a large load current can be passed. It is also strong against the drop in V _CC .

In FIG. 40 or 41, the ground wiring noise is particularly problematic because the reference voltage V _R and the internal power supply voltage V _Li are generated with reference to the ground potential. Conversely, when V _R and V _Li are generated based on the external power supply voltage V _CC , the noise of the V _CC wiring becomes a problem. In this case, the reference voltage generation circuit may be disposed in the vicinity of the V _CC bonding pad, and the V _CC wiring may be separated for each circuit.

In the arrangement / wiring method shown in FIG. 40 or 41, the reference voltage V _R is wired from the reference voltage generation circuit to each drive circuit, but it is desirable to shield this wiring 12. V _R receives noise from other circuits in the semiconductor chip in order to prevent the variation. An example of a shielding method that can be realized by a normal semiconductor manufacturing process will be described below.

FIGS. 42A and 42B are a plan view and a cross-sectional view, respectively, of one embodiment of the shielded wiring. In the figure, 101 is a semiconductor substrate, 104 is SiO ₂ , 108 is a first wiring layer, 109a, 109b and 109c are second wiring layers, 113 and 114 are interlayer insulating films, and 115 is a protective film. Reference numeral 109b _denotes a reference voltage V _R wiring. The surroundings 108, 109, and 109c are wiring for shielding, and are fixed to a constant potential (here, ground). By providing 108 below 109b, noise due to capacitive coupling with the substrate 101 can be prevented, and by providing 109a and 109c on the left and right, noise due to capacitive coupling with adjacent wiring (not shown) can be prevented. FIGS. 42C and 42D show another embodiment of the shielded wiring. In this embodiment, V _R is wired by the first wiring layer 108b, and left and right (108a, 108).
c) Shield wirings are provided on the lower side (106) and the upper side (109), respectively. By providing the shield wiring also on the upper side, noise due to capacitive coupling through the upper space can be prevented, and the shield becomes more effective.

Further, as shown in FIGS. 61A and 61B, if the contact holes 116a and 116c and the through holes 117a and 117c are provided and the shield wirings are connected to each other, the shield is completed. 61 (c) and 61 (d) show other embodiments of the shielded wiring. In this embodiment, the polycrystalline silicon layer 106 is a V _R wiring. A well 112 is formed below the well 112 and connected to the upper first wiring layer 108 through P-type diffusion layers 107a and 107c and contact holes 116a and 116c. That is, the periphery of 106 is shielded by surrounding it with 112, 107a, 116a, 108, 116c, and 107c. The advantage of this embodiment is that since the second wiring layer is not used for the shield, it can be used for other purposes as indicated by 109 in FIG. 61 (c). This is effective, for example, for use in a portion where the V _R wiring intersects with another wiring.

Note that the shield as described above causes a parasitic capacitance between V _R and the ground, but this has a preferable effect. This parasitic capacitance reduces the impedance to the high frequency of V _R wiring, thereby bypassing the high frequency noise, because acts as a so-called decoupling capacitor. If the capacitance is insufficient as a decoupling capacitor with only a shielded wire, it is of course possible to load with a capacitor separately.

In the above example, the potential for fixing the shield line is the ground potential. However, it may not necessarily be the ground potential as long as it is a stable potential. However, the ground potential is the simplest and is desirable because the parasitic capacitance acts as a decoupling capacitor as described above. In particular, connection to the ground wiring for the reference voltage generation circuit (portion 8 shown in FIGS. 40 and 41) may mean that noise generated by the operation of other circuits is avoided. If V _{R is} generated on the basis of the V _CC as described above, the shield line is better to fix the V _CC.

FIG. 43 shows another embodiment of circuit arrangement and wiring. In the figure, 1 is a semiconductor memory chip, 3 is a peripheral circuit, 7a, 7b and 7c are drive circuits for generating an internal power supply voltage _VL , and 14a, 14b, 14c and 14d are voltages using the output of the drive circuit as a power supply. Pulse generation circuits 2a, 2b, 2c, and 2d for generating pulses φ _P1 , φ _P2 , φ _P3 , and φ _P4 having amplitude V _L are fine MOS transistors that operate by φ _P1 , φ _P2 , φ _P3 , and φ _P4 , respectively. This is the memory array used. Here, the reference voltage generation circuit is not shown. FIG. 44 shows the operation timing of these circuits.

A single external power supply voltage V _CC (for example, 5 V) is applied to the semiconductor memory chip 1 of this embodiment. Driving circuit 7a, 7b, the internal power supply voltage VL is lowered from V _CC (e.g. 3V) is output from 7c, the pulse generating circuit 14a, 14b, 14c, are input to 14d. Then, the timing pulse phi _T shown in FIG. 44 to the pulse generation circuit, an address signal a _i and reverse phase / a _i is inputted.

Peripheral circuit 3 receives external address signal A _i and converts internal address signals a _i and / a _i into external control signals (here, row address strobe signal / RAS, column address strobe / CAS, and write enable signal / WE). It generates an internal timing pulse φ _T in response to the. Peripheral circuits do not have much influence on the degree of integration of the chip, so it is not necessary to use fine elements, and due to the convenience of the fly-in interface, the peripheral circuits are operated directly with the external power supply voltage V _CC. It may be operated.

Only the array selected by the address operates as the memory. In this example, when a _i = "0" (/ a _i = "1"), arrays 2a and 2c are selected (2b and 2d are not selected), and a _i = "1" (/ a _i = "0") ), The arrays 2b and 2d are selected (2a and 2c are not selected). Therefore, only the pulse for the selected array is output. That is, as shown in FIG. 44, a _i = the time of "0", the pulse generation circuit 14a and 14c is a timing pulse phi _T phi _P1, the output of the phi _P3 array 2a and 2c, a reversed _i When “1”, the pulse generation circuits 14b and 14d output φ _P2 and φ _P4 in response to the timing pulse φ _T to operate the arrays 2b and 2d.

  The feature of this embodiment is that each drive circuit is arranged close to each pulse generation circuit, and the pulse generation circuits 14b and 14c share the drive circuit 7b. Therefore, the wiring is shorter than that in FIG. 3, the impedance of the wiring is reduced, and the level of noise generated thereby can be suppressed. Further, the number of drive circuits is reduced by one as compared with FIG. 4, thereby realizing reduction of the chip occupation area and power consumption. In addition, since the pulse generation circuits 14b and 14c do not operate simultaneously, the drive circuit 7b only needs to drive one pulse generation circuit, and it is not necessary to double the current drive capability.

The pulse generation circuits 14a to 14d can be realized by the circuits shown in FIGS. 45 (a) and 45 (b), for example. In FIG. 45A, reference numeral 51 denotes a 2-input NAND circuit comprising P channel MOS transistors Q ₅₁ and Q ₅₂ and N channel MOS transistors Q ₅₃ and Q ₅₄ . The power source of this circuit is V _CC , and the input is a timing pulse and an address signal a _i (or / a _i ). 52 is an inverter composed of a P-channel MOS transistor Q ₅₅ and an N-channel MOS transistor Q _56, the power source is a V _L. When φ _T is input when a _i is “1” (potential V _CC ), a pulse φ _P having the amplitude of the internal power supply V _L is input. Here, the NAND circuit is operated with the external power supply voltage V _CC , but may be operated with the internal power supply voltage V _L.

FIG. 46 is an example in which the number of drive circuits is further reduced by one compared to the embodiment of FIG. Address signals a _i and / a _i , timing pulse φ _T , and pulses φ _{P1 to} φ _P4 are the same as those described with reference to FIG.

  In this embodiment, the pulse generation circuits 14a and 14b share the drive circuit 7a, and 14c and 14d share 7b. Therefore, the number of drive circuits is reduced by one as compared with the embodiment of FIG. 43, thereby reducing the chip area and power consumption. Here, as shown in FIG. 44, 14a and 14b, 14c and 14d do not operate simultaneously. Therefore, each of the drive circuits 7a and 7b only needs to drive one pulse generation circuit, and it is not necessary to double the drive capability.

FIG. 47 shows an embodiment in which the present invention is applied when the memory array is divided into eight. In the figure, 1 is a semiconductor chip, 3 is a peripheral circuit, 2a to 2h are memory arrays, 7a and 7b are drive circuits, and 14a to 14h are pulse generation circuits. In this embodiment, two of the eight arrays are selected by the address signals a _i and a _j , and only the selected array operates. That is, when a _i a _j = "00", 2a and 2e, when a _i a _j = "01", 2b and 2f, when a _i a _j = "10", 2c and 2g, a _i a a _{When j} = “11”, 2d and 2h are selected. Thus, only the selected array pulse φ _Pk (k = 1 to 8) is output. That is, as shown in FIG. 48, when the address signal a _{i aj} = “00”, the pulses φ _P1 φ _P5 , and when a _{i aj} = “01”, the pulses φ _P2 and φ _P6 , a _i a _j When φ = “10”, pulses φ _P3 and φ _P7 are output, and when a _{i aj} = “11”, pulses φ _P4 and φ _P are output, respectively. These pulses φ _Pk (k = 1 to 8) are pulses output at the timing of φ _T , and the amplitude thereof is the internal power supply voltage V _L.

  In the present embodiment, two drive circuits 7a and 7b are shared by eight pulse generation circuits for operating the memory array. By doing so, the number of drive circuits can be significantly reduced, and the occupied area and power consumption can be reduced.

[Example of application to DRAM]
Finally, an example in which the present invention is applied to a DRAM will be described. FIG. 49 is a block diagram of a DRAM to which the present invention is applied. In the figure, reference numeral 201 denotes a power supply voltage (V _CC ) supply bonding pad, which is connected to an external power supply. 202 is a differential amplifier, 203 is a supply line for the internally reduced power supply voltage (V _L ), 204 is a driving MOS transistor of a P-channel MOS sense amplifier, 205 is an activation MOS transistor of an N-channel MOS sense amplifier, and 206 is a P-channel MOS sense amplifier, 207 is an N-channel MOS sense amplifier, 208 is a memory cell, 209 is an N-type well portion of a P-channel MOS sense amplifier, 210 is a memory block including a cell array portion and a sense amplifier portion, 211 is an X decoder, and 212 is A Y decoder, 213 is a short precharge signal line, and 214 is a power supply line V _L / 2. The power supply voltage V _CC is used in peripheral circuits such as an X decoder, a Y decoder, gate protection, and a signal generation circuit. In this embodiment, the internally lowered power supply voltage V _L is used for the back gate (well) of the P-channel MOS transistor connected to the sense amplifier driving MOS transistor 204 and a part of the Y decoder.

In the case of a so-called CMOS circuit such as a sense amplifier, when a P-type substrate is used, a P-channel MOS transistor is usually formed in an N-type well. In this case, as shown in the cross-sectional view of FIG. 50, the potential of the N well (back gate of the P-channel MOS transistor) is not the external power supply voltage V _CC but the operating voltage (in this case, V _L ) supplied to its source. Is desirable. The reason for this will be described next.

For example, if V _CC = 5V and V _L1 = 3V, the data line precharge level is 1.5V. Therefore, before starting the sense amplifier, the P-channel MOS transistor is applied with a back gate bias of 1.5V. It becomes 0V. Referring to FIG. 6, the threshold voltage (absolute value) before activation of the sense amplifier is about 0.86V, and after activation, it is about 0.57V. If the N-well voltage is V _CC (= 5V), they are 1.1V and 0.92V, respectively. This is too large compared to the case of V _L1 . FIG. 51 is a diagram in which the operating speed of the sense system of the DRAM is plotted against the threshold voltage of the P-channel MOS transistor. As can be seen from the figure, the increase in the threshold voltage of 0.1 V corresponds to a delay of about 2 ns. In this case, the N-well voltage is set to V _L1 (= 3 V), thereby realizing a speed increase of about 5 ns or more. I understand that I can do it. Since the CMOS LSI in the ultra-high integration era tends to lower the operating voltage and increase the substrate (well) concentration (back gate bias effect becomes larger), the effect of the present invention becomes more important.

Here, when making the N-well voltage equal to the internal power supply voltage V _L supplied to the P-channel MOS transistor, there is a concern about fluctuations in the N-well voltage due to capacitive coupling or the like. In the embodiment shown in FIG. 49, since the data line is precharged to V _L / 2, when the P-channel MOS transistor operates, the drain voltage rises and forms a pair. Noise is very small. Therefore, problems such as latch-up due to fluctuations in the N well voltage do not occur.

  The sense amplifier has been described above as an example, but the same technique can be applied to other CMOS circuits. Further, the present invention is not limited to a DRAM, and can be applied to a CMOS LSI having two or more different operating voltages. In the embodiments of the present invention, it is clear that the present invention can be established even if the semiconductor conductivity types and potential relationships are all reversed.

  As described above, according to the present invention, the voltage limiter circuit needs to drive many types of loads, and even if the type and size of the load vary depending on the operation mode, the type of load and the operation mode It is possible to perform optimum phase compensation according to the voltage limiter and to stabilize the operation of the voltage limiter.

  Further, when there are a plurality of load circuits using the internal voltage as a power source in the semiconductor chip, the wiring from each drive circuit to each load circuit can be shortened, so that the noise level can be kept low. Further, since the number of circuits can be reduced without increasing the driving capability of the driving circuit, the occupied area and the power consumption can be reduced.

  In addition, in a CMOS circuit using an internally reduced operating voltage, the circuit speed can be increased by making the voltage of the back gate (well) of the transistor formed in the well equal to the reduced voltage. The high reliability and high speed of the ultra-high integration LSI can be realized together.

[Third group]
The problem with the above technique is that no consideration is given to a method for inspecting the internal voltage from the outside. For example, in the case of a memory LSI having a voltage limiter, if the internal voltage value generated by the voltage limiter deviates from the design value, the operation margin of the internal circuit becomes narrow or malfunctions. However, when the memory LSI is inspected by a memory tester or the like, the above problems cannot be easily confirmed unless the internal voltage value can be known.

  If a pad is provided at the internal voltage terminal and a memory tester is connected to the pad, the internal voltage value can be known from the outside. However, this method has the following problems.

  First, an error occurs in the measured value due to noise received by the wiring from the pad to the memory tester.

  Second, the voltage value may change depending on the input impedance of the memory tester.

  Third, since the memory tester measures analog voltages, it takes longer to measure than to handle digital signals.

  An object of the present embodiment is to solve the above-described problems and provide a semiconductor device in which an internal voltage can be easily inspected from the outside with a memory tester or the like.

  In order to achieve the above object, in this embodiment, means for comparing a voltage designated from the outside with an internal voltage and means for outputting the comparison result are provided.

  By comparing the voltage designated from the outside with the internal voltage and outputting the comparison result, the signal taken out to the outside becomes a digital signal. Therefore, compared to the case of taking out directly from the internal voltage terminal described above, it is less susceptible to noise and the input impedance of the measuring instrument, and it becomes easier to inspect with a memory tester.

  Hereinafter, this embodiment will be described with reference to the drawings. In the following description, an example in which the present invention is applied to a DRAM is shown, but the present invention is not limited to a DRAM but can be applied to other semiconductor devices.

FIG. 52 shows this embodiment. This is a DARM with a voltage limiter. In the figure, 1 is a semiconductor chip, 2 is a DRAM memory array, 3 is a DARM peripheral circuit, 4 is a voltage limiter, 5 is a comparison circuit, 6 is a multiplexer and an output buffer, and 8 is a test enable signal generation circuit. The voltage limiter 4 generates an internal power supply V _L lower than V _CC based on the external power supply V _CC . The peripheral circuit 3 of the DRAM operates with the external power supply V _CC , while the memory array 2 operates with the voltage of the internal power supply V _L.

A method for inspecting the voltage of the internal power supply V _L in this embodiment will be described.

The comparison circuit 5 compares V _L with the comparison voltage V _S. In this embodiment, the terminal for inputting the V _S is the shared data terminal D _in a DRAM, it may be a dedicated terminal, the other terminal, for example may also be combined with one address pin. The output C of the comparison circuit is output via the multiplexer and the output buffer 6. In this embodiment, the terminal for outputting the C is an also used as the data output terminal D _out of the DRAM, or a dedicated terminal.

The comparison output C is at a high level when V _L > V _S and is at a low level when V _L <V _S. Therefore, the internal voltage V _L can be known by changing the comparison voltage V _S applied to D _in and observing D _out .

For example, if the external power supply V _CC is
V _CCmin ≦ V _CC ≦ V _CCmax (1)
In the range of, and V _L must be lower than the high V _Lmax than V _Lmin.
In order to check this, first, V _Lmin is applied to D _in to change V _CC from V _CCmin to V _CCmax to confirm that D _out is always at a high level. Next, V _CCmax is applied to D _in and V _CC is _changed from V _CCmin to V _CCmax to confirm that D _out is always at a low level.

It is a feature of the present invention that the signal output from the D _out terminal is a digital signal having a high level or a low level. Therefore, it is possible to avoid errors due to noise and the input impedance of the memory tester, compared to the case of directly outputting the analog voltage, and it is easy to inspect with the memory tester.

The test enable signal TE is a signal indicating whether it is a mode for inspecting _VL or a normal read / write mode. This signal is used to enable the comparison circuit 5 and to switch the multiplexer and output buffer 6. Although a dedicated terminal for inputting TE may be provided, in this embodiment, a circuit 8 for generating TE is provided. This circuit generates TE by a combination of timings when a row address strobe signal (/ RAS), a column address strobe signal (/ CAS), and a write enable signal (/ WE) of the DRAM are applied.

  This will be described with reference to FIGS. 53 (a) and 53 (b).

In the DRAM, in the normal read / write mode, / RAS is applied before / CAS as shown in FIG. As shown in FIG. 53 (b) conversely, / CAS is applied before the / RAS, moreover at that time / W _E was low, circuit 8 is a specified V _L inspection mode And TE is generated. For the method of specifying a special operation mode by combining the timings of / RAS, / CAS, and / WE, see, for example, from ISSC, Digest of Technical Papers, page 18. 19th page, February 1987 (ISSCC Digital of Papers, pp.18-19, Feb.1987) or ISSC, Digest of Technical Papers, page 286 287, February 1987 (ISSCC Digest of Technical Papers, pp. 286-287, Feb. 1987).

Here, a supplementary description will be given of the input / output method of dedicated signals (V _S , C, and TE) used for the inspection of V _L.

As described above, dedicated terminals for these signals may be provided. However, in the embodiment of FIG. 1, the input terminal of V _S is shared with D _in and the output terminal of C is also used with D _out, and TE is made by a combination of timings of / RAS, / CAS, and / WE. The advantage of this method is that _VL can be inspected using only the original terminals of the DRAM. Therefore, not only inspection in a wafer state but also inspection after being assembled into a package is possible.

  An example of the comparison circuit 5 is shown in FIG.

In FIG. 54, reference numeral 20 denotes a differential amplifier having V _L and V _S as inputs and a node 27 as an output, and comprises N channel MOS transistors 21, 22, 23 and P channel MOS transistors 24, 25. Reference numeral 30 denotes an inverter having the node 27 as an input and C as an output, and includes an N-channel MOS transistor 31 and a P-channel MOS transistor 32. When V _L is higher than V _{S, the} node 27 is at a low level and the output C is at a high level. When V _L is lower than V _{S, the} node 27 is at a high level and the output C is at a low level.

As a comparison circuit, a single differential amplifier may be used, but if the output of the differential amplifier is further amplified by an inverter as in this embodiment, the output C level is surely high (≈V _CC ). This is desirable because it can be set to a low level (≈0 V).

In this circuit, since TE is input to the gate of the MOS transistor 21, no current flows through the differential amplifier except in the _VL inspection mode (when TE is at a high level). This prevents an increase in power consumption during normal operation. Further, since the P-channel MOS transistor 26 is conductive during normal operation, the node 27 is fixed at a high level.

  Next, a method for realizing the multiplexer and output buffer 6 used in the present invention will be described.

FIG. 55 shows an example of a multiplexer and an output buffer. In FIG. 55, 41, 42, and 49 to 52 are inverters, 43 to 48 are NAMD gates, and 53 and 54 are N channel MOS transistors. This circuit is a circuit that selects one of the data output d _out of the DRAM and the output C of the comparison circuit and outputs it to the output terminal D _out . Which one is selected is determined by TE (the above-described test enable signal) and OE (DRAM output enable signal). When TE is high and OE is low (in _VL inspection mode), C is selected, and when TE is low and OE is high (in read mode), _dout is selected and output. The When both TE and OE are at a low level (in the write mode or standby state), the output terminal _Dout has a high impedance.

FIG. 56 shows another embodiment of the present invention. The difference from the previous embodiment is that two voltages V _S1 and V _S2 are input as comparison voltages, and two comparison circuits 5-1 and 5-2 are provided.

The comparison circuit 5-1 compares the internal voltages V _L and V _S1 , and 5-2 compares V _L and V _S2 . Comparison output C ₁ may, when the V _L> V _S1 is at high level, V _L> V _S2 goes low. Comparison output C ₂ may, when the V _L> V _S2 goes high when the low level, V _L <V _S2. The signal C output to the outside is the result of logical product of C ₁ and C ₂ by the AND gate 9.

In this embodiment, the data input terminal and the output terminal are shared and 4 bits are read / written simultaneously. This is a so-called x4 bit DRAM. Therefore, three of the four data input / output terminals I / O _{0 to} I / O ₃ are used for inputting the comparison voltages V _S1 and V _S2 and outputting the comparison result C. In the case of the × 1 bit configuration DRAM as in the previous embodiment, for example, D _out may be used for C output, and D _in or two of the address terminals may be used for V _S1 and V _S2 inputs.

The advantage of the present embodiment is that it can be determined by a single inspection whether or not _VL is within a certain range. For example, suppose that V _L must be higher than V _Lmin and lower than V _Lmax . In order to check this, V _S1 = V _Lmin and V _S2 = V _Lmax may be set. Only when V _Lmin <V _L <V _Lmax , C is at a high level.

  FIG. 57 shows another embodiment of the present invention.

The difference from the above-described two embodiments is that the comparison voltage V _S is designated by a digital signal, and the comparison voltage V _S is generated by the DAC by DA conversion. In this embodiment, the input terminals for the digital signals S _{0 to} S ₃ are also used as the address terminal A _i .

The input digital signal is converted into an analog voltage V _S by the DA converter 10. Reference voltage applied to the DA converter may be any V _CC, who dedicated voltage V _R is desirable. This is because the V _CC dependency of the internal voltage V _L can be measured. In this embodiment, the V _R input terminal is also used as the data input terminal D _in of the DRAM.

The feature of this embodiment is that it is not only an output but also an input digital signal. Therefore, the test by the memory tester is further facilitated as compared with the previous embodiment. In this embodiment, there is only one comparison voltage V _S , but it goes without saying that it may be two as in the previous embodiment.

  Next, the DA converter used in this embodiment will be described.

FIG. 58 (a) shows an example of a DA converter. In the figure, 61 and 62 are inverters, and R and 2R are resistors. Here, the power source of the inverter 62 is the reference voltage V _R. When a digital signal is input from the terminals S _{0 to} S ₃ , the output voltage of the inverter 62 becomes V _R or 0 V depending on the input signal. The voltage of the output V _S is
V ₈ = (V _R / 16) · (8S ₃ + 4S ₂ + 2S ₁ + 1S ₀ ) (2)
Given in. However, it is assumed that the output impedance of the inverter 62 is sufficiently smaller than the resistors R and 2R.

FIG. 58B shows another embodiment of the DA converter. In the figure, 71 is a decoder, 72 is a MOS transistor, and R is a resistor. In this circuit, the voltage V _i = (i / 16) · V _r (i = 0 to 15) (i) is obtained by dividing the reference voltage V _R by resistance.
One of them is selected as the output V _S. This selection is performed by signals T _{0 to} T _{15 obtained} by decoding the input signals S _{0 to} S ₃ by the decoder 71. The feature of this circuit is that if the impedance of the load (the input impedance of the comparison circuit 5 in FIG. 57) is sufficiently large (the circuit in FIG. 54 satisfies this condition), the output voltage V _S will be the ON resistance of the MOS transistor 72. It is not affected by.

FIGS. 58A and 58B are 4-bit DA converters. However, it goes without saying that the number of bits may be increased or decreased depending on how accurately the internal voltage _VL needs to be set.

FIG. 59 shows still another embodiment of the present invention. A feature of this embodiment is that the internal voltage V _L is AD-converted and output. Therefore, the register 80 for storing the digital signal S ₀ to S ₃ are provided. Hereinafter, the operation of the present embodiment will be described with reference to the timing chart of FIG.

As in the previous embodiment, the test enable signal TE is generated by the combination of the timings of / RAS, / CAS, and / WE. At this time, the contents of the register 80 are set to a state in which only the most significant bit S ₃ is “1” and others are “0”. At this time, the comparison voltage V _S is equal to V _R / 2. As a result of comparing V _S with the internal voltage V _L , if C = 1, that is, V _L > V _R / 2, the most significant bit S ₃ is kept at “1” and C = 0, that is, V _L <V _{If R} / 2, S ₃ is reset to “0”.

Next, S _{2 of the} register is set to “1”. At this time, the comparison voltage V _S is V _R / 4 or 3V _R / 4. As a result of comparing V _S with the internal voltage V _L , if C = 1, S ₂ is kept at “1” as it is, and if C = 0, S ₂ is reset to “0”. Similarly, S ₁ and S ₀ are sequentially determined.

The above operation is performed in synchronization with the clock. In this embodiment, / CAS is used as a clock. That is, first, / CAS is set to a low level before / RAS to designate the _VL inspection mode. This raises TE to a high level. Next, the AD conversion is performed by raising / lowering / CAS while keeping / RAS at a low level. During this time, since each time the comparison result is sequentially appears at the output terminal D _out,
By observing _Dout , the result of AD conversion can be known.

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Claims (7)

A semiconductor device in which an internal voltage generating circuit that converts an external voltage supplied from an external power supply voltage bonding pad into an internal voltage and an internal circuit that operates using the internal voltage as a power source are formed on a semiconductor substrate of the first conductivity type. Because
The internal voltage generation circuit includes a reference voltage generation circuit that generates a reference voltage, a drive circuit that outputs the internal voltage based on the reference voltage, and a phase compensation circuit that changes a frequency characteristic of the drive circuit. ,
The phase compensation circuit includes a second conductivity type well region formed in the semiconductor substrate, the second conductivity type first region formed in the well region, and an insulating film on the well region. A semiconductor device comprising a capacitor having a layer made of polycrystalline silicon or metal formed in the above manner.   2. The semiconductor device according to claim 1, wherein the driving circuit includes a differential amplifier and an output stage connected to the output thereof.   3. The phase compensation circuit according to claim 1, further comprising a resistor connected in series with the capacitor, wherein the reference voltage and the output of the output stage are input to the differential amplifier. A semiconductor device that is characterized in that:   4. The semiconductor substrate according to claim 1, wherein a plurality of MOSFETs are formed on the semiconductor substrate, the well region is formed in the same manufacturing process as a well region where the MOSFET is formed, and the insulating film is the MOSFET. A semiconductor device characterized in that the layer made of polycrystalline silicon or metal is a common layer with the gate of the MOSFET.   5. The semiconductor device according to claim 1, wherein the first conductivity type is a P-type, and the second conductivity type is an N-type.   6. The semiconductor device according to claim 1, wherein the capacitor is a MOS capacitor having a negative threshold voltage. 7. The semiconductor device according to claim 1, wherein an impurity concentration of the first region is higher than an impurity concentration of the well region.

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