JPH02198096A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a stable semiconductor device having low noise levels by dividing a voltage limiter and a drive circuit to compensate their phases, preparing a pulse generating circuit to use selectively a voltage limiter with a control signal and to integrate the voltage limiter into a CMOS, and setting the back gate voltage at a level equal to the source voltage. CONSTITUTION:An internal circuit serving as a load of a voltage limiter is divided into pieces Z1-Z3 together with a drive circuit divided into pieces B1-B3. The phases of these divided circuits are compensated. A feedback amplifier and a phase compensating circuit which are suited to each load circuit can be easily designed by dividing those circuits according to the types and the sizes of the loads. Thus the working of each drive circuit is stabilized. A pulse phi'1 is inputted to a drive circuit B1 synchronously with a timing pulse phi1 which controls the load. Then the circuit constants of a feedback amplifier A1 and a phase compensating circuit C1 are changed to secure the characteristics which are always accordant with the load action mode. Thus the working of the drive circuit is stabilized. These elements are integrated into a CMOS device on an Si substrate 101, and the voltage of a back gate 102 is set at the same level as the working voltage of a source. Thus it is possible to obtain a small sized DRAM having the low noise levels, the low power consumption, and the high speed working.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a semiconductor device, and more particularly to a circuit that generates an internal power supply voltage used in at least some circuits within the device. (Prior Art) In recent years, as semiconductor devices have become more highly integrated, a decrease in breakdown voltage due to the miniaturization of semiconductor elements has become a problem.This problem can be solved by lowering the power supply voltage of the semiconductor device, but
This is not necessarily preferable due to the external interface. Therefore, the power supply voltage applied externally remains the same as before (
For example, in the case of TTL compatible, a method has been proposed in which the voltage is set at 5 V) and an internal power supply with a lower voltage (for example, 3 V) is created within the semiconductor device. For example, I.E., Journal of Solid State Circuits, Vol. 22, No. 3, No. 437.
From page 441. June 1987 (I E E E Journal
of 5olid-8tats C1rcuits,
Vol, 5C-22, No, 3゜pp, 437-441
．． June 1987) applied this method to DRAM.
(dynamic random access memory) and a circuit for generating internal power from an external power supply (
Voltage limiter circuit) is described. FIG. 29 shows a circuit diagram of the voltage limiter circuit described in the above-mentioned document. In FIG. 29, VL is a voltage limiter circuit, which is composed of a reference voltage generation circuit VR and a drive circuit B. Z is the load of the voltage limiter, i.e. the output voltage of the voltage limiter V
This circuit operates using L as a power source. The reference voltage generation circuit VR generates a stable voltage VR with little variation due to external power supply voltage Vcc or temperature. Drive circuit B has a voltage value of V
Like R, this circuit generates a voltage v with a large current drive capability, and is composed of a differential amplifier DA consisting of Qxos to Q1□1 and an output MOS transistor Q2. One of the two input terminals of the differential amplifier DA is connected to VR.
is connected, and the output VL is fed back to the other, so
This circuit operates so that the output vL follows the input VR. The current drive capability of the output v is determined by the channel width of the output MOS transistor Q L L jA. Therefore, if the channel width of Q and □ is designed to be large enough to match the load's consumption current, stable internal power supply voltage VL can be achieved.
can be supplied to the load. Problems to be Solved by the Invention The first problem with the above-mentioned prior art is that the stability of the operation of the voltage limiter circuit is not taken into account. Generally, an amplifier with feedback such as drive circuit B in FIG. 29 will operate unstable unless it is designed to have sufficient phase margin. This will be explained using FIG. 30. Assuming that the frequency vs. gain and frequency vs. phase relationships of the amplifier without feedback are as shown in the diagram, this is a value that shows how much margin there is for one phase delay to 180° at the frequency where the gain is OdB. is the phase margin. If the phase margin is negative, the feedback amplifier will oscillate, and even if it is positive, if the margin is small, the operation will become unstable. It is generally said that a phase margin of 45" or more is required for stable operation. To do this, the second point P, (slope is 6 dB
/oct to 12 dB/oct) must be less than or equal to OdB. Since the mission of the voltage limiter circuit is to supply a stable internal power supply voltage to the internal circuit, it goes without saying that it must not oscillate or become unstable in operation. As a countermeasure to this problem, various methods of compensating for phase delay are described, for example, in Paul Earl Gray and Lopert G. Meyer, Analysis and Design of Analog Integrated Circuits, 2nd edition, John Wiley & Sons, Inc. (Pa.
ul R, Gray and Robert G, Ma
yer: Analysis and Design
of Analog Integrated C1rc
uits. 2nd Ed, John Wiley and
5ons Inc.). However, there are first-order problems when applying phase compensation to voltage limiter circuits of actual semiconductor devices. The circuit serving as the load of the voltage limiter circuit is an internal circuit of an actual semiconductor device, and includes an extremely wide variety of elements such as capacitance, resistance, inductance, nonlinear elements, and combinations thereof. Moreover, these loads are not constant over time and may change depending on the operating mode of the semiconductor device. For example, the current flowing through the load differs greatly between when the semiconductor device is in an operating state and when it is in a standby state. As a result, the bias condition of the output stage of active circuit B in FIG. 29 changes, and as a result, the frequency characteristics of the entire amplifier also change. In order to operate the voltage limiter circuit stably, it is necessary to ensure that the amplifier with such complex characteristics always operates stably. For this purpose, conventional phase compensation methods alone are insufficient. The second problem with the above-mentioned conventional technology is that no consideration is given to the arrangement and wiring on the semiconductor chip. In particular, when there are a plurality of circuits that operate on the internal power supply voltage VL, no consideration has been given to the arrangement of the voltage limiter circuits or the wiring of the output voltage VL. For example, when the above-mentioned conventional technique is applied to a semiconductor memory, the following problems occur. FIGS. 31 and 32 show an example in which the above-mentioned conventional technology is applied to a semiconductor memory. In FIG. 31, 1 indicates the entire semiconductor memory chip;
3 is a peripheral circuit, 7 is a drive circuit of the voltage limiter circuit (the reference voltage generation circuit of the pressure limiter circuit is omitted here), 14a to 14d are pulse generation circuits, 2a to 2d is a memory mat made up of micro MO8) transistors. Since the memory mat uses minute elements, it is operated with an internal power supply voltage Vt. The drive circuit 7 and pulse generation circuits 14a to 14d are circuits for this purpose. 7 generates an internal power supply voltage VL, and 14a to 14d generate pulses φP and φP4 of amplitude VL, respectively. In this example, there are four pulse generating circuits 14a to 14d, but there is only one immediate action circuit 7. Therefore, in order to supply the internal power supply voltage VL generated by this voltage limiter circuit to each pulse generation circuit, a long wiring from the top side to the bottom side of the chip is required, which increases the parasitic impedance of the wiring and causes noise generation. Cause. If you increase the wiring width to reduce this impedance,
This time, a problem arises in that the area occupied by the wiring on the chip increases. FIG. 32 shows an example in which one drive circuit 7 a s 7 b t 7 c * 7 d is provided corresponding to each pulse generation circuit in order to avoid the problem of the wiring becoming long in FIG. 31. In this way, the wiring length between the voltage limiter circuit and the pulse generation circuit can be shortened, but the same number of voltage limiter circuits as the number of pulse generation circuits (four in this case) are required. Therefore, the area occupied by the voltage limiter circuit on the chip and the current consumption increase compared to the case of FIG. 31. When the number of pulse generation circuits increases, the area occupied by the voltage limiter circuit and the power consumption increase will become a serious problem for semiconductor devices that are aiming for higher integration and lower power consumption. The third problem with the above-mentioned prior art is that the operating speed of the CMO8 circuit is not taken into consideration. This problem can be solved with dynamic random access memory (DRAM), which is manufactured using cutting-edge microfabrication technology.
(abbreviated as )). FIG. 33 shows a part of the circuit block configuration of a conventional N-well type CMO8/DRAM. A part of the memory cell array in FIG. 6 is on a P-type substrate. The sense amplifier section is made up of N-channel and P-channel MOS transistors, and an N-well corresponding to the substrate of the P-channel MOS transistor is connected to a power supply voltage. I Nis Nis Cee, F.N.M.18
．． 6, 1984, p. 282 (ISSCC, FAM1
8.6, 1984, p. 282), the size of MOS transistors can be reduced to improve DR.
As the degree of integration of AM increases, problems such as a decrease in stress resistance voltage due to hot carriers of MOS transistors arise. In order to prevent this, it is conceivable to lower only the power supply voltage used in a memory array that needs to be miniaturized to improve the degree of integration, taking into account the stress withstand voltage. This means, for example, that the external power supply voltage Vcc is applied to the peripheral circuits of the DRAM (X decoder, Y decoder, etc.), and the operating voltage VL (IV
LI<Vccl). That is, the third
The voltage supply line connected to the source of the P-channel MOS transistor of the sense amplifier in FIG. However, in the 0MO8-DRAM, it has been found that when the operating voltage of a portion of the memory array is lowered as described above, the operating speed is significantly reduced. As a result of detailed analysis, it became clear that the cause was an increase in threshold voltage due to the back gate bias effect of the P-channel MOS transistor. That is, if the potential of the source of the P-channel MOS transistor formed in the N-well in the P-type substrate is the internal power supply voltage v, and the potential of the N-well (back gate of the P-channel MOS transistor) is the external power supply voltage Vcc. , a back gate bias of Vcc-VL is applied to the P-channel MOS transistor, and its threshold voltage increases. Figure 34 shows the difference between the back gate (N well) voltage and source voltage (back gate bias) of a P channel MOS transistor with a gate length of 1.2 μm and a gate width of 10 μm.
This is a plot of the threshold voltage. In this example, when the bank gate bias is input by 2■,
The threshold voltage increases by about 0.35VL. For example, VL
= 3 V, the threshold voltage increase of 0.35 V exceeds 10% of the operating voltage, which directly leads to speed deterioration. A first object of the present invention is to solve the above first problem and provide a voltage limiter circuit with stable operation. A second object of the present invention is to solve the second problem described above and provide a voltage limiter circuit with low noise, small occupation area, and low power consumption. A third object of the present invention is to solve the third problem described above and provide a high-speed and highly reliable 0MO8-LSI.

[Means to solve the problem]

In order to achieve the above first object, in the present invention, when the voltage limiter needs to drive many types of loads,
The active circuit that makes up the voltage limiter is divided into multiple parts depending on the type of load, and phase compensation is applied to each part. When the type and magnitude of the load changes over time depending on the operating mode of the semiconductor device, the circuit constants of the drive circuit and phase compensation circuit are changed depending on each operating mode. Alternatively, separate operating circuits are provided for each operation mode, and their outputs are connected to provide the output of the voltage limiter. The second purpose is to place a voltage limiter circuit and a load circuit such as a pulse generation circuit that uses its output as a power source in close proximity to each other, so that the voltage limiter circuit can be selected or
This is achieved by sharing one voltage limiter circuit among a plurality of unselected load circuits. In order to achieve the third object, the present invention provides 0MO8
- In an LSI, the back gate (well) voltage of a MOS transistor formed in a well is made equal to the operating voltage supplied to the source end.

[Effect]

When a voltage limiter needs to drive many types of loads, it is possible to achieve optimal phase compensation according to the type of load by dividing the drive circuit into multiple parts according to the load and applying phase compensation to each. become. In addition, it is possible to change the circuit constants of the drive circuit and phase compensation circuit depending on the operation mode of the semiconductor device, or to provide separate drive circuits for each operation mode and connect their outputs to use as the output of the voltage limiter. This enables optimal phase compensation in response to load fluctuations. This makes it possible to create a voltage limiter circuit with stable operation. By placing the voltage limiter circuit and a load circuit such as a pulse generator circuit that uses its output as a power source in close proximity, the impedance of the wiring between them can be reduced, and the level of noise generated can be suppressed. can. Furthermore, the number of voltage limiter circuits can be reduced by sharing one voltage limiter circuit among a plurality of load circuits that are selected/unselected by a control signal such as an address signal. Therefore, the area occupied by the circuit and the power consumption can be reduced. Here, the voltage limiter circuit only needs to drive the circuit in the selected state among the load circuits. Therefore, there is no need to increase the current drive capability of the voltage limiter circuit by sharing. In 0MO8-LSI, MO formed in the well
By setting the well voltage to the internal power supply voltage VL, the S transistor can prevent the threshold voltage from increasing due to the back gate bias effect. [Example] Hereinafter, the present invention will be described in detail with reference to the drawings. In the following description, an example in which the present invention is applied to a semiconductor device using MO3 technology will be mainly shown, but the present invention can also be applied to other semiconductor devices, such as bipolar or BiCMO8 semiconductor devices. Further, although the case where the external power supply voltage and the internal power supply voltage are positive will be described, the present invention can be applied even when the external power supply voltage and the internal power supply voltage are negative by reversing the polarity of the transistor. [Basic Concept] First, the basic concept of the present invention will be explained. FIG. 1 shows an embodiment of the present invention. In the figure, VL is a voltage limiter circuit, which generates internal power supply voltages VL□ to VL from external power supply voltage Vcc. The voltage limiter circuit VL consists of a reference voltage generation circuit VR and sleep circuits B-B3. The reference voltage generation circuit VR generates a stable voltage VR with little variation due to external power supply voltage Vcc or temperature, and each drive circuit B generates a voltage V with a large current drive capability based on VR.
Generate L t. Each drive circuit B1 includes a feedback amplifier At and a phase compensation circuit CI.
Consists of. Z engineering to Z are circuits in the semiconductor device that serve as loads for the voltage limiter circuit VL, and v11 to v, respectively.
It operates using L3 as a power source. φ1 to φ are timing signals that control the load circuits 20 to Z, respectively. φ
1' to φ3' are timing signals synchronized with φ□ to φ, respectively. The first feature of this embodiment is that the internal circuit that serves as the load of the voltage limiter circuit is constructed by Z-2. Accordingly, the drive circuit in the voltage limiter circuit is also divided into three parts, B1 to B3, and phase compensation is applied to each part. Generally, circuits within a semiconductor device include an extremely wide variety of elements such as capacitance, resistance, inductance, nonlinear elements, or combinations thereof. Moreover, they exist dispersedly (ie, in a distributed constant manner) on the semiconductor chip. Phase compensation for stable operation of a feedback amplifier with such a complex load is extremely difficult. If the load circuit is divided into a plurality of parts according to type and size as in this embodiment, it becomes relatively easy to design a feedback amplifier and a phase compensation circuit suitable for each load circuit. This makes it possible to stabilize the operation of each drive circuit. Examples of ways to divide a load circuit include dividing it into resistive loads and capacitive loads, dividing it according to load size (current consumption), dividing it according to circuit operation timing, and dividing it into a resistive load and a capacitive load. Possible methods include dividing the data according to its physical location. When divided by physical location, it is desirable to distribute the drive circuits B1 to B as necessary. A second feature of this embodiment is that each drive circuit B receives a signal φ,' synchronized with a timing signal φi that controls each load. Generally, the current flowing through a circuit within a semiconductor device varies greatly depending on the operating mode. This means that the impedance of the load changes when viewed from the power supply side. In order to cope with such load fluctuations, this embodiment uses a timing signal φ1'. By changing the circuit constants of the feedback amplifier Ai and the phase compensation circuit C8 by φ1', the characteristics can be always adapted to the operation mode of the load. Thereby, the operation of the drive circuit can always be stabilized. Note that in this embodiment, the operating voltage V of the load circuits z1 to Z
It is assumed that the levels of L□ to VL are all equal. Therefore, only one reference voltage generation circuit is provided, and its output VR
is commonly used in drive circuits B to B1. If the operating voltage differs depending on the load circuit, a plurality of reference voltage generating circuits may be provided as shown in FIG. Alternatively, only one reference voltage generation circuit may be provided, and a voltage conversion mechanism may be provided within the drive circuits B1 to B. FIG. 3 shows another embodiment of the invention. The feature of this embodiment is that the load circuit 2. A plurality of (two in this case) drive circuits are provided corresponding to the operating modes of the drive circuit, and their outputs are switched by a switch. A timing signal φ1'' synchronized with the operation of the Z mechanism and its complementary signal Iφ1' are input to each of the drive circuits B and B.
One of the outputs v, 1, and V L x z is selected by the switch SW and supplied to the load Z. φ1′
When 5/φ1' is at a low level, B81 is activated, B12 is inactivated, switch SW is set to v, and 1
connected to the side. Conversely, when φ□'' is at a low level and tφ,'' is at a high level, Bo is inactivated, B2 is activated, and the switch SW is connected to the V L > 2 side. That is, two drive circuits B1, B1. Only one of them is used to supply the internal power supply voltage VL to the load circuit Z, the other being in a disconnected state. In the embodiment shown in FIG. 1, a method was adopted in which the circuit constants of the drive circuit were changed in order to cope with load fluctuations. However, the impedance of the load varies significantly depending on the operating mode, and it may be difficult to operate stably in multiple operating modes simply by changing circuit constants. The method of this embodiment is effective in such cases. This is because each drive circuit only needs to be designed for one operating mode. For example, suppose that there is a very large change in current consumption between when Z is in an operating state and when it is in a standby state. In this case, the feedback amplifier and phase compensation circuit should be designed so that drive circuits B1 and B12 operate stably when Z is in the operating state, and drive circuit B12 operates stably when Z4 is in the standby state. good. In this embodiment, the drive circuit that is not used is inactivated, but this is not necessarily necessary. This is because the unused drive circuit is disconnected by the switch. However, in order to reduce power consumption, it is preferable to keep it in an inactive state. Further, although the output of the drive circuit is switched by a switch, if the drive circuit is designed so that its output becomes high impedance when it is inactive, the switch is not necessary. In the embodiment shown in FIG. 1, since the drive circuit is divided,
There is a concern that a difference in potential may occur between the internal power supply voltages VL, .about.v. If the potential difference between the internal power supply voltages is large,
When signals are exchanged between the load circuits Z and Z, mismatches may occur or elements may be destroyed. FIG. 4 shows one method for preventing this. For simplicity,
This figure shows a case where the load and drive circuit are divided into two parts. In this embodiment, two internal power supply voltages are connected by two N-channel MOS transistors Q1 and Q2. If the threshold voltage of the MOS transistor is VTR, then Q is VLl-VL, > VTH(7),
Q2 is VL2 VLt > VT) + (7) Toi!
! Nisoreso h is conductive. Therefore, VLl and VL2
The potential difference between the internal power supply voltages is maintained within VTH.9 The method of connecting the internal power supply voltages is not limited to that shown in FIG. 4, but some examples are shown in FIG. The simplest method is to connect using a resistor or an element that can equivalently be regarded as a resistor, as shown in (a) to c) of the same figure. Similarly to FIG. 4, FIG. 4(d) shows a method of preventing the potential difference between the internal power supply voltages from exceeding a certain value. Here, a diode D is used instead of a MOS transistor.
0 and B2 are used. The potential difference between Vc and VL is suppressed to within the on-voltage of the diode. Same figure (
e) is a method of connecting 1 and VL2 using a signal WK which becomes high level only immediately after the power is turned on. This is particularly effective in preventing a potential difference from occurring when the rise time constants of the loads VL and VL2 are significantly different. Of course, Figures 4 and 5 (a) to (e)
A connection method that combines some of these methods may also be used. Note that the connection method described here is also effective for voltage limiters that are not subjected to phase compensation. In FIGS. 1 to 4, the load circuit is represented by a single impedance Zl for simplicity. However, in actual semiconductor devices, the load is often distributed within the semiconductor chip, as shown in FIG. In this case, 1
Feedback may be applied to the amplifier A from the middle or far end of the distributed load. In the example in the figure, the distributed load 2 is applied to A□.
Feedback is applied from the near end of the
Returns are applied from the far ends of 31 to ZXS. The advantage of doing so is that it is possible to compensate for a drop in the internal power supply voltage due to the impedance of the wiring, and to stabilize the operation of a load that is far from the drive circuit. When feedback is applied from the middle or far end of a distributed load, it is desirable that the input of the phase compensation circuit is also taken from the same location. [Feedback Amplifier and Phase Compensation Circuit] Next, a feedback amplifier and a phase compensation circuit suitable for use in the present invention will be described. FIG. 7(a) shows an embodiment of the feedback amplifier A and the phase compensation circuit CI. In the figure, 21 is a differential amplifier, which is a MOS
Transistor Q2. ~ Consists of Q□. 22 is an output stage, and MOS transistor 02 G j
It consists of Q x q. Of the two input terminals of the differential amplifier 21, the reference voltage VR is input to one, and the voltage V is fed back from the output stage to the other. Ct is a phase compensation circuit in which a resistor Rn and a capacitor CD are connected in series. A small signal equivalent circuit of this circuit without feedback is shown in FIG. 7(b). For simplicity, the capacity C with a single load
This shows the case where Here, gmxtgmz are the transfer conductance of the differential amplifier and the output stage, r
ll and r are the output resistances of the differential amplifier and output stage, respectively, and Ca is the input capacitance of the output stage (gate capacitance of Q26). The frequency characteristics of this circuit will be explained using FIG. First, the case where no phase compensation is applied will be described. (a) shows the relationship between frequency and gain when there is no phase compensation circuit. In the figure, a is the gain v+'/vt of the differential amplifier 21
, b is the gain Vo/Vt' of the output stage 22, and C is the total gain vo/vs. a and b begin to decrease at a rate of 6 dB10 ct at frequencies f, , f, respectively. Here, . In this example, since fl>ft, the overall gain C decreases at a rate of 6 dB10 ct when the frequency exceeds f3, and 12 dB 10 ct when the frequency further exceeds f2. These points f2 and f8 are so-called pole frequencies. As mentioned above, in order for the feedback amplifier to operate stably,
The gain at the point where it starts to decrease at 12 dB 10 ct (here f) must be O dB or less. As is clear from the figure, when fl and f2 are relatively close,
This condition is often not met. Therefore, f□
By separating f2 and f2 sufficiently, the feedback amplifier can be stabilized. If the phase compensation circuit CI is added here, the frequency characteristics will become as shown in FIG. 2(b). In other words, the gain of the differential amplifier 21 remains the same, but the gain of the output stage is P2□j 221
It has a characteristic that is bent at three places on P22. Po and P. is a pole, and Z2 is a point called a zero point. The frequencies of these points are: As is clear from this figure, by setting f2 near the pole frequency f□ of the differential amplifier, that is, C
By setting the oRo valve Car, the total gain f
The bend at l is eliminated. As a result, the overall gain is 6 dB10 ct when the frequency exceeds f21, and further f. 12dB10 when exceeding
It starts to decrease at the rate of ct. Here, Co=nC
If n is made sufficiently large by setting ar, /r2, Ro=r2/n, f21 and f22 can be separated sufficiently, and the feedback amplifier can be stabilized. FIG. 9(a) shows another embodiment of the feedback amplifier and phase compensation circuit. In this circuit, one phase compensation is performed by inserting a capacitor CF between the input and output of the output stage 22. A small signal equivalent circuit of this circuit without feedback is shown in FIG. 9(b), and its frequency characteristics are shown in FIG. 10. In this case, the gain of the differential amplifier is
Z, the characteristics are bent in three places on P12. In this case, as in the previous embodiment, the feedback amplifier can be stabilized by setting fi to be f, and by separating f11 and f1□ sufficiently. The features of this embodiment are as follows:
Since the phase compensation capacitor CF is inserted between the input and output of the amplification stage, the apparent capacitance increases due to the so-called Miller effect. therefore,
Since phase compensation can be performed even if the actual capacitance is relatively small, the area occupied by the capacitor can be reduced. Here, the capacitor used in the phase compensation circuit of FIG. 7 or 9 will be explained. These capacitors have fairly large capacitances (typically hundreds to thousands of pF);
It is also necessary for L to have small voltage dependence. FIG. 11(,) shows one way to achieve this using a normal CMOS process. In the figure, 101 is a P-type semiconductor substrate, 102 is an N-type well, 103 is a P-type diffusion layer, 104 is a Sin film for isolation, and 105 is a gate isolation R film. 106 is a gate. The capacitor, like a normal MOS capacitor, is formed between the gate 106 and the substrate surface 102a with the gate insulating film 105 in between. Since a thin gate insulating film is used as the capacitor insulating film, a feature is that a large capacitance can be obtained in a relatively small area. However, the difference from a normal MOS capacitor is that the threshold voltage is negative because there is an N-well under the gate. This will be explained using FIG. 4(b). The horizontal axis is the voltage applied to the capacitor (positive on the gate side), and the vertical axis is the capacitance. The threshold voltage is the applied voltage v0 when the capacitance changes significantly, and vo<0. Therefore, as long as a voltage is applied in one direction so that the gate side is positive, the capacitance is almost constant. If a bidirectional voltage can be applied, two capacitors shown in (a) may be used and connected in parallel in opposite directions as shown in FIG. 11(c). What are the steps required to make the capacitor of this example? The steps of forming a well, forming an isolation region, forming a gate insulating film, forming a gate, forming a diffusion layer, and wiring are all steps included in a normal CMOS process. [Therefore, if the semiconductor device is manufactured using a CMOS process, there is no need to add any special steps to manufacture this capacitor. Further, depending on the semiconductor device to which the present invention is applied, a stacked capacitor may be used. For example, a DRAM uses a stacked capacitor as a memory cell capacitor. In such a case, a multilayer capacitor may be used as a phase compensation capacitor. Regarding DRAM using stacked capacitors, see IE, Journal of Solid State Circuits, Vol. 15, No. 4, pp. 661-666, August 1980 (I.E.E. E Journal
of 5olid-9tate circuits,
Vol, 5C-22, No, 3+ pp, 661-66
6. Aug, 1980). [Reference Voltage Generating Circuit] Next, a reference voltage generating circuit suitable for use in the voltage limiter circuit according to the present invention will be described. Note that the reference voltage generation circuit described here can of course also be used in a voltage limiter circuit that does not perform phase compensation. The output voltage v of the voltage limiter is created based on the reference voltage VR. Therefore, due to the characteristics of VR. VL characteristics can be set arbitrarily. When using a voltage limiter circuit in a semiconductor device, the dependence of VL on external power supply voltage VCC is particularly important, so it is necessary to design it with particular attention to the dependence of VR on Vcc. Regarding this, examples of characteristics and their generation methods for various purposes are disclosed in the patent application issued in 1973.
6-57143. Patent application 1986-168698, patent application 1973
7-220083, Japanese Patent Application No. 60-261213, Japanese Patent Application No. 63-8372, Japanese Patent Application No. 63-125742, and US Pat. No. 4,100,437. It goes without saying that these circuits are applicable to the present invention. In the embodiments shown in FIGS. 1 to 4, the reference voltage VR was directly input to the drive circuit. However, the voltage obtained by the reference voltage generation circuit does not necessarily have a value appropriate as an internal power supply voltage used within a semiconductor device. In this case, voltage conversion is required. Further, in some cases, fine adjustment of the voltage, so-called trimming, may be necessary to compensate for variations in the reference voltage due to the manufacturing process. Voltage conversion and trimming methods are described in the aforementioned U.S. Pat. No. 41,004.
Although the method described in No. 37 may be used, a method suitable for semiconductor devices manufactured by a normal MOS process will be introduced here. Figure 12 shows the circuit diagram, DA is a differential amplifier, Q
)1~04m are P channel MOS transistors, F1~
F is a fuse. VR is the input voltage (output of the reference voltage generation circuit), and VR' is the output voltage (becomes the human power of the drive circuit). VR is input to one of the input terminals of DA, and VR' is input to the other input terminal of MOS transistors 031 to Q4.
The voltage V, +3 divided by 1 is fed back. If the amplification factor of DA is sufficiently large, the output voltage VR' is given by the following equation. Here, R1 is Q31 to Q3. The resistance value when the circuit consisting of is equivalently regarded as a resistance, R2 is Q39~Q4m
This is the resistance value when the circuit consisting of is equivalently regarded as a resistance. Since R, and R□ change by cutting the fuse, VR' can be adjusted. A specific trimming method will be explained using FIG. 13. This figure shows the characteristic when d in Figure 0 shows the relationship between input VR and output VR' and does not cut the fuse at all. When the fuses F0°F, , F are cut in order, the R becomes thicker, so VR' becomes higher as shown by c, b, and a. When fuses F, , Fs, and F are cut in order, the above R2
becomes larger, so VR' becomes lower as shown by eofyg. Therefore, first observe VR, and then select the fuse cutting method so that VR' is closest to the target value VR,'' by looking at Figure 13.Our goal is to ensure that VR varies over a wide range. Even though, V
The purpose is to make R' fall within a certain range VRo'±ΔVR'. To do this, as shown by the broken line in the figure, when a certain trimming method (for example, a) is adopted and V R1 == VR, j + ΔVR', the adjacent trimming method (for example, b) is used. If adopted, the circuit constants (channel width/channel length of each MOS transistor) may be selected so that VR' = Vn, '-ΔVR' L knee. FIG. 14 shows another embodiment of the trimming circuit. When lowering the output voltage VR', as in Fig. 12,
Hughes F4. It is sufficient to cut F, , F, in order. 1st
The difference from FIG. 2 lies in the method of increasing the output voltage VR'. In this case, first cut fuse F7 (at this point, select the circuit constants so that the input/output characteristics are as shown in h in Figure 13), then cut R4, F, , F in order. Just go. This circuit has the advantage that it has fewer fuses than the circuit of FIG. 12, and therefore occupies a smaller area. The circuits shown in FIGS. 12 and 14 have the advantage that they occupy a smaller area when fabricated using a normal MOS process than the circuits described in the aforementioned US patents. That is, in the circuit described in the U.S. patent, a resistor is used as an element for dividing the output voltage VR', whereas in the circuits shown in FIGS. 12 and 14, a MOS transistor is used. In order to reduce the current consumption of the circuit, the equivalent resistance of the voltage dividing element must be quite large (on the order of several hundred ohms). In a normal MOS process, an element with a smaller area and larger equivalent resistance can be obtained from a MOS transistor than from a resistor. However, if MOS transistors are used, there is a concern that the characteristics of VR' will fluctuate due to fluctuations in the threshold voltage. However, by making the channel width and length of each transistor sufficiently large to suppress variations, By connecting it to the source to avoid the effects of substrate potential fluctuations, and selecting the fuse cutting method taking into account variations in threshold voltage,
Solvable. Next, the MOS transistor used in the trimming circuit will be explained with reference to FIG. As described above, it is desirable that the pack gates of each transistor be connected to their respective sources in order to suppress the effects of substrate potential fluctuations. For example, if the substrate is P-type, a P-channel MOS transistor as shown in FIG. 3(a) may be used. If the substrate is N-type, an N-channel MOS transistor with all conductivity types reversed in (a) may be used.
In addition, as shown in the same figure (b), a double well structure is used,
By fixing the potential of the outer well 112 (grounded here), it is possible to further strengthen the structure against substrate potential fluctuations. Next, the fuse used in the trimming circuit will be explained. Examples of fuses include polycrystalline silicon, etc.
The same material used to repair defects in semiconductor memory can be used. Therefore, if the semiconductor memory has a defect relief circuit, there is no need to add a special process to make the fuse.The method for cutting the fuse may be a method using laser light or an electrical method. This method has the advantage that it can occupy a small area because it does not require a transistor for cutting, and the electrical method has the advantage that it does not require the use of an expensive laser beam irradiation device. FIG. 16(a) shows another embodiment of a VR to VR' conversion circuit, which differs from the circuit of FIG. 12 or FIG. 14 in that it includes a P-channel MOS transistor Q1. This is the addition of . As a result, the maximum value of the output voltage vR' is V
cc -I VTP l (Vtp is P channel MO
S transistor threshold voltage). This will be explained using FIG. 4(b). This figure shows the Vac dependence of VR and VR''. In the circuit of FIG. 12 or 14, when Vcc is low, VR': Vcc. However, as shown in FIG.
In this circuit, Vcc becomes low due to the addition of Q4m.
The advantage of this embodiment is that when Vcc is under normal operating conditions (for example,
The voltage stability of the internal power supply voltage Vt is good when it is considerably lower than Vt (for example, 3V). This will be explained using FIG. 16(0). This figure shows that in the drive circuit of FIG. 6 or 8,
This is an example of the relationship between output voltage VL and current IL when Vcc is low. Figure 12 or Figure 1 is used to generate VR'.
When using the circuit shown in Figure 4, when Vcc is low, Vb
Since press VR'''=Vcc, the output MOS of the drive circuit
The voltage between the drain and source of the transistor (Q in Figure 6 or Figure 8) is almost 0, and the current drive capability is small. Therefore, when the output current (current consumption of the load) IL increases, VL decreases. V
When the circuit shown in Fig. 16(a) is used to generate R', the drain-source leap voltage of the output MOS transistor of the open circuit is approximately IVtpl (0.5 in this example
Therefore, its current drive capability is relatively large, and the amount of decrease in v is small. That is, by setting VL a little low in advance, the amount of voltage fluctuation is reduced. As a result, the operation of a circuit within the semiconductor device that operates using V as a power source when Vcc is low becomes more stable, and the operating margin with respect to Vcc becomes larger. Note that the Q of the circuit in FIG. 16(a). Similarly to the MOS transistor of the trimming circuit described above, it is desirable to have the structure shown in FIG. 15 in order to suppress the influence of substrate potential fluctuations. [Internal Chip Arrangement/Wiring] Next, a circuit arrangement method and a wiring method for the reference voltage VR and internal power supply voltage v will be described when the present invention is implemented in an actual semiconductor chip. Here, a DRAM is used as a semiconductor device to which the present invention is applied.
will be taken as an example, but the present invention is of course applicable to other semiconductor devices. Furthermore, the arrangement and wiring method described here is also effective for voltage limiter circuits that are not subjected to one-phase compensation. FIG. 17 shows an example of a desirable circuit layout and wiring when a voltage limiter circuit is applied to a DRAM. In the figure,
1 is a semiconductor chip, 2a and 2b are memory arrays made up of fine MOS transistors, and 3a, 3b, and 3c are peripheral circuits. 4.5 is a grounding pad and a bonding pad for external power supply voltage Vcc, 6 is a reference voltage generation circuit, and 7a. 7b, 7c, and 7d are active circuits. 6 and 7a to 7d constitute a voltage limiter circuit. 7a, 7b, and 7c are peripheral circuits 3a, respectively. Internal power supply 'II voltage VL, , V that drives 3b and 3c
L. ■ and generate. 7d generates an internal power supply voltage VL4 for driving memory arrays 2a and 2b. The features of this embodiment include the reference voltage generation circuit 6 and the drive circuit 7a.
~7d, and the reference voltage generation circuit is located near the ground potential input pad. The reason is that each drive circuit is placed near the load circuit. Therefore, the ground wiring 8 from the ground potential input bonding pad to the reference voltage generation circuit and the internal power supply voltage wiring 11a to lid from each drive circuit to each load circuit are shortened, and their impedances are reduced. As a result, the noise on the wiring 8 is reduced, so that the ground level of the reference voltage generation circuit is stabilized, and a stable reference voltage VR can be obtained. Also, the internal power supply voltage V due to the impedance of the wiring 11a to lid
Since the voltage drop of L, ~vL4 decreases, ■L□ ~vL
The level of , becomes stable, and the operation of the load circuit becomes stable. Another feature of this embodiment is the method of ground wiring. First, a dedicated short wiring 8 is used for the reference voltage generation circuit.
will be established. For other circuits, arrangements g9a to g9d are provided. That is, each drive circuit and its load circuit are wired using a common line, but are separated from other drive circuits and load circuits. The advantage of this wiring system is that noise generated on the ground wiring due to the current flowing when each circuit operates can be prevented from adversely affecting other circuits. In particular, if noise occurs in the ground wiring of the reference voltage generation circuit, the levels of all internal power supply voltages vL1 to vL4 will fluctuate, so be sure to separate the ground wiring for the reference voltage generation circuit from other ground wiring. It is also desirable to separate the ground wiring for the memory array from other ground wiring. This is because when a sense amplifier performs an amplification operation in a DRAM, there are many data lines (the capacitance of which is usually several thousand pF).
) are charged and discharged at the same time, causing large noise in the ground wiring. FIG. 18 shows another example of circuit layout and wiring. In this embodiment, the peripheral circuit 3 is arranged in a concentrated manner in the center of the chip, and the bonding pads 4 and 5 for grounding and external power supply voltage Vcc are also arranged in the center of the chip. In this embodiment as well, the reference voltage generation circuit 6 is placed near the ground potential input bonding pad, and the drive circuits 7a and 7d are placed near their respective load circuits. The advantage of this embodiment is that the wiring length is shortened, as is clear from FIG. This makes it resistant to fluctuations in the external power supply voltage Vcc and fluctuations in the current flowing through the load circuit. That is, in the previous embodiment, since the wiring 10 between the Vcc bonding pad and each drive circuit is long, its impedance is large, and the level of Vcc is lowered by the current consumption of the load circuit. Of course, each drive circuit is designed to absorb this decrease, but if the amount of decrease is too large, it may not be able to be absorbed completely, which may lead to a decrease in the level of internal power supply voltage VL. On the other hand, in this embodiment, since the impedance of the Vcc wiring 10 is small,
A larger load current can be passed accordingly. Also, Vcc
It is also resistant to decreases in In FIG. 17 or 18, the noise in the ground wiring is particularly problematic because of the reference voltage VR and the internal 1!
This is because the source voltage V L 1 is generated with the ground potential as a reference. Conversely, Vfl, VL, t are external power supply voltages V
If the noise is generated based on cc, the noise of the Vcc wiring becomes more of a problem. In this case, the reference voltage generation circuit is set to V
It is sufficient to arrange the Vcc wiring near the CC bonding pad and separate the Vcc wiring for each circuit. Note that in the layout/wiring method shown in FIG. 17 or 18, the reference voltage VR is wired from the reference voltage generation circuit to each drive circuit, but it is desirable that this wire 12 be shielded. . This is to prevent VR from varying due to noise from other circuits within the semiconductor chip. An example of a shielding method that can be realized in a normal semiconductor manufacturing process will be described next. FIGS. 19(a) and 19(b) show a plan view and a cross-sectional view, respectively, of an example of shielded wiring, in which 101 is a semiconductor substrate, 104 is a Sin, and 108 is a first wiring. Layer, 109a. 109b and 109c are second wiring layers, 113° and 114 are interlayer insulating films, and 115 is a protective film. 109b is a wiring for the reference voltage VR. 10 around it
Shield wirings 8, 109a, and 109c are fixed at a constant potential (here, grounded). By providing 108 below 109b, noise due to capacitive coupling with the substrate 101 can be prevented, and by providing 109a and 109c on the left and right sides, noise due to capacitive coupling with adjacent wiring (not shown) can be prevented. Figures 19(c) and (d)
) is another example of shielded wiring. In this embodiment, VR is wired with the first wiring M108b,
Shield wiring is provided on the left and right (108a, 108c), below (106) and above (109), respectively. By providing shield wiring above as well, it is possible to prevent noise due to capacitive coupling through the space above, making the shielding more effective. Further, as shown in FIGS. 12(e) and 11(f), contact holes 116a, 116c and through holes 117a, 117c are provided to connect the shielding wirings, thereby completing the shielding. Figure 19(g)
, (b) shows another example of shielded wiring 6
In this embodiment, the polycrystalline silicon layer 106 is the VR wiring. A well 112 is formed below it, and a P-type wave diffusion layer 107a. 107c, and contact hole 116a. It is connected to the upper first wiring layer 108 via 116c. In other words, the surroundings of 106 are 112, 107
a, 116a, 108. 116c. It is shielded by surrounding it with 107c. The advantage of this embodiment is that since the second wiring layer is not used for the shield, it can be used for other purposes as shown at 109 in FIG. 19(g). This is effective when used, for example, at a portion where VR wiring and other wiring intersect. Note that although the above-described shield creates a parasitic capacitance between VR and ground, this has a rather favorable effect. This parasitic capacitance reduces the impedance of the VR wiring to high frequencies and bypasses high frequency noise.
This is because it functions as a so-called decoupling capacitor. If the shield wire alone does not have enough capacitance as a decoupling capacitor, it is of course possible to add a separate capacitor. In the above example, the potential for fixing the shield wire is the ground potential, but it does not necessarily have to be the ground potential as long as it is a stable potential. However, it is easiest to set it to the ground potential, and as mentioned above, it is desirable because the parasitic capacitance acts as a decoupling capacitor. It is better to connect the shield wire to 8) in order to avoid noise generated by the operation of other circuits.If VR is generated based on Vcc as mentioned above, it is better to fix the shield wire to Vcc. good. FIG. 20 shows another example of circuit layout and wiring. In the figure, 1 is a semiconductor memory chip, 3 is a peripheral circuit, 7a, 7
b and 7c are drive circuits 14a and 14b that generate internal power supply voltages VL, respectively; 14c and 14d are pulses φpit φpit φP3゜φ with voltage amplitude Vt using the output of the drive circuit as a power source.
Pulse generating circuits 2a and 2b that generate P. 2c and 2d are respectively φPLe φP2e φpss
This is a memory array using fine MOS transistors operated by φP4. Note that the description of the reference voltage generation circuit is omitted here. FIG. 21 shows the operation timing of these circuits. A single external power supply voltage VCC (for example, 5V) is applied to the semiconductor memory chip 1 of this embodiment. Internal power supply voltage VL (for example, 3V) lowered from Vcc is output from drive circuits 7a, 7b, and 7c, and pulse generation circuits 14a, 14b, and 14c. 14d, respectively. Further, the timing pulse φd shown in FIG. 21 and an address signal a having a phase opposite to that of the address signal a1 are inputted to the pulse generating circuit. Peripheral circuit 3 receives external address signal A+ to generate internal address signals al and a, and receives external control signals (here, row address strobe signal RAS, column address strobe CAS, and write enable signal WE) to generate internal timing pulses. The 0 peripheral circuit that generates φT does not have much effect on the degree of integration of the chip, so there is no need to use minute elements, and due to the convenience of the external interface, the external power supply voltage Vc
Although the circuit is operated directly with c, it is of course possible to operate with the internal power supply voltage. Only the memory array selected by the address operates. In this example, B, = “Q” (a, = (111#
), arrays 28 and 20 are selected (2b and 2d are not selected), and when Q, = “1” (a, = “0”), array 2
b and 2d are selected (2a and 20 are not selected). Therefore, only pulses for the selected array are output. That is, as shown in FIG. 21, a,=゛'0
”, the pulse generating circuits 14a and 14c output φpit φP by the timing pulse φT to drive the arrays 2a and 20, and conversely, when aL="1", the pulse generating circuits 14b and 14d output the timing pulse φT Therefore, φp
2t φP, to operate arrays 2b and 2d. The feature of this embodiment is that each drive circuit is arranged close to each pulse generation circuit, and moreover, the drive circuit 7b is shared between pulse generation circuits 14b and 14c. Therefore,
Compared to the conventional example shown in FIG. 36, the wiring is shorter and the impedance of the wiring is smaller, thereby making it possible to suppress the level of noise generated. Furthermore, compared to FIG. 37, the number of drive circuits is reduced by one, thereby reducing the chip occupation area and power consumption. Moreover, since the pulse generation circuits 14b and 14c do not operate simultaneously, the drive circuit 7b only needs to drive one pulse generation circuit, and there is no need to double the current drive capability. The pulse generating circuits 14a to 14d can be realized by the circuit shown in FIG. 22, for example. In FIG. 22, 51 is
P-channel MOS transistor Q6, TQGz and N-channel MOS transistor Q6. . This is a two-person NAND circuit consisting of Q54. The power supply of this circuit is Vcc, and the inputs are a timing pulse and an address signal at (or ai). 52 is. P-channel MOS transistor Qss and N-channel MO
This is an inverter consisting of an S transistor Q□, and its power supply is VL.When φT is input when eat is at the rtVpC potential (Vcc), a pulse φ with an amplitude of the internal power supply V is generated.
P is output. Note that although the NAND circuit is operated with the external power supply voltage Vcc here, it may be operated with the internal power supply voltage V. FIG. 23 shows an example in which the number of drive circuits is further reduced by one compared to the embodiment shown in FIG. 20. address signal at,
at, timing pulse φd, and pulse φP, ~φ
P4 is the same as that explained in FIG. In this embodiment, the pulse generation circuits 14a and 14b share the drive circuit 7a, and the pulse generation circuits 14c and 14d share the drive circuit 7b. Therefore, compared to the embodiment shown in FIG. 20, the number of drive circuits is reduced by one, thereby reducing the chip area and power consumption. Here, as shown in FIG. 21, 14a and 14
b, 14c and 14d do not operate simultaneously. Therefore, each of the drive circuits 7a and 7b only needs to be able to drive one pulse generation circuit, and there is no need to double the drive capacity. FIG. 24 shows an embodiment in which the present invention is applied when the memory array is divided into eight parts. In the figure, 1 is a semiconductor chip, 3 is a peripheral circuit, 2a to 2h are memory arrays, and 7a
, 7b are drive circuits, and 14a to 14h are pulse generation circuits. In this embodiment, two of the eight arrays are selected by the address signal ass aJ, and only the selected array operates. In other words, when a+aJ="oO", 2a and 2e, and when alaJ: "01", 2b
and 2f, when a t a J = "10", 2C and 2
g, 31i1j::"11"', 2d and 2h are selected, respectively. Therefore, only the pulse φPk (k=1 to 8) for the selected array is output. That is, as shown in FIG. 25, address signal aiaJ="
00'', pulse φP1 and φF @ & 81 a
When J ””“01′”, pulse φP2 and φP@+
When aiaJ="10", pulses φP, φP, ,
When ataa="11", pulses φP4 and φP are output, respectively.These pulses φph (k=1~
8) Ha. This is a pulse output at the timing φT, and its amplitude is the internal power supply voltage VL. In this embodiment, two opening circuits are shared by eight pulse generation circuits for operating the memory array. By doing this, l! The number of dynamic circuits can be significantly reduced, resulting in reductions in occupied area and power consumption. (Example of application to DRAM) Finally, an example in which the present invention is applied to a DRAM will be described. Fig. 26 is a block diagram of a DRAM to which the present invention is applied. In Fig. 0, 201 is a pump for supplying power supply voltage (Vcc). 202 is a differential amplifier, 203 is a supply line for the internally stepped down power supply voltage (VL), and 204 is a starting M for the P-channel MOS sense amplifier.
OS transistor, 205 is a startup MOS transistor of the N-channel MOS sense amplifier, 206 is a P-channel M
OS sense amplifier, 207 is an N-channel MOS sense amplifier, 208 is a memory cell, 209 is a P-channel MOS
210 is a memory block including a cell array part and a sense amplifier part; 211 is an X decoder; 212 is a Y decoder; 213 is a short precharge signal line; and 214 is a power supply 11Vb/2. The power supply voltage Vcc is used in peripheral circuits such as an X decoder, a Y decoder, a gate protection circuit, and a signal generation circuit. In this embodiment, the internally stepped down power supply voltage v is connected to a P-channel MO connected to the sense amplifier activation MOS transistor 204.
It is used for the source power supply of the S sense amplifier, the back gate (well) of the P channel MOS transistor, and a part of the Y decoder. In the case of a so-called CMO8 circuit such as a sense amplifier, P
When using a shaped substrate, a P-channel MOS transistor is typically formed in an N-type well. In this case, as shown in the cross-sectional view of FIG. 27, the potential of the N-well (back gate of the P-channel MOS transistor) is not the external power supply voltage Vcc, but the operating voltage supplied to its source (V L in this case). It is desirable to do so. The reason for this will be explained next. For example, if Vcc = 5V, VL = 3V, the data line precharge level is 1.5V, so before starting the sense amplifier, the P channel MOS transistor has a voltage of 1.5V.
A back gate bias of v is applied and becomes Ov after startup. Taking Figure 34 as an example, the threshold voltage (absolute value) before starting the sense amplifier is about Q, 86V, and after starting it is about 0.5
7V-? 'be. If the N well voltage is Vcc (=5V)
1. IV, 0.92V and iJ, V
It is too large compared to t. Figure 28 shows the above DRA
This is a diagram in which the operating speed of the M sense system is plotted against the threshold voltage of a P-channel MOS transistor. Since the increase in the threshold voltage of IV corresponds to a delay of about 2 ns, it can be seen that in this case, by setting the N-well voltage to VL (=3 V), a speed increase of about 5 ns or more can be realized. CMO8L in the era of ultra-high integration
Since SI tends to further lower the operating voltage and increase the substrate (well) concentration (increasing the bank gate bias effect), the above effects of the present invention become even more important. Here, the N well voltage is supplied to the P channel MOS transistor. 1! In making the gs voltage equal to v, there is a concern about fluctuations in the N-well voltage due to capacitive coupling and the like. The embodiment shown in FIG. Since the data line is precharged to VL/2, when the P-channel MOS transistor operates, one whose drain voltage rises and one whose drain voltage falls form a pair, and the noise is extremely small. therefore. Problems such as latch-up due to fluctuations in the N-well voltage do not occur. Although the sense amplifier has been described above as an example, similar techniques can be applied to other CMO8 circuits as well. Also,
The present invention is applicable not only to DRAM but also to CMO8-LSI having two or more different operating voltages. Furthermore, in the embodiments of the present invention, it is clear that the present invention will work even if the conductivity types and potential relationships of the semiconductors are all reversed. (Effects of the Invention) As explained above, according to the present invention, the voltage limiter circuit needs to drive many types of loads, and even when the type and size of the load varies depending on the operation mode, the load This enables optimal phase compensation depending on the type and operation mode of the voltage limiter, and stabilizes the operation of the voltage limiter.In addition, if there are multiple load circuits in a semiconductor chip that use internal voltage as a power source, Since the wiring to each load circuit can be shortened, the noise level can be kept low. Also, the number of circuits can be reduced without increasing the drive capacity of the drive circuit.
The occupied area and power consumption can be reduced. In addition, in a CMO8 circuit that uses an internally stepped down operating voltage, by making the back gate (well) voltage of the transistor formed in the well equal to the stepped down voltage, the circuit can be made faster. It is possible to achieve both the high reliability and high speed of an ultra-highly integrated LSI. In addition, in a CMO8 circuit that uses an internally stepped down operating voltage, by making the back gate (well) voltage of the transistor formed in the well equal to the stepped down voltage, the circuit can be made faster. It is possible to achieve both the high reliability and high speed of an ultra-highly integrated LSI.

[Brief explanation of the drawing]

1 to 28 are diagrams for explaining the present invention in detail,
29 to 34 are diagrams for explaining the problems of the prior art. ] Fig. 1-6: Fig. Figure CC) Te map (phantom 1st diagram + 01 (Dip diagram (-e) CC) F'7 @ Maru IL Engraving of the drawing (no changes to the content) Noa En Atsushi 1 and 2! Ni ¥22 Figure (α) +b) Hitsuji-24 Zumezuchi 2g Ishi Red Murochi 1 [V] No. =0 (27 ¥32 Zuka 31 ■ Procedural amendment (method) % formula % Indication of the case Heisei 1, Invention Name related to the name amendment case (510) Name Patent Application No. 16148 Semiconductor device

Claims (1)

[Claims] 1. In a semiconductor device having a plurality of internal voltage generation circuits and a plurality of internal circuits that use the output of the internal voltage generation circuit as a power supply, the plurality of internal circuits can be selectively controlled by a control signal. A semiconductor device characterized in that at least two of the internal circuits that operate simultaneously and that do not operate simultaneously share one internal voltage generating circuit. 2. The semiconductor device according to claim 1, wherein the plurality of internal circuits are semiconductor memories, and the control signal is an address signal of the semiconductor memory. 3. A complementary metal insulating film semiconductor integrated circuit that uses a voltage smaller in absolute value than Vcc as the power supply voltage (VL) at least in part, where Vcc is the highest power supply voltage in absolute value among the externally supplied power supplies. (CMOS/LSI
), the MO whose source terminal is connected to the above V_L
1. A semiconductor device comprising an S transistor, and a back gate voltage of at least a part of the MOS transistors is set to the above-mentioned V_L. 4. In a MOS dynamic memory (DRAM) in which a P-channel MOS transistor is integrated on an N-well formed on a P-type substrate, and an N-channel MOS transistor is integrated on the P-type substrate, a sense amplifier including a sense amplifier is integrated. At least in part of the system, the operating voltage (V_L) is lower than the externally supplied voltage (Vcc), and P with V_L as the operating voltage
4. The semiconductor device according to claim 3, wherein the voltage of the N-type well in which the channel MOS transistor is integrated is V_L.