JPH11288586A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the level of noise to be generated in a device by arranging a voltage limiter circuit and the load circuit of a pulse generating circuit or the like closely to make impedances of wirings between these circuits small. SOLUTION: A reference voltage generating circuit 6 and drive circuits 7a to 7d are separated and the reference voltage generating circuit 6 and the drive circuits are respectively arranged in the vicinity of a bonding pad for inputting ground potentials and in the vicinity of respective load circuits. As a result, a grounding wiring 8 from the pad till the circuit 6 and internal power source wirings 11a to 11d from respective driving circuits till respective load circuits are shortened and their impedances become small. Thus, noise being on the wiring 8 is reduced and the ground level of the circuit 6 is stabilized and a constant reference voltage is obtained. Moreover, the short wiring 8 dedicated for the circuit 6 and wirings 9a to 9d for other circuits are provided is provided as a grounding wiring method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-large-scale integrated circuit such as a dynamic memory having a storage capacity of 16 Mbits or more.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, a stable reference voltage with little fluctuation due to an external power supply voltage or temperature may be required. The LSI voltage limiter is described in, for example, ISSC Digest of Technical Papers, pp. 272 to 273.
Page, February 1986 (ISSCC Digest of Technic)
alPapers, pp. 272-273, Feb. 1986). As stated in the last paper,
In a memory LSI such as a RAM (dynamic random access memory), a voltage lower than an external power supply voltage is generated by a circuit (voltage limiter) provided on an LSI chip, and is used as a power supply in some cases. This internal power supply voltage needs to be a stable voltage with little fluctuation due to the external power supply voltage or temperature in order to stabilize the memory operation, and for that purpose, a stable reference voltage is required. Also,
LSIs with built-in analog circuits often require a stable reference voltage as a reference voltage.

As a reference voltage generating circuit that meets such demands, for example, US Pat. No. 3,975,648 and US Pat.
There is a circuit proposed in, for example, No. 100377. FIG.
Figure 2 shows the circuit diagram. This is a circuit that obtains a stable voltage by utilizing a difference in threshold voltage between an H-channel enhancement MOSFET (hereinafter abbreviated as EMOS) and a depletion MOSFET (hereinafter abbreviated as DMOS). In the figure, Q ₉₁ is _{EMOS, Q 90, Q 92,} Q 93 is DMO
S, and V _CC and V _BB are external power supplies of a positive voltage and a negative voltage, respectively. Difference between the threshold voltage of the EMOS and DMOS is the output voltage V _R. Hereinafter, the operation of this circuit will be described.

The currents flowing through Q ₉₀ and Q ₉₁ are represented by I ₉₀ , Q ₉₂ and Q
_The current flowing through ₉₃ is defined as I ₉₁ . Assuming that all four MOSFETs operate in the saturation region, the following four equations hold.

[0005] _{I 90 = (β 90/2} ) · (-V TD) 2 ... (1) I 90 = (β 91/2) · (V 99 -V TE) 2 ... (2) I 91 = (β _92/2 ) · (V ₉₉ −V _R −V _TD ) ² ... (3) I ₉₁ = (β _93/2 ) · (−V _TD ) ² ... (4) where V ₉₉ is the voltage of node 99, V _TE and V _TD are threshold voltages of EMOS and DMOS (V _TE > 0, V _TD <
0), β ₉₀ , β ₉₁ , β ₉₂ , and β ₉₃ are Q ₉₀ , Q ₉₁ ,
Is the conductance coefficient of Q _92, Q _93. (1)-
(4) from the _{equation, V R = V TE - (} 1+ (β 90 / β 91) - (β 93 / β 92)) · V TD ... (5) where beta ₉₀ and beta ₉₃ Do sufficiently small, Or β _{90
/ Β 91 = β 93 / β} 92 and so as to be determined the constant of each MOSFET, the _{V R = V TE -V TD ...} (6). That, EMOS and DM as an output voltage V _R
A voltage having a difference between the OS and the threshold voltage is obtained, which is a stable voltage independent of the voltage of the external power supply V _CC or V _BB .

[0006] In recent years, as the degree of integration of semiconductor devices has increased, reduction in breakdown voltage due to miniaturization of semiconductor elements has become a problem. This problem can be solved by lowering the power supply voltage of the semiconductor device, but this is not always preferable because of the external interface. Therefore, the power supply voltage applied from the outside remains unchanged (for example, TTL (transistor transistor)
(Logic 5) In the case of compatible, a method has been proposed in which an internal power supply of a lower voltage (for example, 3 V) is formed in the semiconductor device. For example, IEE, E., Journal of Solid State Circuits, Vol. 22, No. 3, pp. 437-441, June 1987 (IEEE Journal of Solid State Circuits).
Solid-State Circuits, Vol. SC-22, No. 3,
pp. 437-441, June 1987) describes an example in which this method is applied to a DRAM (Dynamic Random Access Memory) and a circuit (voltage limiter circuit) for generating an internal power supply from an external power supply.

FIG. 7B is a circuit diagram of a voltage limiter circuit described in the above-mentioned document. In the figure, VL is a voltage limiter circuit, which comprises a reference voltage generation circuit VR and a drive circuit B. Z is a circuit that operates using the load of the voltage limiter, that is, the output voltage _VL of the voltage limiter as a power supply. The reference voltage generation circuit V _R generates a stable voltage V _R with little fluctuation due to the external power supply voltage V _CC and temperature. Drive circuit B
Is a circuit in which the voltage value to generate a larger voltage V _L of the same driving capability as V _R, the differential consists of Q ₁₀₆ to Q ₁₁₁ amplifier D
A to consist of the output MOS transistor Q _112. Of the two input terminals of the differential amplifier DA, V _R is connected to one, since the other output V _L is fed back, as the circuit output V _L follows the input V _R Operate. Output V
_L of the drive capability is determined by the channel width of the output MOS transistor Q _112. Accordingly, if designing a size commensurate with channel widths of Q ₁₁₂ to the current consumption of the load,
A stable internal power supply voltage _VL can be supplied to the load.

[0008]

Based on the above-mentioned prior art, the present inventors have studied in detail a specific ultra-large-scale integrated circuit (for example, an LSI of 16 Mbit or more in a DRAM). I discovered the following problems. This problem is broadly related to the reference voltage generation circuit, to the voltage limiter circuit, and to these tests.

First, the problem of the prior art shown in FIG. 7A is that it is difficult to match the characteristics of EMOS and DMOS because they use different devices. In the above description, the characteristics are assumed to be the same for simplicity, but actually, the temperature dependence d of the conductance coefficients β
The characteristics such as β / dT and the temperature dependency dV _T / dT of the threshold voltage are considerably different. This is because the threshold voltage difference V _TE −V between the EMOS and the DMOS is as follows.
_{This is because TD} must be considerably large.

The EMOS must be reliably turned off when the gate-source voltage is 0V. For this purpose, the threshold voltage V _TE needs to be set to a considerably high value (for example, V _TE ≧ 0.5 V) in consideration of manufacturing variations and sub-threshold characteristics. Also, D
Since a MOS is sometimes used as a current source as shown in equations (1) and (4), the absolute value of the threshold voltage V _TD is considerably large (eg, V _TD ≤ -1.5V). Therefore, V _TE −V _TD becomes considerably large (for example, V _TE −V _TD ≧ 2 V), which means that the impurity profile of the channel region of the MOSFET is greatly different. As a result, the MOSFE as described above
A mismatch in characteristics as T occurs. An object of the present invention is to solve the above-mentioned problems and to provide a reference voltage generating circuit that does not use a buried type FET.

A first problem of the prior art shown in FIG. 7B is that the stability of the operation of the voltage limiter circuit is not considered. Generally, an amplifier with feedback, such as the drive circuit B in FIG. 7B, becomes unstable if not designed to have a sufficient phase margin. This will be described with reference to FIGS. Assuming that the relationship between the frequency and the gain and the frequency and the phase of the amplifier when no feedback is applied is as shown in the figure, a numerical value indicating how much margin the phase delay has at 180 ° at a frequency where the gain is 0 dB. Is the phase margin. If the phase margin is negative, the feedback amplifier oscillates, and if it is positive, the operation becomes unstable if the margin is small. It is generally said that a stable operation requires a phase margin of 45 ° or more. For this purpose, the second point P ₂ (in which the slope is 6 dB) among the points (poles) where the frequency vs. gain characteristics are bent.
At the point where the gain changes from / oct to 12 dB / oct)
It must be less than dB. Since the mission of the voltage limiter circuit is to supply a stable internal power supply voltage to the internal circuit, it is needless to say that the voltage limiter circuit must not oscillate or operate unstable.

As a countermeasure against this problem, various methods for compensating for the phase delay have been proposed, for example, by Paul Earl Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, 2nd Edition, John R. Gray and Robert G. Meyer: Ana
lysys and Design of Analog Integrated Circuit
s, 2nd Ed., John Wiley and sons Inc. However, applying the phase compensation to a voltage limiter circuit of an actual semiconductor device has the following problems. A circuit serving as a load of the voltage limiter circuit is an internal circuit of an actual semiconductor device, and includes a very large variety of circuits such as a capacitance, a resistance, an inductance, a non-linear element, and a combination thereof. And those loads are
It is not constant in time and may change depending on the operation mode of the semiconductor device. For example, the current flowing through the load greatly differs between when the semiconductor device is in the operating state and when it is in the standby state. As a result, the bias condition of the output stage of the drive circuit B in FIG. 7B changes, and as a result, the frequency characteristics of the whole amplifier also change. In order to operate the voltage limiter circuit stably, it is necessary that the amplifier having such a complicated property always operates stably. Conventional phase compensation methods alone are not sufficient.

A second problem of the above prior art is that the arrangement and wiring on the semiconductor chip are not considered. In particular, when there are a plurality of circuits operating at the internal power supply voltage _VL , the arrangement of the voltage limiter circuit and its output voltage _VL
Was not considered.

The present inventors have discovered that the following problems occur when the above-described conventional technique is applied to a semiconductor memory. 3 and 4 show examples in which the above-described conventional technique is applied to a semiconductor memory. In FIG. 3, 1 is the entire semiconductor memory chip, 3 is a peripheral circuit, 7 is a driving circuit of the voltage limiter circuit (a reference voltage generating circuit of the voltage limiter circuit is omitted here), and 14a to 14a to
14d is a pulse generating circuit, and 2a to 2d are memory mats composed of fine MOS transistors.

Since the memory mat uses fine elements, it is operated with the internal power supply voltage _VL . The drive circuit 7 and the pulse generation circuits 14a to 14d are circuits for this purpose. 7
Generates an internal power supply voltage _VL , and 14a to 14d have an amplitude _VL
Pulse φ _{P1 to} φ _P4 are generated. In this example,
While there are four pulse generating circuits 14a to 14d, only one driving circuit 7 is provided. Therefore, in order to supply the internal power supply voltage _VL generated by this voltage limiter circuit to each pulse generation circuit, a long wiring extending from the upper side to the lower side of the chip is required, and the parasitic impedance of the wiring becomes large and noise is generated. Cause. If the wiring width is increased in order to reduce the impedance, there arises a problem that the area occupied by the wiring on the chip increases.

FIG. 4 shows one pulse generation circuit corresponding to each pulse generation circuit in order to avoid the problem of long wiring in FIG.
This is an example in which drive circuits 7a, 7b, 7c, 7d are provided individually. By doing so, the wiring length between the voltage limiter circuit and the pulse generation circuit can be reduced, but the same number of voltage limiter circuits as the number of pulse generation circuits (here, four) are required. Therefore, the occupied area and current consumption of the voltage limiter circuit on the chip are increased as compared with the case of FIG. If the number of pulse generation circuits is further increased, the area occupied by the voltage limiter circuit and the power consumption will increase.
This is a serious problem for a semiconductor device for high integration and low power consumption.

The third problem of the above prior art is that the CMOS
That is, the operation speed of the circuit is not considered.
This problem is solved by using a dynamic random access memory (hereinafter referred to as DRAM) manufactured using the state of the art in microfabrication technology.
This will be described below.

FIG. 5 shows a part of a circuit block configuration of an N-well type CMOS DRAM. The memory cell array section in the figure is on a P-type substrate. The sense amplifier section includes N-channel and P-channel MOS transistors, and an N-well corresponding to a substrate of the P-channel MOS transistor is connected to a power supply voltage.

ISSC, FAM 18.6, 1984, p. 282 (ISSC
As discussed in US Pat. Occurs. In order to prevent this, it is conceivable to lower only the power supply voltage used in a memory array that needs to be miniaturized in order to improve the degree of integration in consideration of the stress withstand voltage. This is because, for example, the external power supply voltage V _cc is applied to the peripheral circuit section (X decoder, Y decoder, etc.) of the DRAM, and the operating voltage V _CC lower than V _cc is applied to the memory cell array section including the sense amplifier.
_L (| V _L | <| V _CC |). That is, a voltage supply line connected to the source of P-channel MOS transistor of the sense amplifier in FIG. 5 and V _L, the voltage supply line of the peripheral circuit portion and V _CC.

However, it has been found that in a CMOS DRAM, when the operating voltage of the memory array section is reduced as described above, the operating speed is significantly reduced. As a result of detailed analysis, it has been clarified that the cause is an increase in threshold voltage due to the back gate bias effect of the P-channel MOS transistor. That is, N in the P-type substrate
If the potential of the source of the P-channel MOS transistor formed in the well is the internal power supply voltage V _L and the potential of the N-well (the back gate of the P-channel MOS transistor) is the external power supply voltage V _CC , V A back gate bias of _CC - _VL is applied, and the threshold voltage increases.

FIG. 6 shows a gate length of 1.2 μm and a gate width of 1 μm.
The threshold voltage is plotted against the difference (back gate bias) between the back gate (N well) voltage and the source voltage of a 0 μm P-channel MOS transistor. In this example, when a back gate bias of 2 V is applied, the threshold voltage increases by about 0.35 V. Currently LS
If, for example, V _L = 3 V with respect to the power supply voltage V _CC frequently used in I, the threshold voltage rise of 0.35 V exceeds 10% of the operating voltage, which directly leads to speed degradation.

Another object of the present invention is to solve the above first problem and to provide a voltage limiter circuit with stable operation.

Another object of the present invention is to solve the above second problem and to provide a voltage limiter circuit with low noise, small occupation area and low power consumption.

Still another object of the present invention is to solve the third problem described above and to provide a high speed and high reliability CMOS LSI (la
rge scale intergrated aircuit).

It is another object of the present invention to provide an actual configuration of a very large scale integrated circuit in addition to the above.

It is yet another object of the present invention to provide a practical layout for very large scale integrated circuits.

[0027]

In order to achieve the above object, the present invention uses two enhancement-type FETs having different threshold voltages, and extracts a potential difference when a constant current flows through them. As the reference voltage.

In order to solve the first problem, according to the present invention, when the voltage limiter needs to drive many types of loads, a plurality of drive circuits constituting the voltage limiter are provided according to the type of load. And perform phase compensation on each. When the type and size of the load temporally change depending on the operation mode of the semiconductor device, the circuit constants of the drive circuit and the phase compensation circuit are changed depending on each operation mode. Alternatively, an individual drive circuit is provided for each operation mode, and their outputs are connected to be the output of a voltage limiter.

The second problem is that a voltage limiter circuit and a load circuit such as a pulse generation circuit using its output as a power supply are arranged close to each other, and have a selection / non-selection relationship by a control signal such as an address signal. The problem is solved by sharing one voltage limiter circuit among a plurality of load circuits.

In order to solve the third problem, according to the present invention, in a CMOS LSI, the M
The back gate (well) voltage of the OS transistor is made equal to the operating voltage supplied to the source terminal.

Since two FETs of the enhancement type having different threshold voltages are used instead of the depletion type FETs, the difference between the threshold voltages can be made sufficiently small (in principle, no matter how small it is). Good). Therefore, it is easier to match the characteristics of the two FETs than in the conventional technique, and a more stable reference voltage can be obtained as compared with the conventional technique.

When it is necessary for the voltage limiter to drive many types of loads, the drive circuit is divided into a plurality of circuits according to the loads, and each of the circuits is subjected to phase compensation, so that an optimum phase according to the type of the load is obtained. Compensation becomes possible. In addition, depending on the operation mode of the semiconductor device, the circuit constants of the drive circuit and the phase compensation circuit may be changed, or individual drive circuits may be provided for each operation mode, and their outputs may be connected to be used as the output of a voltage limiter. Thereby, optimal phase compensation corresponding to the load fluctuation can be performed. Thereby, a voltage limiter circuit with stable operation can be made.

By arranging a voltage limiter circuit and a load circuit such as a pulse generation circuit using its output as a power supply close to each other, the impedance of the wiring between them can be reduced, and the level of generated noise can be reduced. Can be suppressed. Further, the number of voltage limiter circuits can be reduced by sharing one voltage limiter circuit among a plurality of load circuits that are selected / non-selected by a control signal such as an address signal. Therefore, the area occupied by the circuit and the power consumption can be reduced. Here, the voltage limiter circuit only needs to drive the circuit in the selected state among the load circuits. Therefore, it is not necessary to increase the current driving capability of the voltage limiter circuit by sharing.

In the CMOS LSI, the threshold voltage of the MOS transistor formed in the well can be prevented from rising due to the back gate bias effect by setting the well voltage to the internal power supply voltage _VL .

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.

This description is divided into first, second, and third groups for easy understanding, and will be described in this order.
Thus, each group describes its application to actual very large scale integrated circuits. However, this will not be understood by those skilled in the art that these groups are not meant to be completely independent. That is,
These groups naturally suggest the combination when it is technically possible to carry out the combination. Further, as will be apparent from the following description, the first, second, and third groups are not mutually exclusive technologies and, in most cases, are more synergistic when combined. The art will be understood by those skilled in the art.

[First Group] Embodiments of a first group of the present invention will be described below with reference to the drawings. In the following description, a case where a positive reference voltage is generated will be described. However, a negative reference voltage can be generated by reversing the polarity and the like of the transistor.

FIG. 1A is a circuit diagram of a first embodiment of the present invention. This circuit is an N-channel MOSFET _Q61
Consists to Q ₆₃ and P-channel _{MOSFET · Q 64, Q 65,} V DD is the external power supply positive voltage. N channel MOS
Among FET, Q ₆₂ and Q ₆₃ are enhancement type FET having a standard threshold voltage V _TE (hereinafter abbreviated as EMOS), enhancement type FET Q ₆₁ is having a higher threshold voltage V _TEE than V _TE (Hereinafter abbreviated as EEMOS). Hereinafter, the operation of this circuit will be described.

The P-channel MOSFETs Q ₆₄ and Q ₆₅ share a gate and a source, and constitute a so-called current mirror circuit 70. That is, the ratio between the drain current I ₂ of the drain currents I ₁ and Q ₆₅ of Q ₆₄ operates as a constant. The current ratio (mirror ratio) is Q
Determined by the constant ratio between the ₆₄ and Q _65. Equal constants Q ₆₁ to Q _63, when both are to be operating in the saturation region,
The following three equations hold.

I ₁ = (β _EE / 2) · (V ₁ −V _TEE ) ² ··· (7) I ₁ = (β _E / 2) · (V ₁ −V _R −V _TE ) ² ··· (8) _{I 2 = (β E / 2} ) · (V R -V TE) 2 ... (9) where beta _EE conductance coefficient EEMOS (Q _61), conductance coefficient beta _E is EMOS (Q _62, Q ₆₃₎ , V ₁ is the voltage at node 61. (7) than to (9) _{below, V 1 = 2V R ... (} 10) V R = (V TEE -xV TE) / (2-x) ... (11) _{However, x = (αβ E) /} (β _EE ) (12) where α is the mirror ratio of the current mirror circuit 70 (I ₁ :
I ₂ = α: 1). In particular, when the constants of Q ₆₄ and Q ₆₅ are the same, α = 1. In this case, the β _EE ≒ β _E if _{V R = V TEE -V TE ...} (13). That, EEMOS and E as the reference voltage V _R
A voltage having a difference between the threshold voltage of the MOS and the MOS is obtained, which is a stable voltage independent of the voltage of the external power supply _VDD . Incidentally, V ₁ in place of V _R (= 2V _R) may be used as the reference voltage.

The feature of this reference voltage generating circuit is that it is easier to match the characteristics of the MOSFET as compared with the above-mentioned prior art. To operate Q _{61 to} Q ₆₃ in the saturation region, V _TEE ≧ 2V _TE , that is, V _TEE −V _TE ≧ V _TE is sufficient. This is because the threshold voltage difference V _TEE -V _TE can be made smaller (for example, 0.7 V) than before, and the difference in the impurity profile of the channel region can be made smaller than before.

In the circuit according to the present invention, the difference in the threshold voltage temperature dependence dV _T / dT can be reduced, so that a stable reference voltage can be obtained even with temperature, but the temperature dependence is further reduced. May be adjusted by adjusting the mirror ratio α. Next, the method will be described. (11) is differentiated by the temperature T of the _{equation, dV R / dT = (1} / (2-x)) · (dV TEE / dT) - (x / (2-x)) · (dV TE / dT) ... (14) Therefore, if the mirror ratio α is set so that dV _TEE / dT = x · dV _TE / dT, the temperature dependence d of the reference voltage can be obtained.
V _R / dT = 0.

It is desirable that the channel length of the MOSFET used in the present circuit is somewhat long. For example, a MOSFE having a channel length of about 1 μm in another circuit of a semiconductor device.
Even if T is used, it is preferable to use a longer MOSFET, for example, a MOSFET having a channel length of 5 μm or more. In Equations (7) to (9), for simplicity, the drain current in the saturated region depends only on the gate-source voltage. However, the drain current actually varies slightly depending on the drain-source voltage. The longer the channel length is, the smaller the rate of change (drain conductance) is, and the better the stability of the reference voltage is. Further, in order to suppress the threshold voltage fluctuation due to the short channel effect, the longer the channel length is, the better.

[0044] FIG. 1 (a), in the circuit of (b), (c) is a back gate of the MOSFET · Q ₆₁ ~Q ₆₃ for making the reference voltage is connected to each of the source, a common substrate You may make it connect to a terminal. However, MOSF
Since the threshold voltage of ET changes depending on the back gate voltage, it is better to connect to the source to avoid the influence.

Here, the current mirror circuit used in the present invention will be supplemented. Figure 1 shows the current mirror circuit.
The present invention is not limited to the circuit composed of two MOSFETs used in the embodiment of FIG. For example, the circuit shown in FIG. 1B or 1C may be used. These circuits are known under the names of cascode type and Wilson type, respectively. The feature of these circuits is that they have good mirror characteristics. That is, in the current mirror circuit of FIG. 1A, the mirror ratio α slightly changes due to a change in the drain-source voltage of Q ₆₄ and Q ₆₅ , but the circuit of FIG. 1B or FIG. Then the amount of change is small. Therefore, when applied to the present invention, the mirror ratio can be set more accurately, and a more stable reference voltage can be obtained. Also,
As the current mirror circuit, a circuit using a bipolar transistor instead of the MOSFET as shown in FIG. 1D may be used. In the following examples, for simplicity,
Although a diagram mainly using the current mirror circuit of FIG. 1A is shown, it goes without saying that the circuits of FIGS. 1B to 1D may be applied to these embodiments.

FIG. 8 shows a second embodiment of the present invention. This circuit is obtained by replacing Q ₆₃ in FIG. 1A with a resistor R ₆₁ . Equal constants Q ₆₁ and Q _62, when both the operating in the saturation region, holds the following three equations.

I ₁ = (β _EE / 2) · (V ₁ −V _TEE ) ² ··· (15) I ₁ = (β _E / 2) · (V ₁ −V _R −V _TE ) ² ··· (16) from _{I 2 = V R / R 61} ... (17) these equations, the mirror ratio alpha = 1, is calculated as _{β EE ≒ β E, V R} = V TEE -V TE ... (18) , and the reference voltage V _R As a result, a voltage having a difference between the threshold voltages of EEMOS and EMOS is obtained.

This embodiment is characterized by EEMOS and EMOS
Is smaller than that in FIG. 1A (in principle, it may be smaller). Therefore, it is easier to match the characteristics of the MOSFET. However, in a normal MOS process, the occupied area of the MOSFET can be generally smaller than that of the resistor. Therefore, when the threshold voltage difference may be somewhat large, the embodiment of FIG. 1A is more preferable.

FIG. 9A shows another embodiment of the present invention.
The difference from the embodiment of FIG. 1A lies in the method of keeping the ratio between the currents I ₁ and I ₂ constant. In the case of FIG. 1A, the current mirror circuit 70 directly keeps the ratio between I ₁ and I ₂ constant, but in the present embodiment, two sets of current mirror circuits 71 and 72 indirectly realize this. I do. That is, four N
Current mirror circuit 71 composed of channel MOSFET
(This is the cascode type described above) keeps I ₂ and I ₃ at a constant ratio, while the current mirror circuit 72 consisting of two P-channel MOSFETs keeps I ₃ and (I ₁ + I ₂ ) constant. Keep ratio. This keeps the ratio between I ₁ and I ₂ constant. For example, if the mirror ratio of the circuit 71 is I ₂ : I ₃ =
1: 1, the mirror ratio of the circuit 72 is I ₃ : (I ₁ + I ₂ ) =
If 1: 2, I ₁ : I ₂ = 1: 1.

The feature of this embodiment, the drain-source voltage of Q ₆₂ is that substantially constant. In the embodiment of FIG. 1 (a), approximately V _DD voltage of the drain (node 62) of _{Q 62 - | V TP | (} V TP is the threshold voltage of the P-channel MOSFET) is, this external supply voltage It changes according to the fluctuation of V _DD . Change in the drain voltage results in a change in the drain current due to the drain conductance, leading to fluctuations in the reference voltage V _R. In contrast, in the present embodiment, Q ₆₂
Is maintained at 2V _R , a more stable reference voltage with respect to _VDD can be obtained.

This is an embodiment having the same concept as the circuit shown in FIG. In this circuit, a current mirror circuit 73 composed of two EEMOSs keeps I ₂ and I ₄ at a fixed ratio, and a current mirror circuit 7 composed of two P-channel MOSFETs.
2 keeps the ratio of I ₁ to I ₂ constant by keeping I ₄ and (I ₁ + I ₂ ) at a constant ratio.

In each of the embodiments described above, the circuits are based on the threshold voltage difference of the N-channel MOSFET. However, the threshold voltage difference of the P-channel MOSFET can be used as the reference. FIGS. 10A and 10B show examples. Q ₇₄ is a P-channel MOSFET having a standard threshold voltage V _TP , and Q ₇₃ is a P-channel MO having a threshold voltage V _TPE lower (negative and larger in absolute value) than V _TP.
SFET. _Assuming that both _Q74 and Q73 operate in the saturation region, the following two equations hold.

[0053] _{I 1 = (β PE / 2} ) · (-V 3 -V TPE) 2 ... (19) I 2 = (β P / 2) · (V R -V 3 -V TP) 2 ... (20 Where V ₃ is the voltage at node 63 and β _PE and β _E are Q
₇₃ and _Q74 are conductance coefficients. The equation of _{Korara, I 1: I 2 = 1} : 1, β PE ≒ is calculated as _{β E, V R = V TP} -V TPE ... (21) becomes, as a reference voltage V _R of the P-channel MOSFET threshold Value voltage difference is obtained.

This embodiment is suitable for being incorporated into a semiconductor integrated circuit formed on a P-type substrate, which requires a stable reference voltage. As described above, it is desirable that the back gate of the MOSFET for generating the reference voltage be connected to each source. However, in a semiconductor integrated circuit on a P-type substrate, the N-channel MOSFET is usually formed directly on the substrate, and all its back gates are connected to a common substrate terminal. Therefore, when the substrate voltage changes, the threshold voltage of the N-channel MOSFET changes. On the other hand, P-channel MOSFET
Is formed in an N-type well, so that by connecting the back gate (well) of each MOSFET to the source, the influence of the substrate voltage fluctuation can be prevented. For example, in a DRAM, it is common to use a P-type substrate and apply a voltage (usually about −3 V) generated by a substrate voltage generation circuit provided on a chip to the substrate. However, the substrate voltage is liable to fluctuate due to the fluctuation of the external power supply voltage or the operation of the memory. In such a case, the circuit of this embodiment is particularly effective. Conversely, in a semiconductor integrated circuit formed on an N-type substrate, a circuit based on the threshold voltage difference of an N-channel MOSFET is better.

FIG. 10B similarly shows a P-channel MOSF.
This is a circuit based on the threshold voltage difference of ET. The difference from the previous embodiments lies in the method of setting the operating point (operating current). In the embodiments described above, the so-called self-bias circuit is used in which the operating point is automatically determined in the reference voltage generating circuit. However, in this circuit, a circuit 76 for setting an operating point is provided independently. The current I ₅ flowing through the operating point setting circuit 76, mainly resistors R ₆₂ (MO
SFET). Operating currents I ₁ and I ₂ of the reference voltage generating circuit are determined by I ₅ and two sets of current mirror circuits 72 and 75. For example, if the mirror ratio of the circuit 72 is I ₅ : (I ₁ + I ₂ ) = 1:
2. If the mirror ratio of the circuit 75 is I ₅ : I ₂ = 1: 1,
I ₁ = I ₂ = I ₅ .

This circuit is characterized in that the operating point setting circuit is independent, so that the operating point varies less due to device variations and therefore the current consumption varies less than the self-bias circuit.

It is desirable that a self-biasing circuit be provided with a starting circuit. The starting circuit is a circuit for preventing the circuit from falling into an undesirable stable point. For example, in the circuit of FIG. 9A, a desirable stable point is a state where V _R is normally generated as described above. At this time, the voltage V _{3 of the} node 63 = 2V _R ,
V ₄ ≒ V _DD − | V _TP | However, there is another stable point of I ₁ = I ₂ = 0. At this time, V ₃ =
0, V ₄ = V _DD , VR = 0. To prevent the circuit from falling into this stable point, for example, a starting circuit 77 as shown in FIG. 11 may be provided. P-channel MOSFET
Q ₇₅ , Q ₇₆ and resistor R ₆₃ (which may be replaced by a MOSFET) constitute a current source. Since when in the stable point circuit is undesirable EEMOS · Q ₇₇ at V ₃ = 0 is very communication state, node 60 is charged by the current source. Then Q ₇₈ is in a conductive state increases the voltage at node 63 acts to escape from stable point undesirably circuit. When the circuit reaches the desired stability point, V
₃ goes above V _TEE and Q ₇₇ conducts, causing the voltage at node 60 to drop. Then, _Q78 becomes non-conductive, and does not affect the operation of the reference voltage generating circuit main body.

Next, an example in which the present invention is applied to a DRAM will be described. FIG. 12 is a configuration diagram of a DRAM provided with an on-chip voltage limiter in order to operate the memory array at an internal voltage _VL lower than the external power supply voltage V _CC . Internal voltage V
_In order to generate _L , the reference voltage generation circuit according to the present invention is used. In the figure, 6 is a reference voltage generating circuit according to the present invention, 24 is a differential amplifier, 7a and 7b are buffers, 3
0 is a word line booster circuit, 2 is a memory array in which memory cells MC are arranged vertically and horizontally, 33 is a sense amplifier, and 31 is a word driver.

The differential amplifier 24 and the two resistors R ₂₁ and R
_22, the output voltage V _R of the reference voltage generating circuit 6 is a circuit for producing an operating voltage V _R 'of the memory array as shown in the following equation.

V _R ′ = ((R ₂₁ + R ₂₂ ) / (R ₂₂ )) · V _R (22) Since V _R is based on the threshold voltage difference of the FET as described above, the memory is not necessarily used. The voltage is not always appropriate as the operating voltage of the array. And performs conversion to V _R 'from V _R by the circuit for that. For example,
If V _R = 1 V and V _R ′ = 3 V, then R ₂₁ : R ₂₂ = 2: 1 may be set. Also, the R ₂₁ and R ₂₂ variable, the fine adjustment of V _R ', may be so-called trimming. As the trimming method, for example, the method described in the aforementioned US Patent can be used.

[0061] buffers 7a and 7b is a circuit for increasing the current driving capability of the V _R '. Buffer is MO
A differential amplifier consisting of SFET · Q ₂₁ ~Q ₂₄ and the current source I _25, is constituted by an output stage composed of MOSFET · Q ₂₆ and a current source I _27. Since the configuration of 7b is the same as that of 7a, it is omitted in the figure. Since feedback is applied from the output stage to the input of the differential amplifier, this circuit operates so that the voltages of the outputs V _L1 and V _L2 follow the input voltage V _R ′. That is, it is possible to obtain the outputs V _L1 and V _L2 having a large driving ability without _changing the voltage value. V
_L1 and V _L2 are used to drive a sense amplifier and a word line of a memory cell, respectively. In this embodiment, a method called word boost is used, in which the word line voltage is made higher than the operating voltage of the memory array (here, V _L1 ). For this purpose, a word line boosting circuit 30 is provided.
For this purpose, a word line boosting circuit 30 is provided. However, the power supply of 30 is not the external power supply V _CC but the internal power supply V _L2
It is. Therefore, the word line drive signal φ _X is boosted based on V _L2 . Word driver 31 receives φ _X and decoder output XD, and drives word line WL.

The sense amplifier 3 used in this embodiment
3 is a normal CM comprising P-channel MOSFETs Q ₁₂₅ and Q ₁₂₆ and N-channel MOSFETs Q ₁₂₇ and Q _128.
An OS sense amplifier. 33 sets φ _S to a high level,
It is activated by lowering / φ _S to make the MOSFETs Q ₁₃₆ and Q ₁₃₇ conductive. However, the source of Q ₁₃₇ is because it is connected to the external power supply V in _CC without an internal power supply V _L1, by 33 to operate, the high level side of the data line in V _L1, the low level side is ground potential Become. That is, the amplitude of the data line is suppressed to _VL1 .

Next, another embodiment in which the present invention is applied to a DRAM will be introduced. FIG. 13 is a circuit diagram of a 16 Mbit DRAM to which the present invention is applied, FIG. 14 is a layout diagram in a chip,
FIG. 15 is a detailed layout diagram of the voltage limiter 13.
In the layout diagram, some circuits are omitted for simplicity. In the figure, 1 is a semiconductor chip, 2
Is a memory array, 31 is a word driver, 32 is a row decoder, 33 is a sense amplifier, 34 is a data line precharge circuit, 35 is a data line selection circuit, 36L and 36
R is a switch circuit, 37 is a column decoder, 38 is a main amplifier, 39 is a data output buffer, 40 is a data input buffer, 41 is a write circuit, 42 is a row address buffer, 43 is a column address buffer, 44 is a timing generation circuit, 45 is a sense amplifier drive signal generation circuit,
46 is a word line voltage generation circuit, 47 is a data line precharge line pressure generation circuit, and 48 is a substrate voltage generation circuit. Reference voltage generating circuit 6 according to the invention in the voltage limiter circuit 13, 6a voltage conversion circuit, 7a, 7b, 7c are drive circuit, 4a, 4b, 4c the bonding pads of the ground V _SS, 5a, 5b external This is a bonding pad for the power supply voltage V _CC . Reference voltage generation circuit 6 generates a regulated voltage V _R (1.1V in this case) with respect to (5V in this case) the external power supply voltage V _CC, the voltage converter 6a each V _R '
(In this case, 3.3V). The drive circuit generates a power supply voltage V _L1 for a memory array and a power supply voltage V _L2 for a peripheral circuit based on V _R ′. In this example, the voltage levels of V _L1 and V _L2 are both 3.3V.

The first feature of this embodiment is that a voltage limiter circuit is also applied to a peripheral circuit. V _L1 is 45 and 47, and V _L2 is 32, 37, 38, 40, 41, 4
2, 43, 44, 46, and 48, respectively. That is, circuits other than the data output buffer 39 operate at the internal power supply voltage V _L1 or V _L2 . By operating the peripheral circuit also at the stabilized voltage V _L1 lower than the external power supply voltage V _CC , the power consumed by the peripheral circuit can be reduced and the operation can be stabilized.

A second feature of the present embodiment is that the voltage limiter circuit 13 is arranged at the center of the semiconductor chip. As a result, the internal power supply voltages V _L1 , V _L2 wirings 11a, 11L
The voltage drop due to the impedance b becomes small. Therefore, the operation of the circuit using V _L1 and V _L2 as the power supply becomes stable and high speed.

The third feature of this embodiment resides in a method of ground wiring. First, a dedicated short ground wiring 8 is provided for the reference voltage generation circuit and the voltage conversion circuit. Next, ground wirings 9a and 9b are provided for the driving circuit. The bonding pad 4b for the voltage limiter circuit is
It is provided separately from the bonding pads 4a and 4c for other circuits. Thus, it is possible to prevent the noise generated on the ground wiring due to the current flowing when each circuit operates from affecting the other circuits. In particular, if noise is generated in the ground wiring of the reference voltage generation circuit and the voltage conversion circuit, the levels of the internal power supply voltages V _L1 and V _L2 fluctuate and affect almost all circuits in the chip. It is desirable to keep the distance as short as possible and separate it from other ground wiring. For this purpose, it is most preferable to separate the bonding pads from the bonding pads. However, a method may be used in which the bonding pads are commonly used and separated from the wiring extraction portion. Although not shown in the figure, it is desirable that the ground wiring for the memory array be separated from other wirings.
This is because, in a DRAM, when the sense amplifier performs an amplifying operation, a large number of data lines (the capacity of which is typically several thousand p
F) is charged and discharged at the same time, and large noise is generated in the ground wiring.

The fourth feature of the present embodiment lies in the method of power supply wiring. The bonding pad for the external power supply voltage V _CC
5a for the memory array and 5b for the peripheral circuit are separately provided. The drive circuit 7a for the memory array is arranged near 5a, and the drive circuits 7b and 7c for the peripheral circuits are arranged close to 5b. Thereby, the voltage drop at the power supply voltages 10a and 10b can be reduced. Of course, this voltage drop is adapted to absorb the respective driving circuits, drop ceases completely absorbed too large, resulting in deterioration of the internal power supply voltage V _L1 or V _L2. In order to prevent this, it is desirable to reduce the impedance of the wirings 10a and 10b as in this embodiment. The reason why bonding pads are separately provided for the peripheral circuit and the memory array is that, similarly to the case of the above-mentioned grounding, noise generated on the power supply line due to current flowing when the circuit operates adversely affects other circuits. This is to prevent giving. The power supply for the reference voltage generation circuit and the voltage conversion circuit is wired from 5b here, but of course another bonding pad may be provided.

Although not shown in the figure, it is desirable that the ground wiring and the power supply wiring for the data output buffer are also separated from the other ground wirings and the power supply wiring. Because, when the data output buffer operates, an external load (usually several hundred pF) is charged and discharged, so that a large noise is generated on the ground wiring and the power supply wiring (the data output buffer operates directly at the external power supply voltage V _CC ). Because you do.

Hereinafter, each part of this embodiment will be described in detail.

First, the reference voltage generating circuit 6 will be described. As the reference voltage generating circuit, FIGS.
The circuits shown in FIGS. 8 to 11 can be used. Here, as described above, in order to reduce the influence of the substrate potential fluctuation, it is desirable that the back gate of each MOSFET is connected to each source. For example, FIG.
In the circuits (a) and (b), a P-channel MOSFET
Threshold voltage difference between Q ₇₃ and Q ₇₄ is the reference voltage V _R.
In this case, as Q ₇₃ and Q ₇₄ , for example, FIG.
A P-channel MOSFET having the structure shown in FIGS. FIG. 16A is a layout diagram, and FIG.
(B) is a sectional view. In the figure, 101 is a P-type semiconductor substrate, 102 is an N-type well, 103 is an N + diffusion layer,
7 is a P + diffusion layer, 104 is SiO for isolation.
₂ and 106 are polycrystalline silicon or metal serving as a gate, 113 is an interlayer insulating film, 108 is a wiring layer, 115 is a protective film, and 116 is a contact hole. The source diffusion layer (the P + diffusion layer on the left side in the figure) and the N well are connected by the wiring layer 108. This terminal is shown in FIG.
This corresponds to the node 66 in the circuit diagram of FIG. This structure can be made by a normal CMOS process. FIG.
(A), (b) is an example in which the well has a double structure.
In the figure, 111 is an N-type substrate, and 112 is a P-type well. In this way, by forming the well into a double structure and fixing the potential of the outer well 112 (for example, grounding), the substrate 111 and the back gate 102 of the MOSFET are electrostatically shielded. Therefore, it is possible to prevent interference noise via a parasitic capacitance between them, and it is possible to almost completely eliminate the influence of substrate potential fluctuation. The substrate 1
11 may be connected to, for example, an external power supply V _CC . This structure can be made by adding only one step of forming a well to a normal CMOS process, and a great effect can be obtained at a relatively low cost.

FIGS. 1 (a) to 1 (d), FIGS. 8, 9 (a),
(B) In the circuit of FIG. 11, the N-channel MOSFET Q
Threshold voltage difference between the ₆₁ and Q ₆₂ is a reference voltage. When these circuits are used, the N type having the structure in which the conductivity type is reversed in FIGS. 16A and 16B or FIGS.
A channel MOSFET may be used.

A pair of MOSFs for generating a reference voltage
In the case of ET FIGS. 10 (a) and 10 (b), Q ₇₃ and Q ₇₄ , FIG.
(A) ~ (d), 8, FIG. 7 (a), the layout pattern of (b), Q ₆₁ and Q ₆₂ in the case of FIG. 11) is to geometrically congruent figures, also the direction of placing It is desirable that they be the same in order to reduce the influence of manufacturing process variations. For example, by making the arrangement method of the contact holes on the source / drain diffusion layers the same, the influence of the diffusion layer resistance can be made the same. In addition, by making the channel direction the same, the influence of the difference in mobility depending on the crystal plane direction can be eliminated.

Next, the voltage conversion circuit 6a will be described.
FIG. 18 shows one implementation method of the voltage conversion circuit. In the figure, 24
Is a differential amplifier, 25 is a trimming circuit, Q _{39 to} Q ₄₇ and Q ₄₉ are P-channel MOSFETs, and F _{4 to} F ₇ are fuses. Embodiments related to this are shown in FIGS.
9 (a), which will be more apparent upon reference to this. This circuit generates a voltage V _R 'constant multiple of the reference voltage V _R. Also, fine adjustment of the voltage to compensate for variations in V _R due to the manufacturing process (trimming) is possible.

One of the input terminals of the differential amplifier 24 has V
_R is input, and V _R ′ is connected to MOSFETs Q _{44 to} Q _{47 on the other side.}
And the voltage V _R ″ divided by Q _{39 to} Q ₄₂ is fed back. If the amplification factor of 24 is sufficiently large, the output voltage V _R ′ is given by the following equation.

[0075] _{V R '= ((R T1} + R T2) / R T2) · V R wherein, R _T1 resistance value when regarded as equivalent to resistance circuit consisting of Q ₄₄ ~Q _47, R _T2 Is the resistance value when the circuit consisting of Q _{39 to} Q ₄₂ is equivalently regarded as a resistor. By cutting the fuse, R _T1 and R _T2 change.
_R ′ can be adjusted. Standard values of V _R, V _R 'is,
Since the voltages are 1.1 V and 3.3 V, respectively, as described above, R _T1 : R _T2 = 2: 1 when the fuse is not cut. When V _R > 1.1 V, R _T2 is increased by cutting F _{4 to} F _6, and when V _R <1.1 V, R _T1 is increased by cutting F ₇ to increase V _R. 'Can be adjusted so that it does not greatly deviate from the standard value.

[0076] MOSFET · Q ₄₉ and Q ₅₀ is for the V _R '= 0V when the test mode. In the test mode, the signal _TE is at the V _CC level, and the output V _R ′ is at 0 V.

The circuit shown in FIG.
In comparison with the circuit described in
There is an advantage that the area occupied by the S process is small. That is, in the circuit described in U.S. Patent, as an element for dividing the output voltage V _R ', whereas have used resistors in the circuit of Figure 18 is MOSFET
Is used. In order to reduce the current consumption of the circuit, the equivalent resistance of the voltage dividing element must be considerably large (about several hundred kΩ). In a normal MOS process, an element having a smaller area and a larger equivalent resistance can be obtained with a MOSFET than with a resistor. However, if MOSFET is used,
There is a concern that the characteristics of V _R ′ may fluctuate due to the fluctuation of the threshold voltage. However, the channel width and channel length of the MOSFET are made sufficiently large to suppress the fluctuation, and the back gate is connected to the source to change the substrate potential. Can be solved by avoiding the effect of the above and selecting the fuse cutting method in consideration of the variation of the threshold voltage. The MOSFET used for this trimming is shown in FIGS. 16A and 16B or FIG.
It is desirable to use the structure shown in FIGS. 7 (a) and 7 (b).

It is desirable to add a large-capacity capacitor between the terminals of the reference voltages V _R and V _R ′ between the terminals and the ground. This is to reduce the impedance of V _R and V _R ′ to high frequencies and to bypass high frequency noise. In particular, as shown in FIG. 15, when the V _R ′ wiring 12a inevitably intersects with other wirings, it also has the meaning of stabilizing the operation of the voltage limiter circuit (preventing oscillation). The reason will be described with reference to FIG.

The driving circuits 7a and 7b respectively generate voltages V _L1 and V _L2 having large current driving capability from V _R '. This V
_L1 , V _L2 itself, or V
The output of the circuit which operates the _L2 as the power supply (the voltage level V _L2) wiring 16 of V _R 'wiring is, V _R' wire 12a of
When they intersect with each other, a feedback loop occurs via the parasitic capacitance C _C3 between the wirings as shown by 17a to 17c. If the gain of this loop is greater than 1 (0 dB), the circuit will oscillate,
If the margin is small even if it is smaller than 1, the circuit operation becomes unstable. In order to prevent this, C _R is connected between VR 'and ground.
Capacitors C _R1 and C _R2, which are sufficiently larger than _{C 1 to} C _C3 , may be inserted to make the loop gain sufficiently small (for example, -10 dB or less).

FIGS. 20A and 20B show an example of a method of realizing the capacitor used here. FIG. 20A is a layout diagram, and FIG. 20B is a sectional view. In the figure, 101 is a P-type semiconductor substrate, 102 is an N-type well, and 103 is N
+ Diffusion layer 104 is SiO ₂ for isolation, 1
05 is a gate insulating film, 106 is polycrystalline silicon or metal serving as a gate, 113 is an interlayer insulating film, 108 is a wiring layer, 115 is a protective layer, and 116 is a contact hole. The capacitor has a gate 106 and a substrate surface 102 sandwiched by a gate insulating film in the same manner as a normal MOS capacitor.
a is formed between them. Since a thin gate insulating film is used as the capacitor insulating film, it is characterized in that a large capacitance can be obtained in a relatively small area. However, the usual M
The difference from the OS capacitor is that the threshold voltage (flat band voltage) is negative because there is an N well under the gate. Therefore, as long as a voltage in one direction is applied so that the gate side becomes positive, there is a characteristic that the power collection capacity is almost constant. The steps required to make this capacitor are well formation, isolation area formation, gate insulation film formation, gate formation, diffusion layer formation,
And the steps of wiring, all of which are steps included in a normal CMOS process. Therefore, if the semiconductor device is manufactured by a CMOS process,
There is no need to add any additional steps to make this capacitor.

FIG. 21 shows a method for realizing the driving circuits 7a and 7b.
(A). In the figure, reference numeral 21 denotes a differential amplifier,
Consisting of FET · Q ₂₁ ~Q _25. 22 is an output stage;
Consisting of OSFET · Q ₂₆ ~Q _{27. CL} is equivalent to a load of a drive circuit (memory array or peripheral circuit) expressed by one capacitor. One of the two input terminals of the differential amplifier 21 receives the reference voltage V _R ', and the other receives V _L1 (V _L2 ) from the output stage. Therefore, this circuit operates such that V _L1 (V _L2 ) follows V _R ′. Reference numeral 23 denotes a so-called phase compensation circuit for stabilizing the operation of the feedback amplifier composed of 21 and 22. MOSFET · Q ₂₈ ~Q _30, the drive circuit for a high impedance output when inactive, and V _L1 a (V _L2) in order to V _CC level when the test mode. That is, when in the inactive state, the test signal TE is at a low level, the activation signal φ ₁ ′ (φ ₂ ′) is at a low level, and the gate is at the level of the gate V _{CC of} Q ₂₆ , and the output V
_L1 (V _L2 ) becomes high impedance. Further, at this time, since Q ₂₅ and Q ₂₇ are turned off, the power consumption of the circuit is reduced. When the test mode, TE becomes V _CC level, the gate of Q ₆ goes low, V _CC is output directly. FIG. 21 (b) shows a method for realizing the driving circuit 7c.
Shown in Also in this circuit, when the activation signal φ ₃ ′ is at a low level, the output has a high impedance. Note that the phase compensation circuit of this time can be shared with that of 7b (7b and 7c
Are connected in parallel), so no phase compensation circuit is provided here.

As described above, the drive circuit 7a sets V _L1 to 7
b and 7c are circuits for generating V _L2 . In the normal state, 7c is always activated, and 7a and 7b are activated only when the memory is in operation. Therefore, the activation signal phi ₃ 'is always V _CC level, phi _1' and the phi ₂ 'V according below for details of the operation timing (timing of the memory _CC
Become a level. In the test mode, φ ₁ ′, φ ₂ ′,
φ ₃ ′ are all low, and the test signal TE is V _CC
Become a level. At this time, both V _L1 and V _L2 become equal to V _CC . This is effective for directly applying an external power supply voltage to check the operation of the memory (for example, the power supply voltage dependence of the access time). Immediately after power-on, it is desirable to activate all of φ ₁ ′, φ ₂ ′, and φ ₃ ′ in order to speed up the rise of V _L1 and V _L2 . As described later, V _L2 is used to generate the word line voltage V _CH and the substrate voltage V _BB . Therefore, by activating φ ₂ ′ when the voltage levels of V _CH and V _BB deviate from the standard values, the stability of these voltages can be improved. The reason why the high levels of the activation signals φ ₁ ′, φ ₂ ′, φ ₃ ′ and the test signal TE are not V _L2 but V _CC is that the P-channel MOSFETs Q ₂₈ and Q ₂₉ are surely non-conductive. It is in order to make a state.

The drive circuits 7a and 7b must have a large current drive capability. When the memory is active, 7
This is because a and 7b need to drive a large (several hundred to several thousand pF) load capacitance. In particular, when the sense amplifier performs an amplifying operation, a large number of data lines must be driven. For example, if the capacity of one data line is 0.3p
F, assuming that the number of sense amplifiers operating simultaneously is 8192, the total capacitance is 2500 pF. Therefore, 7
a, as the output MOSFET · Q ₂₆ of 7b, for example, the channel width / channel length used of about 3000 .mu.m / 1.2 [mu] m. 7c is only required to have a current driving capability enough to guarantee a leak current when the memory is in a standby state, and its output MOSFET is 100 μm / 1.2 μm
Degree is fine.

The connection circuit 15 is for preventing the potential difference between V _L1 and V _{L2 from} becoming too large. V _L2
This is because if the potential difference between the memory array and V _L1 is large, a mismatch in transmission and reception of signals between the memory array and the peripheral circuits may occur. FIG. 22 shows an example of this circuit. In the figure, Q ₁ , Q ₂ ,
Q ₅ is an N-channel MOSFET, Q ₄ is a P-channel MOS
FET. Assuming that the threshold voltage of the N-channel MOSFET is V _TN , Q ₁ is Q ₂ when V _L1 −V _L2 > V _TN
Conduct when V _L2 −V _L1 > V _TN . Therefore, the potential difference between V _L1 and V _L2 is kept within V _TN . Q
_The signal WK, which goes high only immediately after the power is turned on, is input to the gate ₅ . This is particularly effective in preventing a potential difference from occurring when the load time constants of V _L1 and V _L2 are significantly different. Relatively small MOSF of Q _1, Q _2, conductance in any case be non-conduction of Q ₅
ET · Q ₄ is conducting. This serves, for example, as V _L1 = V _L2 while the memory is in a standby state.

In the memory array 2, the MOSFET Q
_A so-called one-transistor, one-capacitor dynamic memory cell MC _ij comprising ₁₂₁ and a capacitor C ₁₂₂ is
They are arranged at intersections of the word lines WL _i and the data lines DL _j. Although only two word lines and one pair of data lines are shown in the figure, a large number of word lines are actually arranged in a matrix. One end PL (plate) of the capacitor _C122 is connected to a direct current. Although the voltage level is arbitrary, the capacitor C ₁₂₂
From the viewpoint of the withstand voltage of the memory array,
2, that is, V _L1 / 2 is desirable.

The word driver 31 includes a row decoder 32
And a circuit for driving the selected word line in response to the output of In this embodiment, the word line voltage is set higher than the operating voltage of the memory array (here, V _L1 = 3.3 V). A so-called word line boosting method is employed. The advantage of this method is that the storage voltage of the memory cell can be increased. Therefore, the voltage V _CH (V _CH > V _L1 ) generated by the word line voltage generation circuit 46 is supplied to the selected word line.

The sense amplifier 33 is a circuit for amplifying a small signal on the data line, and is an N-channel MOSFET.
It is composed of a flip-flop composed of T · Q ₁₂₅ and Q ₁₂₆ and a flip-flop composed of P-channel MOSFETs Q ₁₂₇ and Q ₁₂₈ . MOSFET Q ₁₃₆ sense amplifier high levels phi _S, a / phi _S as a low level, Q
It is activated by making ₁₃₇ conductive.

[0088] Data line precharge circuit 34 is a circuit for prior to reading a memory cell sets each data line to a predetermined voltage V _P. By applying the precharge signal φ _P, MOSFETQ ₁₂₉ ~Q ₁₃₁ becomes conductive, the voltage of the data line DL _j / DL _j is equal to V _P. The data line precharge voltage V _P can be any voltage, but in view of reducing the data line charging and discharging current, one half of the operating voltage of the memory array, i.e. V _L2 /
It is desirable to set it to 2.

Receiving the output φ _YS of column decoder 37, data line selecting circuit 35 sets the selected data line pair to MO.
Input / output lines I / O and / I through SFETs Q ₁₃₂ and Q ₁₃₃
/ O circuit. In this embodiment, by using the technique of column decoder 37 is arranged only one on the end, that distributes the output phi _YS to a plurality of data line selection circuit, so-called multi-divided data lines. This is effective for reducing the area occupied by the column decoder.

In this embodiment, the sense amplifier 33, the data line precharge circuit 34, and the data line selection circuit 35 are shared by the left and right memory arrays.
A technique called shared I / O is employed. This is effective in reducing the area occupied by sharing 33, 34, 35. Therefore, switch circuits 36L and 36R controlled by switch signals φ _SHL and φ _SHR are provided between the memory array and 33, 34, 35.

Main amplifier 38, data output buffer 3
9, a data input buffer 40, and a write circuit 41 are circuits for inputting and outputting data. In the case of reading, the data latched in the sense amplifier 33 is input / output lines,
Via the main amplifier 38 and the data output buffer 39,
The data is output to the data output terminal Dont. For writing,
Data input from the data input terminal Din is set to an input / output line via a data input buffer 40 and a write circuit 41, and further written to a memory cell via a data line selection circuit 35 and a data line. In this embodiment, as described above, the power supplies 38, 40, and 41 are operated at the internal power supply voltage V _L2 to reduce power consumption and stabilize the operation. Only the data output buffer 39 has an external power supply voltage V _CC for convenience of the external interface (TTL compatible here).
(= 5V).

The row address buffer 42 and the column address buffer 43 are circuits that receive an external address signal A and supply the row decoder 32 and the column decoder 37 with address signals, respectively. Timing generation circuit 44
Is a circuit which receives external control signals / RAS, / CAS, / WE and generates a timing signal necessary for the operation of the memory. These circuits are also operated at _VL2 with the internal power supply voltage to reduce power consumption and stabilize operation.

The word line voltage generation circuit 46 is a circuit for generating the word line voltage V _CH (about 5 V here) as described above (this voltage is also used in the switch circuit as described later). Data line precharge voltage generation circuit 47
The data line precharge voltage V _P) (here 1.65
V). The substrate voltage generation circuit 48
This is a circuit that generates a voltage V _BB (here, −2 V) applied to the semiconductor substrate. The power supply for these circuits is stabilized V _L1 or V _L2 instead of V _CC . for that reason,
There is an advantage that the output voltage does not fluctuate even if V _CC changes.

Next, the operation of the DRAM in the case of reading will be described with reference to the operation waveform diagram of FIG.

In the standby state (both / RAS and / CAS are high), data line precharge signal φ _P and switch signals φ _SHL and φ _SHR are both high (= V _L2 ).
, And the data lines DL, / DL is set to V _P. The sense amplifier driving signal phi _SAN, phi _SAP and the input-output lines I / O, / I / O has to be V _P is precharged (these precharge circuit is not shown in FIG. 13). In this state, out of the drive circuit activation signals of the voltage limiter, only φ ₃ ′ is at a high level (= V _CC ), φ ₁ ′,
φ ₂ ′ is at a low level. Therefore, only the standby driving circuit 7c with low power consumption is activated, and thereby the level of the internal power supply voltage V _L2 is maintained. Also, the level of V _L1 is held through the connection circuit 15. High current drive capability but high power consumption 7
a and 7b are inactive. By doing so, power consumption during standby can be reduced.

When / RAS goes low, the drive circuit activation signal φ ₂ ′ for the peripheral circuit goes high (= V _CC ).
become. As a result, 7b having a large current driving capability is activated, and a large current can be supplied to a peripheral circuit that operates using V _L2 as a power supply. Precharge signal phi _P goes low (= 0V), (in the case of FIG. 23 phi _SHL) of memory array side selected switch signal is boosted to V _CH levels, the other side of the switch signal (FIG. 23 In this case, φ _SHR becomes 0V. The reason for _raising φ _SHL is as follows. Although the voltage amplitude of the sense amplifier is V _L1 as described later, when the level of φ _SHL is V _L2 , the voltage amplitude of the data line decreases to V _L2 −V _TN, and as a result, the storage voltage of the memory cell also decreases. V _L2 −V _TN (V _TN is N
Threshold voltage of channel MOSFETs Q ₁₂₃ and Q ₁₂₄ ). This can be prevented by boosting φ _SHL, and the storage voltage of the memory cell can be secured.

[0097] Next, when the row address buffer 42 and row decoder 32 is operated, is selected one word line WL _i, its voltage becomes V _CH. Signal charge to each data line from each memory cell on WL _i is read, the potential of the data line changes. Operation waveforms of FIG. 18 is an example in which the capacitor in advance the high potential of the memory cell (≒ V _L1) is accumulated, the potential of the data line DL _j is increased slightly, between / DL _j A potential difference has occurred.

Prior to the operation of the sense amplifier, the drive circuit activation signal φ ₁ ′ for the memory array is set to a high level (=
V _CC ). As a result, the drive circuit 7a is activated, and a large current can be supplied to the sense amplifier drive signal generation circuit 45 that operates using V _L1 as a power supply. Next, φ
_S goes high (= V _L2 ) and / φ _S goes low (= 0 V). As a result, the MOSFETs Q ₁₃₆ and Q ₁₃₇ become conductive, φ _SAN is grounded through Q ₁₃₆ , and φ _SAP is connected to V _L1 through Q ₁₃₇ . As a result, a minute potential difference between the data lines DL _j / DL _j is amplified, and one (DL _{j in} FIG. 23) becomes _VL1 and the other (/ _{J in} FIG. 23).
DL _j ) becomes 0V.

When / CAS goes low, the column address buffer 43 and column decoder 37 operate to select one data line. As a result, the data line selection signal _φYS becomes high level (= V _L2 ), and the data line is connected to the input / output line through the data line selection circuit 35. The data latched by the sense amplifier 33 is output to the data output terminal Dont via the input / output line, the main amplifier 38, and the data output buffer 39.

[0100] The / RAS returns to a high level, first made the word line WL _i is at a low _{level, φ S, / φ S,} φ SHL,
φ _SHR and φ _P return to the original level. The drive circuit activation signal φ ₁ ′ for the memory array is at a low level (= 0 V) here.
, And the drive circuit 7a becomes inactive. further,/
When CAS returns to the high level, the drive circuit activation signal φ ₂ ′ for the peripheral circuit also goes to the low level (= 0 V), and the drive circuit 7
b becomes inactive.

As is clear from the above description, the activation signals φ ₁ ′ and φ ₂ ′ of the drive circuit go high only when required. That is, φ ₁ ′ changes from immediately before the start of the operation of the sense amplifier until / RAS returns to a high level.
φ ₂ 'goes high when / RAS or / CAS is low, respectively. Thereby, the driving circuit 7
Reduction of the power consumed by a and 7b can be realized.

As described above, according to this embodiment,
A reference voltage generating circuit can be made without using a depletion type FET and using a threshold voltage difference between enhancement type FETs as a reference. Enhancement type F
Matching the characteristics of the ETs is easier than matching the characteristics of the depletion-type and enhancement-type FETs, so that a more stable reference voltage can be obtained than in the past. Therefore, for example, when applied to the above-described voltage limiter of the memory LSI, a more stable internal power supply voltage can be generated.

[Second Group] Embodiments of the second group of the present invention will be described below with reference to the drawings. In the following description, an example in which the present invention is mainly applied to a semiconductor device based on MOS technology will be described. However, the present invention can be applied to other semiconductor devices, for example, a semiconductor device based on bipolar or BiCMOS technology. The case where the external power supply voltage and the internal power supply voltage are positive will be described. However, even when the external power supply voltage and the internal power supply voltage are negative, the present invention can be applied by reversing the polarity of the transistor.

First, the basic concept of the second group will be described.

FIG. 24 shows this embodiment. In the figure, VL is a voltage limiter circuit which generates internal power supply voltages V _{L1 to} V _L3 (hereinafter, described as V _Li (i = 1, 2, 3)) from the external power supply voltage V _CC . Voltage limiter circuit VL is a reference voltage generating circuit VR and the drive circuit B ₁ ~B ₃ (hereinafter B _i (i =
1, 2, 3). Reference voltage generating circuit VR generates the external power supply voltage V _CC and fluctuation due to a temperature less stable voltage V _R, the driving circuit B _i (B ₁ ~B ₃₎
Generates a large voltage V _L1 of the current driving capability on the basis of V _R. Each drive circuit B _i includes a feedback amplifier A _i and a phase compensation circuit C _i (i = 1, 2, 3). Z ₁ to Z ₃ is a circuit in the semiconductor device as a load of the voltage limiter circuit VL, it operates as a power source V _L1 ~V _L3, respectively. φ ₁ ~
phi ₃ is a timing signal for controlling the load circuit Z ₁ to Z _3, respectively. φ ₁ '~φ _3' is a timing signal synchronized with phi ₁ to [phi] _3, respectively.

[0106] The first feature of this embodiment is that the internal circuit as a load of the voltage limiter circuit and three divided in Z ₁ to Z _3, driving circuits B ₁ .about.B in the voltage limiter circuit in response thereto ₃ is divided into three parts, and each of them is subjected to phase compensation. Generally, circuits in a semiconductor device include a very wide variety of circuits such as a capacitance, a resistance, an inductance, a nonlinear element, or a combination thereof. Moreover, they are dispersed on the semiconductor chip (ie, distributed constant).
Exists. Phase compensation for stably operating a feedback amplifier having such a complicated load is extremely difficult. If the load circuit is divided into a plurality of types and sizes as in this embodiment, it becomes relatively easy to design a feedback amplifier and a phase compensation circuit suitable for each load circuit. Thereby, the operation of each drive circuit can be stabilized.

As a method of dividing the load circuit, for example, the following method can be considered.

A method of dividing into a resistive load and a capacitive load.

A method of dividing according to the size of the load (current consumption).

A method of dividing according to the operation timing of a circuit.

A method of dividing a circuit according to a physical position in a semiconductor chip.

In the case of division according to physical positions, it is desirable to disperse the drive circuits B _{1 to} B ₃ as necessary.

The second feature of this embodiment is that each drive circuit B _i
, A signal φ _i ′ synchronized with the timing signal φ _i for controlling each load is input. Generally, a current flowing through a circuit in a semiconductor device greatly changes depending on an operation mode. This means that the impedance of the load changes from the power supply side. In order to be able to cope with such a load change, in this embodiment,
The timing signal φ _i ′ is used. changing the circuit constant of the feedback amplifier A _i and the phase compensation circuit C _i by phi _i ', can always be the characteristics adapted to the operating mode of the load. Thereby, the operation of the drive circuit can be always stabilized.

In this embodiment, the levels of the operating voltages V _{L1 to} V _L3 of the load circuits Z _{1 to} Z ₃ are all equal. Therefore, the reference voltage generating circuit is only one provided, and commonly use the output V _R by the drive circuit B ₁ .about.B _3. When the operating voltage differs depending on the load circuit, a plurality of reference voltage generating circuits may be provided as shown in FIG. Alternatively, only one reference voltage generating circuit is provided, and the driving circuits B ₁ to B ₁ to
A voltage conversion mechanism may be provided in the B _3.

FIG. 26 shows another embodiment of the present invention. The feature of this embodiment, corresponding to the operation mode of the load circuit Z ₁ is provided a drive circuit of a plurality (two in this case), it is that their output is switched by the switch. Drive circuits B ₁₁ and B
₁₂ , a timing signal φ _i ′ and a complementary signal / φ _i ′ synchronized with the operation of Z ₁ are input.
One of the output V _L11, V _L12 of B _11, B ₁₂ is selected by the switch SW, is supplied to the load Z _1. When φ ₁ ′ is at a high level and φ ₁ ′ is at a low level, B ₁₁ is activated and B _11
12 is deactivated, and the switch SW is connected to the _VL11 side. Conversely, when φ ₁ ′ is at a low level and / φ ₁ ′ is at a high level, B ₁₁ is deactivated, B ₁₂ is activated, and the switch SW
Is connected to the V _L12 side. That is, two drive circuits B
_11, only one of B ₁₂ is used to supply the internal power supply voltage V _L1 to the load circuit Z _1, the other is in a state of being detached.

The embodiment of FIG. 24 employs a method of changing the circuit constant of the drive circuit in order to cope with a change in load. However, the impedance of the load greatly varies depending on the operation mode, and it may be difficult to operate the semiconductor device stably in a plurality of operation modes by simply changing the circuit constant. In such a case, the method of this embodiment is effective. This is because each drive circuit may be designed exclusively for one operation mode. For example, the in the case in a standby state when Z ₁ is in operation, there is a change in a very large current consumption. In this case, the driving circuit B ₁₁ when the Z ₁ is in operation, B ₁₂ is to operate stably respectively when Z ₁ is in the standby state, Oke design the feedback amplifier and phase compensation circuit I just need.

In this embodiment, the drive circuit which is not used is inactivated, but this is not always necessary.
This is because the drive circuit that is not used is separated by the switch. However, in order to reduce power consumption, it is desirable to keep it inactive. Although the output of the drive circuit is switched by a switch, the switch is unnecessary if the output is designed to have a high impedance when the drive circuit is in an inactive state.

In the embodiment of FIG. 24, since the drive circuit is divided, there is a concern that a potential difference may occur between the internal power supply voltages V _{L1 to} V _L3 . And the potential difference between the internal power supply voltage is large, or occurred mismatch when there is exchange of the load circuit Z ₁ to Z ₃ signals therebetween, sometimes elements to destroy. FIG. 27 shows one method for preventing this. For simplicity, the case where the load and the drive circuit are divided into two is shown. In this embodiment, two internal power supply voltages are connected to each other by two N-channel MOS transistors Q ₁ and Q ₂ . Assuming that the threshold voltage of the MOS transistor is V _TH , Q ₁ is Q ₂ when V _L1 −V _L2 > V _TH.
Are conductive when V _L2 −V _L1 > V _TH . Therefore, the potential difference between V _L1 and V _L2 is kept within V _TH .

The method of connecting the internal power supply voltages is shown in FIG.
7 is not limited. FIGS. 28A to 28E show some examples. The simplest method is a method of connecting with a resistor or an element which can be regarded as equivalently a resistor as shown in FIGS. FIG.
As in FIG. 27, this is a method for preventing the potential difference between the internal power supply voltages from exceeding a certain value. Here, diodes D ₁ and D ₂ are used instead of MOS transistors. V
The potential difference between the _L1 and V _L2 are suppressed within the ON voltage of the diode. FIG. 11E shows a method of connecting V _L1 and V _L2 by using a signal WK which becomes high only immediately after the power is turned on. This is particularly the case where the time constant of the rise of the load V _L1 and V _L2 are significantly different, it is effective to prevent a potential difference from occurring. 27 and 28.
A connection method in which some of (a) to (e) are combined may be adopted.

Note that the connection method described here is also effective for a voltage limiter that is not subjected to phase compensation.

In FIGS. 24 to 27, the load circuit is represented by a single impedance Z _i for simplicity. However, the load in an actual semiconductor device is often distributed in a semiconductor chip as shown in FIG. In such a case, it may be subjected to feedback from the portion of the middle or far end of the load distribution to the amplifier A _i. In the illustrated example, although the A ₁ is multiplied by the feedback from the proximal end of the load Z ₁₁ to Z ₁₉ distributed,
From the center of the load Z ₂₁ to Z ₂₉ are the A _2, loads the A ₃ Z ₃₁
Respectively multiplying the feedback from the far end of the to Z _39. The advantage of this configuration is that a drop in the internal power supply voltage due to the impedance of the wiring can be compensated, and the operation of a load far from the drive circuit can be stabilized. When feedback is applied in the middle of the distributed load or from the far end, it is desirable that the input of the phase compensation circuit is also taken from the same point.

[Feedback Amplifier and Phase Compensation Circuit] Next, a feedback amplifier and a phase compensation circuit suitable for use in the present invention will be described.

[0123] FIG. 30 (a) shows an embodiment of a feedback amplifier Ai and the phase compensation circuit C _i. In the figure, reference numeral 21 denotes a differential amplifier, which comprises MOS transistors Q _{21 to} Q ₂₅ . Reference numeral 22 denotes an output stage, which includes MOS transistors Q ₂₆ and Q ₂₇ . Of the two input terminals of the differential amplifier 21, the reference voltage V _R is input to one, V _L is fed back from the output stage to the other. C _i is the phase compensation circuit, the resistor R _D and a capacitor C _D is connected in series. FIG. 30 (b) shows a small signal equivalent circuit of this circuit when no feedback is applied.
For simplicity, the case where the load is a single capacitance _CL is shown. Here, g _m1, g _{m @ 2} each differential amplifier, the transfer conductance of the output stage, r _1, r _2, respectively differential amplifier, the output resistance of the output stage, C _G is the input capacitance of the output stage (Q ₂₆
Gate capacitance).

The frequency characteristics of this circuit are shown in FIG.
This will be described with reference to FIG. First, the case where no phase compensation is performed will be described. FIG. 31A shows the relationship between frequency and gain when there is no phase compensation circuit. In the figure, the gain v of a differential amplifier 21 _i '/ v _i, b is the output stage 22 gain v _o /
v _i ′, c is the total gain v _o / v _i . a and b begin to decrease at a rate of 6 dB / oct at frequencies f ₁ and f ₂ , respectively. Here, f ₁ = 1 / (2πC _G r ₁ ) and f ₂ = 1 / (2πC _L r ₂ ). In this example, since f ₁ > f ₂ , the total gain c
= V _o / V _i is 6 dB / oct when the frequency exceeds f ₂
In further decreases at a rate of 12dB / oct exceeds f _1. These points f ₂ and f ₁ are the so-called pole frequencies. As described above, in order for the feedback amplifier to operate stably, the point at which the feedback amplifier starts to decrease at 12 dB / oct (here, f
The gain in ₁ ) must be 0 dB or less. As is clear from the figure, if f ₁ and f ₂ are relatively close, this condition is often not satisfied. FIG. 31 (a)
Is not satisfied. Therefore, by separating sufficiently and f ₁ and f _2, it is possible to stabilize the feedback amplifier.

[0125] Here, when adding a phase compensation circuit C _i, the frequency characteristic becomes as shown in FIG. 31 (b). That is, the gain of the differential amplifier 21 does not change, but the gain of the output stage has a characteristic bent at three points P ₂₁ , Z ₂ , and P ₂₂ .
P ₂₁ and P ₂₂ Paul, Z ₂ is a point called the zero point.
The frequencies at these points are as follows:

[0126] _{f 21 = 1 / (2π (} C D r 2 + C L r 2 C D R D)) f 22 = (C D r 2 + C L r 2 C D R D) / (2πC L C D r 2 R _D ) f ₂ = 1 / (2π C _D R _D ) As is clear from this figure, by setting f ₂ near the pole frequency f ₁ of the differential amplifier, ie, C _D
By setting R _D ≒ C _G r ₁ , the bending at f ₁ of the total gain is eliminated. As a result, the overall gain is
If the frequency exceeds f ₂₁ in 6 dB / oct, further f ₂₂
Is exceeded, the rate will decrease at a rate of 12 dB / oct. Here, by securing larger n as _{C D = nC G r 1 /} r 2, R D = r 2 / n, it is possible to separate sufficiently and f ₂₁ and f _22, to stabilize the feedback amplifier Can be.

FIG. 32A shows another embodiment of the feedback amplifier and the phase compensation circuit. In this circuit, by inserting a capacitor C _F between the input and the output of the output stage 22, which performs phase compensation. FIG. 32B shows a small signal equivalent circuit of this circuit when no feedback is applied, and FIG. 33 shows its frequency characteristics. In this case, the gain in the direction of the differential amplifier, a bent characteristic at three locations of the _{P 11, Z 1, P 12} . In this case, as in the previous embodiment, the feedback amplifier can be stabilized by setting f ₁ ≒ f ₂ and separating f ₁₁ and f ₁₂ sufficiently. The feature of this embodiment is that the apparent capacitance is increased by the so-called Miller effect because the phase compensation capacitor _CF is inserted between the input and the output of the amplification stage. Therefore, even if the actual capacitance is relatively small, phase compensation can be performed, so that the area occupied by the capacitor can be reduced.

Here, FIG. 30 (a) or FIG. 32 (a)
The capacitor used in the phase compensation circuit described above will be described.
These capacitors need to have a considerably large capacitance (usually several hundred to several thousand pF) and a small voltage dependency. FIG. 34A shows one method for realizing this in a normal CMOS process. In the figure, 101 is a P-type semiconductor substrate, 102 is an N-type well, 103 is an N ⁺ diffusion layer, 104 is SiO ₂ for isolation, 105 is a gate insulating film, and 106 is a gate. The capacitor is
As with the ordinary MOS capacitor, the gate insulating film 1
It is formed between the gate 106 and the substrate surface 102a with the layer 05 interposed. Since a thin gate insulating film is used as the capacitor insulating film, it is characterized in that a large capacitance can be obtained in a relatively small area. However, the difference from a normal MOS capacitor is that the threshold voltage is negative because of the N well under the gate. This is shown in FIG.
This will be described with reference to FIG. The horizontal axis is the voltage applied to the capacitor (positive on the gate side), and the vertical axis is the capacitance. The threshold voltage (flat band voltage) is the applied voltage V ₀ when the capacitance changes greatly, and V ₀ <0. Therefore, as long as a voltage in one direction is applied so that the gate side becomes positive, there is a characteristic that the power collection capacity is almost constant. If bidirectional voltage can be applied,
By using two capacitors shown in FIG.
What is necessary is just to connect in parallel in the opposite direction as shown in (c).

The steps required to fabricate the capacitor of this embodiment are the steps of forming a well, forming an isolation region, forming a gate insulating film, forming a gate, forming a diffusion layer, and wiring. This is a step included in a normal CMOS process. Therefore, as long as the semiconductor device is manufactured by a CMOS process, it is not necessary to add a particular step to manufacture the present capacitor.

Further, depending on the semiconductor device to which the present invention is applied, a stacked capacitance may be used. For example, a DRAM using a stacked capacitance as a capacitor of a memory cell
Is so. In such a case, the laminated capacitance may be used as a phase compensation capacitor. D using stacked capacitance
About RAM, IEE, Journal of Solid State Circuits, 15th
Vol. 4, No. 4, pp. 661 to 666, August 1980
Month (IEEE Journal of Solid-State Circuits,
Vol. SC-22, No. 3, pp. 661-666, Aug.
1980).

[Reference Voltage Generating Circuit] Next, a reference voltage generating circuit suitable for use in the voltage limiter circuit according to the present invention will be described. The reference voltage generation circuit described here can be used for a voltage limiter circuit that does not perform phase compensation. Needless to say, the embodiment described in Group 1 can be applied.

The output voltage V _L of the electric limiter is generated based on the reference voltage V _R. Therefore, the characteristics of V _R,
The characteristics of _VL can be set arbitrarily. When using a voltage limiter circuit in the semiconductor device, since the external power supply voltage V _CC dependence of V _L is particularly important, it is necessary to design special attention to the V _CC dependency of V _R. Regarding this, examples of characteristics for various purposes and methods of generating the characteristics are described in Japanese Patent Application No.
57143, Japanese Patent Application 56-168698, Japanese Patent Application 57-57
220083, Japanese Patent Application No. 60-261213, Japanese Patent Application No. 63
-8372, Japanese Patent Application No. 63-125742, U.S. Pat.
No. 100377 and the like. It goes without saying that these circuits can be applied to the present invention.

In the embodiments of FIGS. 24 to 27, the reference voltage V
_R was directly input to the drive circuit. However, the voltage obtained by the reference voltage generation circuit is not always an appropriate value as the internal power supply voltage used in the semiconductor device. In this case, voltage conversion is required. In some cases, fine adjustment of the voltage, that is, so-called trimming, may be necessary to compensate for variations in the reference voltage due to the manufacturing process. As a method of voltage conversion and trimming, the method described in the aforementioned US Pat. No. 4,100,437 may be used. Here, a method suitable for a semiconductor device manufactured by a normal MOS process will be introduced.

FIG. 35 is a circuit diagram. In the figure, DA is a differential amplifier, Q _{31 to} Q ₄₃ are P-channel MOS transistors,
F ₁ ~F ₈ is a fuse. (Output of the reference voltage generating circuit) V _R is the input voltage is V _R 'is the output voltage (the input of the drive circuit). While the the DA input terminal, V _R is input, MOS transistors Q ₃₁ to V _R 'to the other ~Q
If the amplification factor of .DA that V _R "divided is fed back is sufficiently large by _42, the output voltage V _R 'is given by the following equation.

V _R ′ = ((R ₁ + R ₂ ) / R ₂ ) · V _R where R ₁ is a resistance value when a circuit composed of Q _{31 to} Q ₃₈ is equivalently regarded as a resistance, R ₂ Is the resistance value when the circuit consisting of Q _{39 to} Q ₄₂ is equivalently regarded as a resistor. R ₁ and R ₂ change by cutting the fuse.
It is possible to adjust the V _R '.

A specific trimming method will be described with reference to FIG. This figure shows the relationship between the input V _R and output V _R '. In the figure, d is the characteristic when the fuse is not blown at all. When the fuse F _1, F _2, F ₃ in order, since the R ₁ increases, c, b, as indicated by a V _R 'increases. When the fuses F ₄ , F ₅ , and F ₆ are blown in order, the above R ₂ increases, so that e, f, g
As shown by, V _R ′ decreases. Therefore, first observe the V _R, as V _R from FIG 13 'is most target value V _R0' close to, it may be selected method of cutting a fuse. Our goal is, also vary in the V _R is a wide range, V _R '
Is within a certain range V _R0 ′ ± ΔV _R ′. For this purpose, as shown by a broken line in FIG, V _R 'to the case of employing some trimming method (e.g., a)
= V _R0 ′ + ΔV _R ′, if a trimming method (for example, b) adjacent thereto is adopted, V _R ′ = V _R0 ′
So as to - [Delta] V _R ', it is sufficient to choose circuit constant (channel width / channel length of the MOS transistor).

FIG. 37 shows another embodiment of the trimming circuit. To lower the output voltage V _R ′, fuses F ₄ , F ₅ , and F ₆ may be cut in order, as in FIG. The difference from FIG. 35 lies in the method of increasing the output voltage V _R ′. In this case, first, the fuse F ₇ (this input-output characteristic at the time left to choose circuit constant so as h in FIG. 36), then F _4, F _5, cut F ₆ sequentially Just do it. This circuit has an advantage that the number of fuses is smaller than that of the circuit of FIG. 35, so that the occupied area can be reduced.

The circuits shown in FIGS. 35 and 37 are different from the circuits described in the above-mentioned U.S. Pat.
There is an advantage that the area occupied by the process is small. That is, in the circuit described in the US patent,
While a resistor is used as an element for dividing output voltage V _R ′, the circuit shown in FIGS.
An S transistor is used. In order to reduce the current consumption of the circuit, the equivalent resistance of the voltage dividing element must be considerably large (about several hundred kπ). In a normal MOS process, an element having a small area and a large equivalent resistance can be obtained with a MOS transistor than with a resistor. However, MO
When the S transistor is used, there is a concern that the characteristics of V _R ′ may fluctuate due to the fluctuation of the threshold voltage. However, the channel width and channel length of each transistor are made sufficiently large to suppress the fluctuation, and the back gate is connected to the source. Can be solved by avoiding the influence of the substrate potential fluctuation and selecting the fuse cutting method in consideration of the variation in the threshold voltage.

Next, the MOS transistor used in the trimming circuit will be described with reference to FIGS. As described above, the back gate of each transistor is desirably connected to each source in order to suppress the influence of substrate potential fluctuation. For example, when the substrate is a P-type, a P-channel MOS as shown in FIG.
A transistor may be used. When the substrate is N-type, an N-channel MOS transistor whose conductivity type is all reversed in FIG. 38A may be used. FIG. 38
As shown in (b), by forming the double well structure and fixing the potential of the outer well 112 (grounding in this case), it is possible to further strengthen the substrate potential fluctuation.

Next, a fuse used in the trimming circuit will be described. As the fuse, for example, the same fuse used for relieving defects in a semiconductor memory, such as polycrystalline silicon, can be used. Therefore, in the case of a semiconductor memory having a defect relieving circuit, it is not necessary to add a particular step for forming a fuse. The method of cutting the fuse may be a method using laser light or an electric method. The method using laser light has an advantage that an occupied area can be reduced because a cutting transistor is not necessary, and the advantage that an expensive laser light irradiation device does not need to be used for an electrical method. is there.

[0141] shows another embodiment of the conversion circuit to the V _R 'from V _R in FIG. 39 (a). Differs from the circuit of FIG. 35 or FIG. 37 is that obtained by adding a P-channel MOS transistor Q _48. As a result, the maximum value of the output voltage V _R ′ is suppressed to V _CC − | V _TP | (V _TP is the threshold voltage of the P-channel MOS transistor). This will be described with reference to FIG. This figure shows the dependence of V _R and V _R ′ on V _CC . In the circuit of FIG. 35 or 37, when V _CC is low, V _R ≒ V _CC . However, the circuit of FIG. 39 (a) is the addition of Q _48, when V _CC is lower V _R '= V
_CC− | V _TP | and | V _TP |.

The advantage of this embodiment is that when V _CC is much lower than normal operating conditions (eg, 5V) (eg, 3 V).
V), the voltage stability of the internal power supply voltage _VL is good. This will be described with reference to FIG. This figure is
In the driving circuit of FIG. 30 (a) or FIG. 32 (a), which is an example of the relationship between the power voltage V _L and the current I _L when V _CC is low. 35 or 37 to generate V _R '.
When using the circuit of, V _L ≒ V _R When V _CC is low '≒
Since V _CC , the drain-source voltage of the output MOS transistor (Q _{26 in} FIG. 30A or FIG. 32A) of the driving circuit is almost 0, and the current driving capability is small. Therefore, when the output current (current consumption of the load) I _L increases, V _L decreases. On the other hand, when the circuit of FIG. 39A is used to generate V _R ′, V _L ≒ V _R ′ ≒ V _CC − | V _TP | The drain-source voltage is approximately equal to | V _TP | (in this example, 0.5 V). Therefore, its current driving capability is relatively large, and the amount of decrease in V _L is small. That is, by setting _VL a little lower in advance, the operation of the circuit in the semiconductor device that operates the amount of voltage fluctuation when V _CC is low becomes more stable,
_The operating margin for _CC increases.

[0143] Note that the circuit Q ₄₈ in FIG. 39 (a) is also similar to the MOS transistor of the above-mentioned trimming circuit, in order to suppress the influence of the change of substrate voltage, FIG. 38 (a), in the structure shown in (b) It is desirable to keep.

[In-Chip Arrangement and Wiring] Next, a circuit arrangement method for mounting the present invention in an actual semiconductor chip will be described.
And described interconnection method of the reference voltage V _R and the internal power supply voltage VL. Although a DRAM is taken as an example of a semiconductor device to which the present invention is applied, the present invention can be applied to other semiconductor devices. Further, the arrangement / wiring method described here is also effective for a voltage limiter circuit that is not subjected to phase compensation.

FIG. 40 shows an example of a desirable circuit arrangement and wiring when the voltage limiter circuit is applied to a DRAM. In the figure, 1 is a semiconductor chip, 2a and 2b are fine MOSs
Memory array composed of transistors, 3a, 3
b and 3c are peripheral circuits. 4 and 5 are ground V
_GND is a bonding pad for the external power supply voltage V _CC , 6 is a reference voltage generating circuit, and 7a, 7b, 7c, 7d are driving circuits. 6 and 7a to 7d constitute a voltage limiter circuit. 7a, 7b and 7c are peripheral circuits 3 respectively.
a, 3b, 3c internal power supply voltages V _L1 , V _L2 , V
Generates _L3 . 7d generates an internal power supply voltage V _L4 for driving the memory arrays 2a and 2b.

The present embodiment is characterized in that the reference voltage generating circuit 6 and the driving circuits 7a to 7d are separated, the reference voltage generating circuit is located near the bonding pad for inputting the ground potential, and the driving circuit is located near the respective load circuits. It is arranged in. Therefore, the ground wiring 8 from the ground potential input bonding pad to the reference voltage generating circuit and the internal power supply voltage wirings 11a to 11d from each drive circuit to each load circuit are shortened, and their impedance is reduced. Thus, the noise on the wire 8 is reduced, the ground level of the reference voltage generating circuit is stabilized, stable reference voltage V _R is obtained. Further, since the voltage drop of the internal power supply voltages V _{L1 to} V _L4 due to the impedance of the wirings 11a to 11d is reduced,
Level _L1 ~V _L4 is stabilized, the operation of the load circuit is stabilized.

Another feature of this embodiment lies in the method of ground wiring. First, a dedicated short wiring 8 is provided for the reference voltage generating circuit. For other circuits, wiring 9a
To 9d. That is, each drive circuit and its load circuit are wired with a common line, but are separated from other drive circuits and load circuits. The advantage of this wiring method is that noise generated on the ground wiring due to current flowing when each circuit operates can be prevented from adversely affecting other circuits. In particular, the reference voltage noise to the ground wiring of the generator occurs, all the level of the internal power supply voltage V _L1 ~V _L4 varies, only a ground wire for the reference voltage generating circuit is necessarily other ground wiring is separated It is desirable to keep. It is also desirable that the ground wiring for the memory array be separated from other ground wirings. This is because, in a DRAM, when a sense amplifier performs an amplifying operation, a large number of data lines (the capacitance of which is usually several thousand pF) are simultaneously charged and discharged, and a large noise is generated in a ground wiring.

FIG. 41 shows another embodiment of the circuit arrangement and wiring. In this embodiment, the peripheral circuit 3 are arranged concentrated in the center of the chip, which is further disposed at the center of the bonding pads 4, 5 chip for ground and the external power supply voltage V _CC. Also in this embodiment, the reference voltage generating circuit 6 is provided with the driving circuits 7a and 7
d is arranged near each load circuit.

The advantage of this embodiment is that the wiring length is short, as is apparent from FIG. As a result, the power supply becomes more resistant to fluctuations in the external power supply voltage V _CC and fluctuations in the current flowing through the load circuit. That is, in the previous embodiment, since the wiring 10 between the V _CC bonding pad and each drive circuit is long, its impedance is large, and the level of V _CC is reduced by the current consumption of the load circuit. Of course, this reduction is absorbed by each drive circuit, but if the reduction is too large, it cannot be absorbed, and the internal power supply voltage V
_L level may decrease. On the other hand, in the present embodiment, since the impedance of the V _CC wiring 10 is small, a larger load current can flow. Also V
Strong against _CC drop.

In FIG. 40 or FIG. 41, the reason why the noise of the ground wiring is particularly problematic is that the reference voltage V _R and the internal power supply voltage V _Li are generated with reference to the ground potential. Conversely, when V _R and V _Li are generated with reference to the external power supply voltage V _CC , the noise of the V _CC wiring is more problematic. In this case, the reference voltage generating circuit may be arranged near the V _CC bonding pad, and the V _CC wiring may be separated for each circuit.

[0151] Incidentally, in the arrangement and wiring method shown in FIG. 40 or FIG. 41, the reference voltage V _R from the reference voltage generating circuit is wired to each drive circuit, keep Faraday shield to the wiring 12 Is desirable. This is to prevent V _R from fluctuating due to noise from other circuits in the semiconductor chip. An example of a shielding method that can be realized by a normal semiconductor manufacturing process will be described below.

FIGS. 42 (a) and 42 (b) are a plan view and a cross-sectional view, respectively, of one embodiment of the shielded wiring. In the figure, 101 is a semiconductor substrate, 104 is SiO ₂ , 1
08 is a first wiring layer, 109a, 109b and 109c are second wiring layers, 113 and 114 are interlayer insulating films, and 115 is a protective film. 109b is the reference voltage V _R wiring.
The surrounding wires 108, 109, and 109c are shielding wires, which are fixed to a constant potential (here, ground). Substrate 1 is provided by providing 108 below 109b.
01 can be prevented and noise 109
The provision of a and 109c can prevent noise due to capacitive coupling with an adjacent wiring (not shown). FIG.
(C) and (d) show another embodiment of the shielded wiring. In this embodiment, the V _R first wiring layer 108
The wiring is provided by b, and shielding wirings are provided on the left and right (108a, 108c), below (106) and above (109), respectively. By providing the shield wiring also above, noise due to capacitive coupling through the space above can also be prevented, and the shield becomes more effective.

Further, as shown in FIGS. 61 (a) and 61 (b), contact holes 116a and 116c and through hole 1
If the shield wires are connected by providing the wires 17a and 117c, the shield becomes complete. FIGS. 61C and 61D show another embodiment of the shielded wiring. In this embodiment, the polycrystalline silicon layer 106 is a wiring V _R. A well 112 is formed below the P-type diffusion layer 107.
a, 107c and contact holes 116a, 116c
Is connected to the upper first wiring layer 108 via the. That is, 112, 107a, 11
6a, 108, 116c, and 107c provide shielding. An advantage of the present embodiment is that the second wiring layer is not used for the shield, and this is shown in FIG.
09, it can be used for other purposes.
This is, for example, the wiring and the other wiring V _R is effective for use in the intersection.

It is to be noted that the above-described shield makes it possible to obtain V _R
There is a parasitic capacitance between the capacitor and ground, which has a rather favorable effect. This parasitic capacitance reduces the impedance to the high frequency of V _R wiring, thereby bypassing the high frequency noise, because acts as a so-called decoupling capacitor. In the case where the capacitance is insufficient as a decoupling capacitor using only the shielded wire, it is of course possible to load the capacitor separately with the capacitor.

In the above example, the potential for fixing the shield line is the ground potential. However, the potential is not necessarily the ground potential as long as the potential is stable. However, a ground potential is the simplest, and is desirable because the parasitic capacitance acts as a decoupling capacitor as described above. Especially,
The connection to the ground wiring for the reference voltage generation circuit (the portion 8 shown in FIGS. 40 and 41) may be sufficient to avoid noise generated by the operation of other circuits. As described above, V _{R is} V
If generated on the basis of the _CC, the shield line is better to fix the V _CC.

FIG. 43 shows another embodiment of the circuit arrangement and wiring. In the figure, 1 is a semiconductor memory chip, 3 is a peripheral circuit, 7a, 7b, 7c are drive circuits each generating an internal power supply voltage _VL , and 14a, 14b, 14c, 14d are voltages using the output of the drive circuit as a power supply. A pulse generating circuit for generating pulses φ _P1 , φ _P2 , φ _P3 , φ _P4 of amplitude _VL ;
a, 2b, 2c, 2d are φ _P1 , φ _P2 , φ _P3 , φ
_This is a memory array using micro MOS transistors operated by _P4 . The description of the reference voltage generation circuit is omitted here. FIG. 44 shows the operation timing of these circuits.

A single external power supply voltage V _CC (for example, 5 V) is applied to the semiconductor memory chip 1 of this embodiment. Drive circuits 7a, 7b, 7c output internal power supply voltage VL (for example, 3 V) lowered from V _CC and are input to pulse generation circuits 14a, 14b, 14c, 14d, respectively. The pulse generation circuit receives a timing pulse φ _T shown in FIG. 44 and a signal / _ai having a phase opposite to that of the address signal a _i .

[0158] peripheral circuit 3, an external address signal A and the internal address signals a _i and / a _i receives _i, external control signals (where the row address strobe signal / RAS, a column address strobe / CAS, and write enable signal / WE) to generate an internal timing pulse φ _T. Peripheral circuits, it is not necessary to use a dare fine element since the chip integration little effect, and the convenience of the Eastern Marsh Harrier interface, external power supply voltage V _CC
, But may of course be operated with the internal power supply voltage.

In the memory, only the array selected by the address operates. In this example, a _i = “0” (/ a _i =
When “1”), the arrays 2a and 2c are selected (2b and 2d are not selected), and when a _i = “1” (/ a _i = “0”), the arrays 2b and 2d are selected (2a and 2c are not selected). (Selection). Therefore, only the pulse for the selected array is output. That is, as shown in FIG. 44, a _i =
"0" when the pulse generation circuit 14a and 14c is a timing pulse phi _T phi _P1, and outputs the phi _P3 array 2
a and 2c, when the a _i = "1" Conversely, the pulse generating circuit 14b and 14d is the timing pulse phi _T phi _P2,
By outputting _φP4 , the arrays 2b and 2d are operated.

The feature of this embodiment is that each drive circuit is arranged close to each pulse generation circuit, and the pulse generation circuit 14
b and 14c share the drive circuit 7b. Therefore, compared to FIG. 3, the wiring is shorter, the impedance of the wiring is smaller, and the level of generated noise can be suppressed. Also, compared to FIG.
The number of drive circuits is reduced by one, thereby realizing a reduction in chip occupation area and power consumption. Moreover, since the pulse generating circuits 14b and 14c do not operate at the same time, the driving circuit 7b only needs to be able to drive one pulse generating circuit.
There is no need to double the current drive capability.

The pulse generation circuits 14a to 14d can be realized by the circuits shown in FIGS. 45 (a) and (b), for example. In FIG. 45A, reference numeral 51 denotes a two-input NAND circuit including P-channel MOS transistors Q ₅₁ and Q ₅₂ and N-channel MOS transistors Q ₅₃ and Q ₅₄ . The power supply for this circuit is V _CC and the inputs are the timing pulse and the address signal a _i (or / a _i ). 52 is an inverter composed of a P-channel MOS transistor Q ₅₅ and an N-channel MOS transistor Q _56, the power source is a V _L. When φ _T is input when a _i is “1” (potential V _CC ), a pulse φ _P having an amplitude of the internal power supply _VL is input. Here, the NAND circuit is operated at the external power supply voltage V _CC , but may be operated at the internal power supply voltage V _L.

FIG. 46 shows an example in which the number of drive circuits is further reduced by one as compared with the embodiment of FIG. Address signals a _i , / a _i , timing pulse φ _T , and pulse φ _P1
To [phi] _{P 4} are the same as those described in FIG. 43.

In this embodiment, the pulse generation circuits 14a and 1
The drive circuit 7a is shared by 4b, and the drive circuit 7b is shared by 14c and 14d. Therefore, as compared with the embodiment of FIG. 43, the number of drive circuits is reduced by one, thereby reducing the chip area and power consumption. Here, as shown in FIG.
a and 14b and 14c and 14d do not operate simultaneously. Therefore, the driving circuits 7a and 7b need only be able to drive only one pulse generating circuit, and it is not necessary to double the driving capability.

FIG. 47 shows an embodiment to which the present invention is applied when the memory array is divided into eight. In the figure, 1
Is a semiconductor chip, 3 is a peripheral circuit, 2a to 2h are memory arrays, 7a and 7b are drive circuits, and 14a to 14h are pulse generation circuits. In this embodiment, two out of eight arrays
Are selected by the address signals a _i and a _j , and only the selected array operates. In other _{words, a i a j = "00} "
2a and 2e, a _i a _j = 2b and 2f when the "01", 2c and 2g is when a _i a _j = "10" when the, a _i a _j =
In the case of "11", 2d and 2h are respectively selected. Therefore, the pulse φ _Pk (k = 1 to
Only 8) is output. That is, as shown in FIG. 48, the address signal a _i a _j = "00" pulses phi _P1 when the
φ _P5, a _i a _j = pulse φ _P2 and φ _P6, a when the "01"
_{When i aj} = “10”, pulses φ _P3 and φ _P7 , a _i a _j =
When it is “11”, pulses φ _P4 and φ _P are output, respectively. These pulses φ _Pk (k = 1 to 8) are pulses output at the timing of φ _T and have an amplitude of the internal power supply voltage _VL .

In this embodiment, two driving circuits 7a and 7 are composed of eight pulse generating circuits for operating the memory array.
b. By doing so, the number of driving circuits can be significantly reduced, and the occupied area and power consumption can be reduced.

[Example of Application to DRAM] Finally, an example in which the present invention is applied to a DRAM will be described. FIG. 49 is a configuration diagram of a DRAM to which the present invention is applied. In the figure, reference numeral 201 denotes a bonding pad for supplying a power supply voltage (V _CC ), which is connected to an external power supply. 202 is a differential amplifier, 203 is a supply line for an internally stepped-down power supply voltage (V _L ), 204 is a driving MOS transistor of a P-channel MOS sense amplifier,
05 is a starting MOS transistor of the N-channel MOS sense amplifier, 206 is a P-channel MOS sense amplifier, 2
07 is an N-channel MOS sense amplifier, 208 is a memory cell, 209 is an N-type well of a P-channel MOS sense amplifier, 210 is a memory block including a cell array and a sense amplifier, 211 is an X decoder, 212 is a Y decoder, 213 Is a short precharge signal line, 214
Is a power supply line V _L / 2. The power supply voltage V _CC is used in peripheral circuits such as an X decoder, a Y decoder, gate protection and a signal generation circuit. In the case of the present embodiment, the internally stepped down power supply voltage _VL is the sense amplifier driving MOS transistor 2
It is used for the back gate (well) of the P-channel MOS transistor connected to the part 04 and part of the Y decoder.

In the case of a so-called CMOS circuit such as a sense amplifier, if a P-type substrate is used, a P-channel MOS transistor is usually formed in an N-type well. In this case, as shown in the cross-sectional view of FIG. 50, the potential of the N-well (the back gate of the P-channel MOS transistor) is not the external power supply voltage V _CC but the operating voltage supplied to its source (V _{L in} this case). It is desirable that The reason will be described below.

For example, if V _CC = 5 V and V _L1 = 3 V, since the data line precharge level is 1.5 V, a back gate bias of 1.5 V is applied to the P-channel MOS transistor before the start of the sense amplifier. After starting, it becomes 0V. Referring to FIG. 6, the threshold voltage (absolute value) before the start of the sense amplifier is about 0.86 V and about 0.57 V after the start. If the N-well voltage V _CC (= 5
V), they are 1.1V and 0.92V, respectively. This is too large as compared with V _L1 . FIG.
FIG. 7 is a diagram in which the operating speed of the sense system of the DRAM is plotted against the threshold voltage of a P-channel MOS transistor. As can be seen from the figure, a rise in threshold voltage of 0.1 V corresponds to a delay of about 2 ns. In this case, setting the N-well voltage to V _L1 (= 3 V) achieves a speedup of about 5 ns or more. We can see that we can do it. Since the CMOS LSI in the era of ultra-high integration tends to lower the operating voltage and increase the substrate (well) concentration (increase the back gate bias effect), the effect of the present invention becomes even more important.

Here, the N-well voltage is changed to a P-channel MOS.
In making the internal power supply voltage _VL equal to the internal power supply voltage supplied to the transistor, there is a concern that the N-well voltage may fluctuate due to capacitive coupling or the like. In the embodiment shown in FIG. 49, the data line is V _L
Since the transistor is precharged to / 2, when the P-channel MOS transistor operates, it is paired with the transistor which decreases as the drain voltage increases, and the noise is extremely small.
Therefore, problems such as latch-up due to fluctuations in the N-well voltage do not occur.

Although the above description has been made taking the sense amplifier as an example, the same method can be applied to other CMOS circuits. In addition, the present invention is not limited to a DRAM, and is applicable to any CMOS / LSI having two or more different operating voltages.
Further, in the embodiments of the present invention, it is apparent that the present invention is established even if all the conductivity types and potential relationships of the semiconductor are reversed.

As described above, according to the present invention, it is necessary for the voltage limiter circuit to drive many types of loads, and even when the type and size of the load vary depending on the operation mode, And an optimal phase compensation according to the operation mode and the operation of the voltage limiter can be stabilized.

Further, when there are a plurality of load circuits in the semiconductor chip using the internal voltage as a power supply, the wiring from each drive circuit to each load circuit can be shortened, so that the noise level can be reduced. Further, the number of circuits can be reduced without increasing the driving capability of the driving circuit, so that the occupied area and power consumption can be reduced.

In addition, C using the internally stepped down operation voltage
In a MOS circuit, by making the voltage of the back gate (well) of the transistor formed in the well equal to the stepped-down voltage, the circuit can be operated at high speed. High speed can also be realized.

[Third Group] The problem with the above technique is that the method of externally checking the internal voltage is not considered. For example, a memory L having a voltage limiter
In the case of SI, if the internal voltage value generated by the voltage limiter deviates from the design value, the operation margin of the internal circuit becomes narrow or malfunctions. However, when testing the memory LSI with a memory tester or the like, the above-described problems cannot be easily confirmed unless the internal voltage value is known.

If a pad is provided at the internal voltage terminal and a memory tester is connected to the pad, the internal voltage value can be known from the outside. However, this method has the following problems.

First, an error occurs in the measured value due to noise received on the wiring from the pad to the memory tester.

Second, the voltage value may change depending on the input impedance of the memory tester.

Third, since a memory tester measures an analog voltage, it takes longer to measure than a digital signal.

An object of the present embodiment is to solve the above problems and to provide a semiconductor device in which the internal voltage can be easily inspected from the outside by a memory tester or the like.

In order to achieve the above object, in this embodiment,
Means are provided for comparing the externally designated voltage with the internal voltage, and means for outputting the result of the comparison.

By comparing the externally designated voltage with the internal voltage and outputting the result of the comparison, the signal taken out to the outside becomes a digital signal. Therefore, compared to the case where the voltage is directly taken out from the above-mentioned internal voltage terminal, it is less susceptible to the influence of noise and the input impedance of the measuring instrument, and the inspection with a memory tester becomes easy.

Hereinafter, this embodiment will be described with reference to the drawings. In the following description, an example in which the present invention is applied to a DRAM will be described. However, the present invention is not limited to a DRAM and can be applied to other semiconductor devices.

FIG. 52 shows this embodiment. This is a DARM with a voltage limiter. In the figure, 1 is a semiconductor chip, 2 is a DRAM memory array, 3 is a peripheral circuit of DARM, 4 is a voltage limiter, 5 is a comparison circuit, 6 is a multiplexer and an output buffer, and 8 is a test enable signal generation circuit. The voltage limiter 4 generates an internal power supply _VL lower than V _CC based on the external power supply V _CC . DRA
The peripheral circuit 3 of M operates by the external power supply V _CC , while the memory array 2 operates by the voltage of the internal power supply _VL .

A method for inspecting the voltage of the internal power supply _VL in this embodiment will be described.

[0185] Comparison circuit 5 compares the comparison voltage V _S and V _L. In this embodiment, the terminal for inputting the V _S is, DRA
Although it is shared with the data terminal D _{in of} M, it may be a dedicated terminal or may be shared with another terminal, for example, one of the address terminals. The output C of the comparison circuit is output via the multiplexer and the output buffer 6. In this embodiment, C
Is also used as the data output terminal D _out of the DRAM, but may be a dedicated terminal.

The comparison output C goes high when V _L > V _S and goes low when V _L <V _S. Therefore, D
By observing the D _out by changing the comparison voltage V _S applied to the _in, it is possible to know the internal voltage V _L.

[0187] For example, the external power supply V _CC is, in the range of _{V CCmin ≦ V CC ≦ V CCmax} ... (1), and V _L must be less than the higher V _Lmax than V _Lmin. To test this, first, D
_Apply V _Lmin to _in and change V _CC from V _CCmin to V _CCmax to confirm that D _out is always high.
Next, V _CCmax is applied to D _in to _change V _CC from V _CCmin to V _CC
Until _CCmax varied, it may be confirmed that D _out is always low level.

The feature of the present invention is that the signal output from the D _out terminal is a digital signal of a high level or a low level. Therefore, compared to the case of directly outputting the analog voltage, it is possible to avoid noise and errors due to the input impedance of the memory tester, and it is easy to perform the inspection with the memory tester.

The test enable signal TE is a signal indicating whether the mode is a mode for checking _VL or a normal read / write mode. This signal is used to enable the comparison circuit 5 and to switch the multiplexer and the output buffer 6. Although a dedicated terminal for inputting TE may be provided, in this embodiment, TE
Is provided. This circuit uses D
The TE is generated by a combination of the timing at which the row address strobe signal (/ RAS), the column address strobe signal (/ CAS), and the write enable signal (/ WE) of the RAM are applied.

This will be described with reference to FIGS. 53 (a) and 53 (b).

In the normal read / write mode of the DRAM, as shown in FIG. 53A, / RAS is / CA
It is applied before S. Conversely, as shown in FIG.
/ CAS is applied before the / RAS, moreover at that time / W _E was low, circuit 8 is determined to be a specified V _L inspection mode, generates a TE. In addition,
A method of designating a special operation mode by a combination of timings of / RAS, / CAS and / WE is described in, for example, ISSC, Digest of Technical Papers, pp. 18-19. page,
February 1987 (ISSCC Digest of Technical)
Papers, pp. 18-19, Feb. 1987) or
ISSC, Digest of
Technical Papers, pages 286-287,
February 1987 (ISSCC Digest of Technical)
Papers, pp. 286-287, Feb. 1987).

[0192] previously supplemented here by a dedicated signal for inspection in the V _L (V _S, C, and TE) for input and output method.

As described above, dedicated terminals for these signals may be provided. However, in the embodiment of FIG. 1, the input terminal of V _S is D _in and the output terminal of C is D _out.
, And TE is / RAS, / CAS, /
It is created by a combination of WE timings. The advantage of this method is that _VL can be inspected using only the original terminals of the DRAM. Therefore, not only inspection in a wafer state but also inspection after assembling in a package becomes possible.

FIG. 54 shows an example of the comparison circuit 5.

In FIG. 54, reference numeral 20 denotes a differential amplifier having V _L and V _S as inputs and a node 27 as an output.
It comprises channel MOS transistors 21, 22, 23 and P channel MOS transistors 24, 25. Reference numeral 30 denotes an inverter having a node 27 as an input and C as an output.
N-channel MOS transistor 31 and P-channel MOS
It comprises a transistor 32. Node 27 when V _L is higher than V _S is low, output C is high. V _L
Is below V _S, node 27 is high and output C
Becomes low level.

As a comparison circuit, a single differential amplifier may be used. However, when the output of the differential amplifier is further amplified by an inverter as in the present embodiment, the level of the output C is reliably increased to a high level (≒ V _CC ) and low level (≒ 0 V).

In this circuit, since TE is input to the gate of the MOS transistor 21, no current flows through the differential amplifier except in the _VL inspection mode (when TE is at a high level). This can prevent an increase in power consumption during normal operation. Also, during normal operation, P-channel MOS transistor 26 is conductive, so that node 27 is fixed at a high level.

Next, a method of realizing the multiplexer and the output buffer 6 used in the present invention will be described.

FIG. 55 shows an example of a multiplexer and an output buffer. 55, 41, 42, and 49 to
52 is an inverter, 43 to 48 are NAMD gates, 53
And 54 are N-channel MOS transistors. This circuit is a circuit that selects one of the data output d _out of the DRAM and the output C of the comparison circuit and outputs it to an output terminal D _out . Which one to select is determined by TE (the above-described test enable signal) and OE (the output enable signal of the DRAM). TE is high level, O
When E is at a low level (in the _VL inspection mode), C is
When TE is at a low level and OE is at a high level (in a read mode), d _out is selected and output. T
When both E and OE are at a low level (in a write mode or a standby state), the output terminal D _out has a high impedance.

FIG. 56 shows another embodiment of the present invention. The difference from the previous embodiment is that two comparison voltages V _S1 and V _S2 are input and two comparison circuits 5-1 and 5-2 are provided.

The comparison circuit 5-1 compares the internal voltages _VL and _VS1 , and 5-2 compares _VL and _VS2 . Comparison output C ₁ may, when the V _L> V _S1 is at high level, V _L> V _S2 goes low. Comparison output C ₂ may, when the V _L> V _S2 goes high when the low level, V _L <V _S2. The signal C output to the outside is the result of ANDing C ₁ and C ₂ with the AND gate 9.

In this embodiment, the data input terminal and the output terminal are shared, and four bits are read / written simultaneously. This is a so-called × 4 bit DRAM. Therefore, three of the four data input / output terminals I / O _{0 to} I / O ₃ are used for inputting the comparison voltages V _S1 and V _S2 and outputting the comparison result C. In the case of the × 1 bit DRAM as in the previous embodiment, for example, D _out is applied to the output of C,
_S1 and _VS2 are input to _Din or 2 of the address terminals.
You just have to use them.

An advantage of this embodiment is that it is possible to determine by one inspection whether or not _VL is within a certain range. For example,
_Assume that _VL must be higher than _VLmin and lower than _VLmax . To check this, V _S1 = V _Lmin , V _S2
= V _Lmax . C is high only when V _Lmin <V _L <V _Lmax .

FIG. 57 shows another embodiment of the present invention.

The difference from the above-described two embodiments is that the comparison voltage V _S is designated by a digital signal, and the comparison voltage V _S is converted from a digital signal to produce the comparison voltage V _S by a DAC. In this embodiment, the input terminal of the digital signal S ₀ to S ₃ are also used as address terminal A _i.

The input digital signal is converted by the DA converter 10 into an analog voltage V _S. The reference voltage applied to the DA converter may be V _CC , but a dedicated voltage V _R is more desirable. This is because the V _CC dependency of the internal voltage _VL can be measured. Input terminal of the V _R In this example,
It is also used as a data input terminal D _in the DRAM.

The feature of this embodiment is that it is an input digital signal as well as an output. Therefore, the test by the memory tester is further facilitated as compared with the previous embodiment. In this embodiment, although the comparison voltage is only one V _S ,
Needless to say, two pieces may be used as in the previous embodiment.

Next, a DA converter used in this embodiment will be described.

FIG. 58A shows an example of a DA converter. In the figure, 61 and 62 are inverters, R and 2R
Is resistance. Wherein the power supply of the inverter 62 is the reference voltage V _R. When the digital signal from the terminal S ₀ to S ₃ are input, the output voltage of the inverter 62 becomes V _R or 0V according to the input signal. Voltage output V _S is given by _{V 8 = (V R / 16} ) · (8S 3 + 4S 2 + 2S 1 + 1S 0) ... (2). However, it is assumed that the output impedance of the inverter 62 is sufficiently smaller than the resistances R and 2R.

FIG. 58B shows another embodiment of the DA converter. In the figure, 71 is a decoder, 72 is a MOS transistor, and R is a resistor. This circuit selects one of a voltage V _i = (i / 16) · V _r (i = 0 to 15) (3) obtained by dividing the reference voltage V _R by resistance and sets the selected output as the output V _S. This choice is
A signal T obtained by decoding the input signals S _{0 to} S ₃ by the decoder 71
It is carried out by ₀ ~T _15. The feature of this circuit, is sufficiently large if (input impedance of the comparator circuit 5 in FIG. 57) the impedance of the load (circuit of Figure 54, this condition is satisfied), the output voltage V _S is MOS transistor 7
2 is not affected by the on-resistance.

FIGS. 58 (a) and 58 (b) show the case where 4
It is a bit DA converter. However, it goes without saying that the number of bits may be increased or decreased depending on how accurately it is necessary to set internal voltage _VL .

FIG. 59 shows still another embodiment of the present invention.
The feature of this embodiment is that the internal voltage _VL is AD-converted and output. Therefore, the register 80 for storing the digital signal S ₀ to S ₃ are provided. Hereinafter, the operation of this embodiment will be described with reference to the timing chart of FIG.

The generation of the test enable signal TE by the combination of the timings of / RAS, / CAS and / WE is the same as in the previous embodiment. The contents of the register 80 at this time, only the most significant bit S ₃ is "1", the other is set to a state of "0". At this time, the comparison voltage V _S is V _R
/ 2. Results of the comparison between the V _S and the internal voltage V _L, if C = 1 i.e. V _L> V _R / 2, the upper bits S ₃ top is kept as it is "1", C = 0 i.e. V _L <V
_R / 2 if S ₃ is reset to "0".

[0214] of the next register S ₂ is set to "1". At this time, the comparison voltage V _S is V _R / 4 or 3V _R /
4. Results of the comparison between the V _S and the internal voltage V _L, C
= 1 if S ₂ is directly held at "1", C = 0 if S ₂ is reset to "0". Similarly,
S ₁ and S ₀ are sequentially determined.

The above operation is performed in synchronization with the clock. In this embodiment, / CAS is used as a clock. That is, first, / CAS is set to a low level prior to / RAS, and the _VL inspection mode is designated. This allows TE
Becomes a high level. Next, by keeping / RAS low and raising / lowering / CAS, the above AD
Conversion is performed. During this time, the result of each comparison appears at the output terminal D _out in order, so that the result of AD conversion can be known by observing D _out .

[0216]

According to the present invention, since the test result of the internal voltage is output to the outside as a digital signal, it is easy to externally test the internal voltage with a memory tester or the like.

As described above, according to the present invention, an ultra-large-scale semiconductor integrated circuit can be actually provided.
Stable operation and the like can also be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a first group of the present invention.

FIG. 2 is a diagram illustrating a problem discovered by the present inventors.

FIG. 3 is a diagram illustrating a problem discovered by the present inventors.

FIG. 4 is a diagram illustrating a problem discovered by the present inventors.

FIG. 5 is a diagram illustrating a problem discovered by the present inventors.

FIG. 6 is a diagram illustrating a problem discovered by the present inventors.

FIGS. 7A and 7B are circuit diagrams illustrating a conventional technique.

FIG. 8 is a diagram illustrating an example of a first group of the present invention.

FIG. 9 is a diagram illustrating an example of the first group of the present invention.

FIG. 10 is a view for explaining an example of the first group of the present invention.

FIG. 11 is a view for explaining an example of the first group of the present invention.

FIG. 12 is a diagram illustrating an example of the first group of the present invention.

FIG. 13 is a view for explaining an example of the first group of the present invention.

FIG. 14 is a view for explaining an example of the first group of the present invention.

FIG. 15 is a diagram illustrating an example of the first group of the present invention.

FIG. 16 is a view for explaining an example of the first group of the present invention.

FIG. 17 is a view for explaining an example of the first group of the present invention.

FIG. 18 is a view for explaining an example of the first group of the present invention.

FIG. 19 is a view for explaining an example of the first group of the present invention.

FIG. 20 is a diagram illustrating an example of the first group of the present invention.

FIG. 21 is a view for explaining an example of the first group of the present invention.

FIG. 22 is a view for explaining an example of the first group of the present invention.

FIG. 23 is a view for explaining an example of the first group of the present invention.

FIG. 24 is a view for explaining an example of the second group of the present invention.

FIG. 25 is a diagram illustrating an example of the second group of the present invention.

FIG. 26 is a view for explaining an example of the second group of the present invention.

FIG. 27 is a diagram illustrating an example of the second group of the present invention.

FIG. 28 is a diagram illustrating an example of the second group of the present invention.

FIG. 29 is a diagram illustrating an example of the second group of the present invention.

FIG. 30 is a view for explaining an example of the second group of the present invention.

FIG. 31 is a view for explaining an example of the second group of the present invention.

FIG. 32 is a view for explaining an example of the second group of the present invention.

FIG. 33 is a view for explaining an example of the second group of the present invention.

FIG. 34 is a view for explaining an example of the second group of the present invention.

FIG. 35 is a view for explaining an example of the second group of the present invention.

FIG. 36 is a view for explaining an example of the second group of the present invention.

FIG. 37 is a view for explaining an example of the second group of the present invention.

FIG. 38 is a view for explaining an example of the second group of the present invention.

FIG. 39 is a view for explaining an example of the second group of the present invention.

FIG. 40 is a view for explaining an example of the second group of the present invention.

FIG. 41 is a view for explaining an example of the second group of the present invention.

FIG. 42 is a view for explaining an example of the second group of the present invention.

FIG. 43 is a view for explaining an example of the second group of the present invention.

FIG. 44 is a view for explaining an example of the second group of the present invention.

FIG. 45 is a view for explaining an example of the second group of the present invention.

FIG. 46 is a view for explaining an example of the second group of the present invention.

FIG. 47 is a view for explaining an example of the second group of the present invention.

FIG. 48 is a view for explaining an example of the second group of the present invention.

FIG. 49 is a view for explaining an example of the second group of the present invention.

FIG. 50 is a view for explaining an example of the second group of the present invention.

FIG. 51 is a diagram illustrating an example of the second group of the present invention.

FIG. 52 is a view for explaining an example of the third group of the present invention.

FIG. 53 is a view for explaining an example of the third group of the present invention;

FIG. 54 is a view for explaining an example of the third group of the present invention.

FIG. 55 is a view for explaining an example of the third group of the present invention.

FIG. 56 is a view for explaining an example of the third group of the present invention.

FIG. 57 is a view for explaining an example of the third group of the present invention.

FIG. 58 is a view for explaining an example of the third group of the present invention;

FIG. 59 is a view for explaining an example of the third group of the present invention.

FIG. 60 is a view for explaining an example of the third group of the present invention.

FIG. 61 is a view for explaining an example of the second group of the present invention.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 21/8242 G11C 11/34 354F 371A H01L 27/10 681F (72) Inventor Masakazu Aoki 1-280, Higashi Koigakubo, Kokubunji-shi, Tokyo Stock (72) Inventor Kiyoo Ito 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Tokyo, Japan Inside (72) Inventor Yoshinobu Nakago 1-1280 Higashi Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Inside the Central Research Laboratory (72) Inventor Shinichi Ikenaga 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory Hitachi, Ltd. (72) Inventor Jun Eto 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo (72) Inventor Norio Miyake Above Kodaira City, Tokyo 1450 Honcho, Musashi Plant, Hitachi, Ltd. (72) Inventor Takaaki Noda 1450, Kamisumi Honcho, Kodaira, Tokyo, Japan (72) Inventor Hitoshi Tanaka 5--20, Josui Honcho, Kodaira, Tokyo No. 1 Nichichi Super LSI Engineering Co., Ltd.

Claims (9)

[Claims] A first power supply terminal and a second power supply terminal for receiving an external voltage; and an internal voltage generation circuit for generating an internal voltage from the external voltage with reference to a potential supplied to the first power supply terminal. An internal circuit that operates using the internal voltage as a power supply, wherein the internal voltage generation circuit generates a reference voltage formed based on a potential supplied to the first power supply terminal; A drive circuit that supplies the internal voltage formed based on the reference voltage to the internal circuit, wherein the reference voltage generation circuit is disposed near the first power supply terminal, and the drive circuit is The reference voltage generation circuit is disposed apart from the reference voltage generation circuit so as to be in the vicinity of an internal circuit, and the reference voltage output from the reference voltage generation circuit is supplied to the drive circuit by reference voltage distribution wiring Wherein a being. 2. A first power supply terminal and a second power supply terminal for receiving an external voltage, and an internal voltage generation circuit for generating an internal voltage from the external voltage with reference to a potential supplied to the first power supply terminal. A plurality of internal circuits that operate using the internal voltage as a power supply, wherein the internal voltage generation circuit generates a reference voltage generated based on a potential supplied to the first power supply terminal. And a plurality of drive circuits provided corresponding to each of the plurality of internal circuits and configured to supply the internal voltage formed based on the reference voltage to the corresponding internal circuit. A circuit is arranged near the first power supply terminal, and each of the plurality of drive circuits is arranged at a distance from the reference voltage generation circuit so as to be near a corresponding internal circuit. The reference voltage output from the reference voltage generating circuit, wherein a supplied by the reference voltage distribution wiring to the plurality of drive circuits. 3. The semiconductor device according to claim 1, wherein a conductor which is set to a fixed potential is provided immediately below said reference voltage distribution wiring. 4. The semiconductor device according to claim 1, wherein a conductor which is set to a fixed potential is provided immediately above the reference voltage distribution wiring. 5. The semiconductor device according to claim 1, wherein a ground potential is supplied to said first power supply terminal. 6. The semiconductor device according to claim 1, wherein a conductor which is set to a fixed potential is provided adjacent to both sides of said reference voltage distribution wiring. 7. The semiconductor device according to claim 1, wherein said internal voltage is lower than said external voltage. 8. The driving circuit according to claim 1, wherein the driving circuit has a gate controlled based on a differential amplifier receiving the reference voltage at one input terminal and a signal output from the differential amplifier. Output MOSF for outputting the internal voltage
A semiconductor device comprising: ET; and feedback means for inputting a signal based on the output of the output MOSFET to the other input terminal of the differential amplifier. 9. The semiconductor device according to claim 1, wherein said semiconductor device is a dynamic memory including a plurality of dynamic memory cells.