KR0130374B1 - Kr/ method for manufacturing tfd semiconductor device - Google Patents
Kr/ method for manufacturing tfd semiconductor deviceInfo
- Publication number
- KR0130374B1 KR0130374B1 KR1019940012360A KR19940012360A KR0130374B1 KR 0130374 B1 KR0130374 B1 KR 0130374B1 KR 1019940012360 A KR1019940012360 A KR 1019940012360A KR 19940012360 A KR19940012360 A KR 19940012360A KR 0130374 B1 KR0130374 B1 KR 0130374B1
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- emitter
- impurity diffusion
- semiconductor device
- ion implantation
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims abstract description 28
- 238000009792 diffusion process Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 6
- 230000007774 longterm Effects 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 230000008021 deposition Effects 0.000 description 6
- 230000006378 damage Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 3
- 238000005275 alloying Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
제1도 (a) 내지 (e)는 일반적인 ESD 보호회로의 구성도.1 (a) to (e) is a configuration diagram of a general ESD protection circuit.
제2도 (a) 내지 (g)는 종래의 TFD 반도체 소자의 공정단면도.2 (a) to (g) are process cross-sectional views of a conventional TFD semiconductor device.
제3도 (a) 내지 (e)는 본 발명의 TFD 반도체 소자의 공정단면도.3 (a) to 3 (e) are process cross-sectional views of the TFD semiconductor device of the present invention.
제4도 (a) 내지 (e)는 본 발명의 다른 실시예를 나타낸 TFD 반도체 소자의 공정 단면도.4A to 4E are process cross-sectional views of a TFD semiconductor device according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : p형 반도체기판 22 : 초기산화막21: p-type semiconductor substrate 22: initial oxide film
23, 27 : 포토레지스트 24 : 버퍼산화막23, 27: photoresist 24: buffer oxide film
25 : 질화막 26 : 필드산화막25: nitride film 26: field oxide film
28 : 에미터 불순물확산영역 29 : 콜렉터 불순물확산영역28 emitter impurity diffusion region 29 collector impurity diffusion region
30 : 고온저압증착(HLD)산화막 31 : BPSG층30: high temperature low pressure deposition (HLD) oxide film 31: BPSG layer
32,33 : 메탈전극32,33: metal electrode
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 방전경로를 벌크(Bulk) 내부에 형성하여 ESD(Electro Static Discharge)방전능력을 향상시키는데 적당하도록 한 TFD(Thick Field Device) 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a thick field device (TFD) semiconductor device suitable for improving electrostatic discharge (ESD) discharge capability by forming a discharge path inside a bulk. It is about.
일반적으로 ESD(Electro Static Discharge)에 의한 디바이스의 파괴는 소자의 열화에 의한 배선막과 산화막의 파괴를 들 수 있는데, ESD에 의한 디바이스 파괴를 줄이기 위해 디바이스에 대전하는 ESD를 내부 셀에는 영향을 주지않고 순차적으로 방전시키기 위해 적절한 보호회로를 개설한다.In general, the destruction of a device by electrostatic discharge (ESD) may include the destruction of the wiring film and the oxide film due to the deterioration of the device, which does not affect the internal cells of the ESD charged to the device to reduce the device destruction by the ESD. In order to discharge sequentially, an appropriate protection circuit is established.
ESD 보호회로는 외부(사람, 기계장치) 및 주변회로에서 발생하는 ESD로부터 내부셀을 보호하기 위하여 반도체 칩 설계시에 구성하는 것으로 일반적인 ESD 보호회로의 구성도를 나타낸 제1도 (a) 내지 (e)에서와 같이 PN 접합의 다이오드를 사용하여 구성하는 방법과, MOS 트랜지스터 또는 필드 산화 디바이스(Thick Field Device)를 사용하여 보호회로를 구성하는 방법등이 있다.The ESD protection circuit is configured at the time of semiconductor chip design to protect the internal cells from ESD generated from external (human, mechanical) and peripheral circuits. As in e), there is a method of using a diode of a PN junction and a method of configuring a protection circuit using a MOS transistor or a thick field device.
이하, 첨부된 도면을 참고하여 종래의 TFD 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional TFD semiconductor device will be described with reference to the accompanying drawings.
제2도 (a) 내지 (g)는 종래의 TFD 반도체 소자의 공정 단면도이다.2A to 2G are cross-sectional views of a conventional TFD semiconductor device.
먼저, 제2도 (a)에서와 같이 P형 반도체 기판(1)상에 후공정에서 기판의 계면에 가해지는 스트레스를 줄이기 위해 초기산화막(2)을 210Å~250Å 정도의 두께로 형성하고 상기의 초기산화막(2) 전면에 질화막(3)을 1400±140Å 정도의 두께로 증착한다.First, as shown in FIG. 2 (a), on the P-type semiconductor substrate 1, an initial oxide film 2 is formed to a thickness of about 210 kPa to about 250 kPa in order to reduce the stress applied to the interface of the substrate in a later step. The nitride film 3 is deposited on the entire surface of the initial oxide film 2 to a thickness of about 1400 ± 140 mm 3.
이어, 제2도 (b)에서와 같이 상기의 질화막(3)상에 포토레지스트(4)를 도포하고 노광 및 현상공정으로 패터닝하여 필드영역상의 질화막(3)을 제거한후, 필드영역에 이온 주입을 실시하여 필드영역의 절연성을 증가시키고 주입되는 이온의 농도를 높혀 임계전압(Threshold Voltage)값을 증가시킨다.Subsequently, as shown in FIG. 2 (b), the photoresist 4 is applied onto the nitride film 3 and patterned by an exposure and development process to remove the nitride film 3 on the field region, and then ion implantation into the field region. By increasing the insulation of the field region and increasing the concentration of implanted ions, the threshold voltage value is increased.
그리고 제2도 (c)에서와 같이, 필드 이온 주입시 마스크로 사용했던 포토레지스트(4)를 제거하고 질화막(3)을 마스크로 산화 공정을 실시하여 일정 두께의 필드산화막(5)을 형성한다.As shown in FIG. 2 (c), the photoresist 4 used as a mask during field ion implantation is removed, and the nitride film 3 is subjected to an oxidation process using a mask to form a field oxide film 5 having a predetermined thickness. .
이어, 제1도 (d)에서와 같이 상기 필드산화막(5)을 마스크로 하여 엑티브 영역에 n형 불순물 이온주입(As+, 80KeV, 4.5×1015atoms/㎠)을 실시하여 에미터 불순물 확산영역(6)과 콜렉터 불순물 확산영역(7)을 형성한다.Next, as shown in FIG. 1 (d), n-type impurity ion implantation (As + , 80 KeV, 4.5 x 10 15 atoms / cm 2) is applied to the active region using the field oxide film 5 as a mask to diffuse emitter impurities. The region 6 and the collector impurity diffusion region 7 are formed.
그리고 제2도의 (e)에서와 같이 전면에 고온 저압 증착산화막(High Temperature Low Pressure Deposition : HLD)(8)을 6000Å 정도의 두께로 형성하고 제1도 (f)에서와 같이 상기의 고온 저압 증착산화막(8)사에 평탄화용 보호막(BPSG)(9)을 7000Å 정도의 두께로 형성하여 절연막을 형성한다.A high temperature low pressure deposition (HLD) film (8) is formed on the entire surface as shown in FIG. 2 (e) to a thickness of about 6000 kPa, and the high temperature low pressure deposition as shown in FIG. A planarization protective film (BPSG) 9 is formed on the oxide film 8 to a thickness of about 7000 Å to form an insulating film.
이어, 제2도 (g)에서와 같이 액티브 영역사의 평탄화용 보호막(BPSG)(9), 고온 저압증착산화막(8)의 절연막을 일정 넓이 선택적으로 식각하여 콘택 개구부를 형성한후, 전면에 메탈전극(10)(11)을 형성하기 위한 135Å~165Å 두께의 Mosix와 6750Å~8250Å 두께의 Al을 증착한 후 필드영역상의 금속층을 제거하고 합금화 공정을 시행하여 메탈전극(10)(11)을 형성한다.Subsequently, as shown in FIG. 2G, the planarization protective film (BPSG) 9 of the active region yarn and the insulating film of the high temperature low pressure deposition oxide film 8 are selectively etched to a predetermined extent to form a contact opening, and then a metal Metal electrodes 10 and 11 are formed by depositing 135 μm to 165 μm thick Mosix and 6750 μm to 8250 μm thick Al to remove the metal layer on the field region and performing an alloying process. do.
상기와 같이 구성된 종래의 TFD 반도체 소자는 필드산화막의 폭이 3~4㎛(베이스의 실효폭)이고 필드산화막의 양측 p형 반도체기판(1)내에 형성된 불순물 확산영역(6)(7)이 콜렉터 불순물 확산영역(7)은 입력 패드(Input pad)에 연결되고 에미터 불순물 확산영역(7)은 Vcc 및 Vss 단자에 연결되어 상기의 TFD 반도체 소자에 ESD가 대전되면 에미터 및 콜렉터 불순물 확산영역(6)(7)과 p형 반도체기판(1)사이에 브레이크 다운 전류가 흐르게 되고 p형 반도체 기판(1)에 인가되는 ON 전압에 의해 소자가 스냅 백(Snap Back) 상태로 들어가 ESD를 방전하게 된다.In the conventional TFD semiconductor device constructed as described above, the field oxide film has a width of 3 to 4 탆 (effective width of the base) and the impurity diffusion regions 6 and 7 formed in both p-type semiconductor substrates 1 of the field oxide film are collectors. The impurity diffusion region 7 is connected to an input pad, and the emitter impurity diffusion region 7 is connected to the Vcc and Vss terminals. When ESD is charged to the TFD semiconductor device, the emitter and collector impurity diffusion regions ( 6) A breakdown current flows between (7) and the p-type semiconductor substrate 1, and the element enters the snap back state to discharge the ESD by the ON voltage applied to the p-type semiconductor substrate 1 do.
그러나 상기와 같은 TFD 반도체 소자는 디바이스에 ESD가 대전되어 ON되었을때 필드산화막이 형성된 기판의 계면에 집중적으로 전류의 흐름이 생겨 열화에 의한 소자의 파괴로 누설전류(Leakage Current)가 발생하는 문제점이 있었다.However, the TFD semiconductor device as described above has a problem that leakage current occurs due to destruction of the device due to deterioration because current flows intensively at the interface of the substrate where the field oxide film is formed when the device is charged with ESD. there was.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로써, ESD 방전경로를 벌크(Bulk) 내부에 형성하는 방법으로 디바이스에 대전하는 ESD의 방전능력을 향상시킨 TFD 반도체 소자를 제공하는데 그 목적이 있다.An object of the present invention is to provide a TFD semiconductor device that improves the discharge capacity of ESD to charge the device by forming an ESD discharge path in the bulk to solve the above problems. have.
상기와 같은 목적을 달성하기 위한 본 발명의 TFD 반도체 소자의 제조방법을 첨부된 도면을 참고하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method for manufacturing a TFD semiconductor device of the present invention for achieving the above object is as follows.
제3도 (a) 내지 (e)는 본 발명의 TFD 반도체 소자의 공정단면도이고, 제4도 (a) 내지 (e)는 본 발명의 다른 실시예를 나타낸 TFD 반도체 소자의 공정단면도이다. 먼저 제3도 (a)에서와 같이, p형 반도체기판(21)의 초기산화막(22)상에 포토레지스트(23)를 도포하고 노광 및 현상 고정으로 채널영역상의 포토레지스트(23)만 제거되도록 패터닝하고 상기의 패터닝되어진 포토레지스트(23)을 마스크로 하여 노출된 p형 반도체 기판(21)에 BF2 +불순물 이온을 80KeV 에너지로 4.0×1013atoms/㎠의 농도로 이온 주입(Ion Implantation)을 실시한다.3A to 3E are process cross-sectional views of the TFD semiconductor device of the present invention, and FIGS. 4A to 4E are process cross-sectional views of the TFD semiconductor device according to another embodiment of the present invention. First, as shown in FIG. 3 (a), the photoresist 23 is coated on the initial oxide film 22 of the p-type semiconductor substrate 21, and only the photoresist 23 on the channel region is removed by exposure and development fixing. patterning and ion implantation of BF 2 + impurity ions to the p-type semiconductor substrate 21 exposed by the photoresist (23) been the patterning of a mask at a concentration of 4.0 × 10 13 atoms / ㎠ to 80KeV energy (ion implantation) Is carried out.
이어, 제3도 (b)에서와 같이 상기의 포토레지스트(23) 및 초기산화막(22)을 제거하고 전면에 210Å~250Å 정도의 두께로 버퍼산화막(24)를 형성하고 전면에 1400±140Å 정도의 두께로 질화막(25)을 형성하고 상기의 질화막(25)을 채널영역상에만 남도록 제거한다.Subsequently, as shown in FIG. 3 (b), the photoresist 23 and the initial oxide film 22 are removed, and a buffer oxide film 24 is formed on the front surface with a thickness of about 210Å to 250Å and about 1400 ± 140Å The nitride film 25 is formed to a thickness of and the nitride film 25 is removed so as to remain only on the channel region.
그리고 제3도 (c)에서와 같이, 상기의 질화막(25)을 마스크로 하여 채널영역 이외의 p형 반도체 기판(21)에 두꺼운 필드산화막(Thick Field Oxide)(26)을 5000±600Å의 두께로 형성한다.As shown in FIG. 3 (c), the thick field oxide film 26 is formed on the p-type semiconductor substrate 21 other than the channel region by using the nitride film 25 as a mask. To form.
이어, 제3도 (d)에서와 같이, 상기의 공정에서 마스크로 사용된 질화막(25)을 제거하고 전면에 포토레지스트(27)를 도포하고 노광 및 현상 공정으로 후공정에서 불순물 이온 주입을 할 부분만 제거되도록 패터닝하여 노출된 필드산화막(26)을 제거하고 As+불순물 이온을 80KeV 에너지로 4.5×1015atoms/㎠의 농도로 이온 주입을 실시하여 에미터 및 콜렉터 불순물 확산영역(28)(29)을 형성한다.Subsequently, as shown in FIG. 3 (d), the nitride film 25 used as a mask in the above process is removed, the photoresist 27 is applied to the entire surface, and impurity ion implantation is performed in a post process by an exposure and development process. The exposed field oxide film 26 was removed by patterning only portions, and As + impurity ions were implanted at a concentration of 4.5 × 10 15 atoms / cm 2 at 80 KeV energy to emitter and collector impurity diffusion regions 28 ( 29).
그리고, 제3도 (e)에서와 같이, 상기 공정에서 마스크로 사용된 포토레지스트(27)를 제거하고 전면에 고온 저압증착(High Temperature Low Pressure Deposition : HLD) 산화막(30)을 5500Å~7500Å 정도의 두께로 BPSG(Boron Phosphorus Silicate Glass)층(31)을 형성하여 절연막을 형성한다.Then, as shown in FIG. 3 (e), the photoresist 27 used as a mask in the process is removed, and the high temperature low pressure deposition (HLD) oxide film 30 on the front surface is about 5500 Pa ~ 7500 Pa. A BPSG (Boron Phosphorus Silicate Glass) layer 31 is formed to form an insulating film.
그리고, 에미터 및 콜렉터 불순물 확산영역(28)(29)상의 고온 저압 증착(HLD) 산화막(30)과 BPSG층(31)의 절연막을 선택적으로 제거하여 콘택 개구부를 형성하고 전면에 150±15Å 두께의 Mosix와 7500±750Å 두께의 Al을 차례로 증착하고 에미터 및 콜렉터 불순물 확산영역(28)(29)상에만 남도록 선택적으로 식각한후 합금화공정(450℃, N2/H2, 20Min)을 시행하여 메탈전극(33)(32)을 형성한다.Then, the high temperature low pressure deposition (HLD) oxide film 30 on the emitter and collector impurity diffusion regions 28 and 29 and the insulating film of the BPSG layer 31 are selectively removed to form a contact opening, and the thickness of the surface is 150 ± 15 전면. Mosix and Al with a thickness of 7500 ± 750Å are deposited in this order, and selectively etched to remain on the emitter and collector impurity diffusion regions 28 and 29, followed by alloying process (450 ℃, N 2 / H 2 , 20Min). The metal electrodes 33 and 32 are formed.
그리고 제4도 (a) 내지 (e)는 본 발명의 다른 실시예를 나타낸 것으로, 에미터 및 콜렉터 불순물 확산영역(28)(29)을 형성하기 위한 이온 주입공정을 실시하기 전에 노출된 p형 반도체기판(21)을 일정부분 식각하여 트렌치(Trench)구조를 갖게 한 것이다.4 (a) to 4 (e) show another embodiment of the present invention, wherein the p-type is exposed before the ion implantation process for forming the emitter and collector impurity diffusion regions 28 and 29 is performed. A portion of the semiconductor substrate 21 is etched to have a trench structure.
상기와 같은 공정으로 제조된 본 발명의 TFD 반도체 소자는 ESD가 대전되었을때 서지(Surge) 전류가 p형 반도체 기판으로 유입되어 에미터 불순물 확산영역과 콜렉터 불순물 확산영역이 NPN 바이폴라 트랜지스터의 동작으로 들어가 대전된 ESD를 방전하게 된다.In the TFD semiconductor device of the present invention manufactured by the above process, when the ESD is charged, surge current flows into the p-type semiconductor substrate so that the emitter impurity diffusion region and the collector impurity diffusion region enter the operation of the NPN bipolar transistor. The charged ESD will be discharged.
p형 반도체 기판의 베이스 실효폭은 2~3㎛로써 콜렉터에 서지(Surge) 전류가 인가되지 않으면 NPN 바이폴라 트랜지스터는 OFF 상태로 남게 된다.The base effective width of the p-type semiconductor substrate is 2 to 3 μm, and the NPN bipolar transistor is left in the OFF state when no surge current is applied to the collector.
상기와 같은 동작을 하는 본 발명의 TFD 반도체 디바이스는 종래의 TFD 반도체 디바이스와 같이 전류의 흐름이 필드 산화막의 계면에 집중되지 않고, 필드 산화막을 식각하여 에미터 및 콜렉터 불순물 확산영역이 형성하는 방법으로 전류의 흐름이 벌크(Bulk) 내부에서 이루어져 반도체 기판의 계면 열화에 의한 소자 파괴를 줄일 수 있다.In the TFD semiconductor device of the present invention which operates as described above, as in the conventional TFD semiconductor device, the current flow is not concentrated at the interface of the field oxide film, and the field oxide film is etched to form an emitter and a collector impurity diffusion region. Since current flows in the bulk, device destruction due to interfacial degradation of the semiconductor substrate can be reduced.
그러므로 본 발명의 TFD 반도체 소자를 사용하여 ESD 보호회로를 구성할 경우 작은 레이 아웃(Layout) 면적으로 뛰어난 ESD 방전능력을 갖게하는 효과가 있다.Therefore, when the ESD protection circuit is configured using the TFD semiconductor device of the present invention, there is an effect of having excellent ESD discharge capability with a small layout area.
Claims (5)
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