KR0128880B1 - Memory structure for motion compensation used in a picture decoder - Google Patents

Abstract

A memory structure for motion compensation connects a multiplexor(50) to four DRAM(30a-30d)'s output side where previous frame data is being stored and connects two dual ports SRAM(60a,60b) storing pixel data that is needed for motion compensation at an output side of this multiplexor(50). Pixel data for motion compensation stored at two dual ports SRAM(60a,60b) is inputted to a half-pixel motion compensation part(70) after read by read address signal from address generation part(40). After being motion compensated, the pixel data is supplied to a between frame difference pulse code(10) and then outputs to display part finally as a data signal altered to between frame difference pulse code.

Description

Memory Structure for Motion Compensation in Image Decoder

1 is a block diagram of a memory structure for motion compensation in an image decoder according to a preferred embodiment of the present invention.

2 is a block diagram of a motion compensation memory structure in a conventional video decoder.

* Explanation of symbols for main parts of the drawings

10: differential pulse code modulation unit between frames 20: demultiplexer

30, 60: memory, 30a: DRAM 40: address generator

50: multiplexer 60a: SRAM

70: half-pixel motion compensation unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion compensation memory structure used in a video decoder, and in particular, operates at a high frequency such as high definition television (abbreviated as HDTV or lower definition HDTV) and performs motion compensation of MPEG (Moving Picture Experts Group) -II. A memory structure for motion compensation in an image decoder using the method is provided.

Nowadays, the method of HDTV has been decided to have a high frequency and almost compatible with the MPEG-II method. The MPEG-II method is composed of three pictures, I, B, and P, as is well known in the art. Here, I picture means intra picture, P picture means predictive picture by forward motion compensation by I picture, B picture means I and P picture or bi-direction by P and P picture Predicted image by motion compensation of bi-direction). In addition, according to the MPEG-II method, motion compensation with better efficiency is performed through various motion compensation functions.

In addition, as an example of the above method, there is a method of increasing the efficiency of motion compensation using motion compensation of a frame shape, a field shape, and motion compensation of a dual prime.

Among the motion compensation methods, first, frame-type motion compensation is performed from the data of the macro block size of the anchor frame found by the motion vector in order to process the data of the macro block in the same manner as the well-known general motion compensation method. In this case, motion compensation in the form of a field is performed by finding a motion vector of two fields in a macroblock and finding field data at different positions. In this case, the data of the upper field is processed first, followed by the data of the lower field.

On the other hand, in the above-described motion compensation method, the dual prime method is a method that can appear when P pictures are continuous. Therefore, the motion compensation in the forward direction is always performed because only the P picture is performed. The processing method here compensates for the motion by the values of two fields, respectively, obtained from two fields of an I picture or a P picture, which are previous anchor frames. In this case, when a single motion vector is taken in the same field as the field to be processed, the motion vector is used as it is, and in the case of different fields, a new motion vector is calculated and processed by a predetermined method.

The present invention relates to the improvement of the memory structure in a video decoder using the motion compensation method of MPEG-II substantially in the motion compensation method as described above.

2 is a block diagram showing an example of a memory structure in a conventional video decoder. In the conventional example, the memory is configured in units of fields by motion compensation such as dual prime. In addition, a plurality of DRAMs (Dynamic Random Access Memory) is used as the memory 30, and a plurality of dual port static random access memories (SRAMs), which are small memories, are connected to the outputs of the plurality of DRAMs. In the port SRAM, only the search area data is stored, thereby compensating for the DRAM speed problem (row address change, etc.).

As shown in FIG. 2, in the memory structure of a conventional video decoder, the memory 30 is connected to four DRAMs 32a-32d and four DRAMs respectively for storing data of forward and reverse anchor frames. It is composed of four SRAMs 34a-34d for storing each pixel data necessary for motion compensation, and has a structure for storing data of two frames in units of fields.

In addition, in order to process one pixel in motion compensation, data of up to two pixels must be read from the memory 30. This case corresponds to both the forward and reverse motion vectors and the dual prime motion compensation. As a result, the multiplexer 50 is required because valid data for motion compensation is output only in up to two of the four memories.

Therefore, the pixel data read in accordance with the read address from the address generator 40 is input to the half-pixel motion compensator 70 through the multiplexer 50, and the motion is performed through the half-pixel motion compensator 70. The compensated data signal is provided to the inter frame differential pulse code modulator 10. In the half-pixel motion compensator 70, the half-pixel position is located at the center of a single pixel, so that the single pixel data values are located close to the horizontal and vertical axes with respect to the half-pixel position to be compensated. This is done by taking an average.

As a result, the inter-frame differential pulse code modulator 10 is finally reconstructed based on the inverse DCT signal from the input side and the motion compensated signal from the half-pixel motion compensator 70, and then modulated with a full code. By outputting the signal to the display unit not shown in FIG. 2, a desired image of high quality is displayed on the screen. However, in the memory structure of the conventional video decoder as described above, although the data valid for motion compensation is output only in up to two of the four memories, as shown in FIG. 2, four dual-port SRAMs are shown. By having 34a-34d, not only is it disadvantageous in implementing the system, but also there is a problem that a rise in manufacturing cost is caused.

Accordingly, an object of the present invention is to provide a motion compensation memory structure for an image decoder capable of simplifying the structure while performing the same function.

In order to achieve the above object, the present invention performs half-pixel motion compensation to restore the original signal to the data signal read from the memory means in which the data of the motion-compensated previous frame is stored. A motion compensation memory structure in a video decoder for performing inter-frame differential pulse code modulation, wherein the memory means comprises: a plurality of memories, each of which is inter-frame based on a write address signal from an address generating means; A first memory group for storing data of a previous frame input from a differential pulse code modulator through a demultiplexer; A multiplexer for transferring pixel data for the half-pixel motion compensation read out from the first memory group in accordance with a read address from the address generating means; Two memory units having a smaller capacity than each of the memories included in the first memory group, wherein each of the small memory units receives pixel data necessary for the half-pixel motion compensation provided from the multiplexer from the address generating means. A memory structure for motion compensation in an image decoder comprising a second memory group for storing in accordance with a write address signal is provided.

In the motion compensation memory structure according to the present invention having the above configuration, substantially the first memory is composed of four DRAMs and the second memory is composed of two SRAMs.

Other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram of a motion compensation memory structure in an image decoder according to a preferred embodiment of the present invention.

As shown in the figure, the memory structure according to the present invention includes a plurality of dual-port SRAMs 34a-34d and a multiplexer 50 in which pixel data necessary for motion compensation is stored in the conventional memory structure shown in FIG. The characteristic of this is that the input / output positions between the two are changed. More specifically, as shown in FIG. 1, the multiplexer 50 is connected to the output side of the four DRAMs 30a-30b in which data of the previous frame is stored. The main structure is characterized in that two dual-port SRAMs 60a and 60b for storing pixel data necessary for motion compensation are connected to the output side of the multiplexer 50. The object of the invention is achieved.

That is, by moving the position of the multiplexer 50 from the output side of the dual port SRAM to the input side as described above, the number of dual port SRAMs can be reduced from four to two. This is possible because, as described above, valid data for motion compensation is output only in up to two DRAMs out of four DRAMs during half-pixel motion compensation in the image decoder, so only the valid data need be stored in the dual port SRAM.

Therefore, pixel data for motion compensation stored in these two dual-port SRAMs 60a and 60b are read out by the read address signal from the address generator 40, input to the half-pixel motion compensation unit 70, and moved. The data signal finally modulated by the inter-frame differential pulse code is output to the display unit (not shown).

In addition, the memory structure according to the present invention is very advantageous in the implementation of the system by substantially reducing the amount of bus data by the configuration as described above.

As described above, according to the present invention, when a DRAM and a dual port SRAM are used as a frame memory in an image decoder that operates at a high frequency such as an HDTV and has a motion compensation such as the MPEG-II method, the position of the multiplexer is changed to a dual port SRAM. By reducing the number of dual-port SRAMs by moving from the output side to the input side, the manufacturing cost can be reduced and the system can be easily implemented.

Claims (2)

Performs half-pixel motion compensation for restoring the original signal to the data signal read from the memory means in which the data of the motion-compensated previous frame is stored, and performs inter-frame differential pulse code modulation with data signals of the current frame A memory structure for motion compensation in an image decoder, the memory means comprising; A first memory group for storing data of a previous frame, which is input through a demultiplexer from an inter-frame differential pulse code modulator, based on a write address signal from an address generating means; A multiplexer for transferring pixel data for the half-pixel motion compensation read from the first memory group in accordance with a read address from the address generating means; Two memory units having a smaller capacity than each of the memories included in the first memory group, wherein each of the small memory units receives pixel data necessary for the half-pixel motion compensation provided from the multiplexer from the address generating means. And a memory structure for motion compensation in a video decoder comprising a second memory group for storing in accordance with a write address signal. The memory structure of claim 1, wherein the first memory group comprises four DRAMs and each of the two memories included in the second memory group comprises SRAMs.