JPH07336689A - Motion compensation circuit - Google Patents

Abstract

PURPOSE:To access a frame memory at high speed by switching a buffer memory. CONSTITUTION:Difference picture data inputted from an input terminal 11 is written in a buffer circuit 12. This buffer circuit 12 is provided with two sets of the buffer memories of one micro portion, and at the same time as write-in is executed to the buffer memory of one side, read-out can be executed from the buffer memory of the other side. Further, the address of the frame memory to be read out is calculated in accordance with an inputted motion vector 18 by a memory access control circuit 19. Next, necessary reference picture element data is read out of the frame memories 20 to 22, and predictive picture data is calculated in a predictive picture data calculation circuit 17, and is written in the buffer circuit 12. Simultaneously with the write-in, the predictive picture data of a microblock preceding by one is outputted to an addition circuit 13, and is summed with the difference picture data, and is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion compensating circuit, and more particularly to a motion compensating circuit which can be suitably used for a highly efficient coded moving picture decoding device and the like.

[0002]

2. Description of the Related Art Motion compensation (MC: Motion Compensation)
n) is used as a method for improving the coding efficiency in high-efficiency coding of moving images, and is an international standard method of moving-picture high-efficiency coding, MPEG (Moving Pictures Ex
pert Group For details, refer to ISO / IEC, "Information Te"
chnology-Generic Coding of Moving Picturesan
d Associated Audito ", ISO / IEC CD13818-2,
(See 1993.11 etc.). With this technique,
Divide the screen into macroblocks consisting of vertical and horizontal fixed pixels,
For each macroblock, a portion having the smallest difference in the already encoded reference image is searched for, and the motion vector indicating the position on the screen and the difference image data are transmitted. In general, images have a strong correlation between frames, so that a higher compression rate can be obtained by this method than by directly encoding image data. At the time of decoding, a reference image is stored in a frame memory (FM), a relevant part of the reference image is read out according to the motion vector, and the reproduced image is obtained by adding the read image to the difference image data.

In MPEG, there are three types of coded images.
There are various types, and these are combined to form a series of moving images. One is that the prediction is not performed by motion compensation, and the encoding is completed only within the screen (referred to as I-Picture).
Is. The remaining two are for predicting. P-Picture for predicting by referring to the past screen in time, and B-Pictur for performing prediction by referring to the past and future screens.
It is divided into e and. However, the reference screen is limited to the I-Picture or the P-Picture, and is encoded before the B-Picture which is predicted by referring to the I-Picture or the P-Picture. FIG. 14 shows a basic motion compensation configuration. The buffer memory 81 adjusts the timing of the input differential image data and rearranges the pixels, and the frame memories 20 to 22 according to the motion vector. From the memory access control circuit 19 that reads out the necessary portion of the written reference image, the calculation circuit 17 that creates the predicted image data from the read reference image, and the adder circuit 13 that adds the difference image data and the predicted image data. Become. I-
When the Picture is input, since the prediction by the motion compensation is not performed, the output of the prediction image data calculation circuit 17 is set to 0, and the difference image data becomes the output of the addition circuit 13 as it is. ~ 22.

In the P-Picture and B-Picture which perform prediction by motion compensation, the memory access control circuit 19 reads out the necessary portions of the reference image written in the frame memories 20 to 22, and based on this, the estimated image data Prediction image data is created by the calculation circuit 17, and the addition circuit 1
In step 3, the difference image data and the predicted image data are added, and the frame memories 20 to 2 are passed through the memory access control circuit 19.
Write in one of the two. At this time, a predicted image is created from one reference image in P-Picture and a predicted image from two reference images in B-Picture. FIG. 15 shows the operation timing at this time. First, the difference image data for a certain number of pixels is written in the buffer memory. Next, the predicted image data calculation circuit creates predicted image data, the difference image data is read from the difference image data buffer memory in synchronization with this, and the addition circuit creates and outputs the image. Motion compensation can be performed as described above.

[0005]

In the above-mentioned prior art, as the resolution of the coded image increases, the number of pixels in one screen increases and it is necessary to perform the processing at high speed. However, in the conventional configuration, while the difference image data and the predicted image data are being added, the next difference image data cannot be written in the buffer memory, so continuous processing cannot be performed, and speedup is difficult. There was a problem. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a motion compensation circuit that solves the above-described problems in the conventional technique and enables high-speed processing. is there.

[0006]

The above objects of the present invention are as follows:
Motion compensation characterized by having multiple buffer memories for differential image data and predictive image data, writing and reading from different buffer memories, and switching the buffer memory to be used each time a certain number of pixels are processed This is achieved by a circuit or a motion compensation circuit characterized by expanding the data bus width of the frame memory so that a plurality of adjacent pixels can be accessed.

[0007]

In the motion compensation circuit according to the present invention, since the buffer memory is switched, the frame memory can be accessed at high speed, and the difference image data can be continuously input. Higher speed can be realized.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of a motion compensation circuit according to the first embodiment of the present invention. In the figure, 11 is an input terminal for differential image data, and 12 is 1 as shown in FIG.
A buffer circuit having two sets of buffer memories (31) for macroblocks, and 13 an adder circuit. Reference numeral 17 is a predictive image data calculation circuit for calculating predictive image data by various motion compensation methods, 18 is a motion vector input terminal,
Reference numeral 19 denotes a memory access control circuit that controls access to the frame memories 20 to 22. The operation of the motion compensation circuit according to this embodiment configured as described above will be described below. It should be noted that here, as one macroblock, the luminance 16 × 16 (=
256) pixels, color difference 8 × 8 × 2 (C-B, C-R) (= 12
8) Use a block consisting of 384 pixels in total.

The differential image data input from the input terminal 11 is written in the buffer circuit 12. As described above, this buffer circuit has two sets of buffer memories for one macroblock, and it is possible to write to one buffer memory and read from the other simultaneously, and write and read for each macroblock. The buffer memory is switched and used. Therefore, the difference image data of the previous macroblock is sent from the buffer circuit 12 to the addition circuit 13. Since the I-Picture does not perform prediction by motion compensation, the output of the prediction image data calculation circuit 17 is set to 0 so that the difference image data becomes the output of the addition circuit. Prediction P-Picture and B-
In Picture, first, the address of the frame memory to be read by the memory access control circuit 19 is calculated according to the input motion vector 18.

Next, necessary reference image data is read from the frame memories 20 to 22, the predicted image data calculation circuit 17 calculates the predicted image data, and the buffer circuit 1
Write to 2. The buffer circuit 12 also has the same configuration as the buffer circuit for the difference image data, and the predicted image data of the previous macroblock is output to the addition circuit 13 simultaneously with the writing. The adder circuit 13 adds the difference image data and the predicted image data and outputs the result. The image data created by the adder circuit 13 is written in an appropriate frame memory of the frame memories 20 to 22 through the memory access control circuit 19. As described above, the feature of the present invention resides in that each of the input image data and the difference image data has a buffer circuit having a size of two macro blocks, and reading / writing is switched.

As a result, it becomes possible to pipeline the image creation by motion compensation at the macroblock level.
The operation timing at this time will be described with reference to FIG. The differential image data buffer circuit 12 and the buffer memory in the predictive image data buffer circuit 12 are switched between reading and writing in macro block processing units as shown in the figure, and at the time of reading, both are added by an adding circuit 13 and output. To be done. The output image data of the adder circuit 13 is written in an appropriate frame memory through the memory access control circuit 19. As you can see from this figure,
The output data from the adder circuit 13 is continuously obtained, as shown in FIG.
It is possible to perform the motion compensation processing at a higher speed than the conventional example shown in FIG.

FIG. 4 is a block diagram of a motion compensation circuit according to the second embodiment of the present invention. The symbols in the figure are those shown in FIG.
It is attached according to. The differential image data input from the input terminal 11 is written in the buffer circuit 12 as in the case of the embodiment shown in FIG. 1, and the differential image data of the previous macroblock is sent to the adding circuit 13. I-Pi
In the case of cture, as in the case of the embodiment shown in FIG.
The output of the prediction data calculation circuit 17 is set to 0. In P-Picture and B-Picture that perform prediction, first, the memory access control circuit 1 according to the input motion vector 18.
Calculate the address of the frame memory to be read in 9,
Necessary reference image data is read from the frame memories 20 to 22 and written in the buffer circuit 12.

The buffer circuit 12 also has the same configuration as the buffer circuit for the difference image data, and the reference image data of the previous macroblock is sent to the predicted image data calculation circuit 17. In the predicted image data calculation circuit 17, from the reference image data read from the buffer circuit 12,
The predicted image data is calculated and output. The operation of the adder circuit 13 is similar to that of the first embodiment shown in FIG. 1, and the difference image data and the predicted image data are added and output. The image data created by the adder circuit 13 is written in an appropriate frame memory of the frame memories 20 to 22 through the memory access control circuit 19. In the configuration of this embodiment,
Although the capacity of the buffer circuit is increased as compared with the case of the first embodiment shown in FIG. 1, it is not necessary to synchronize the reading of the two reference images used for creating the predicted image data on a pixel-by-pixel basis. The effect of facilitating access control is obtained.

The operation timing at this time is shown in FIG.
The differential image data buffer circuit 12 and the buffer memories in the two sets of reference image data buffer circuits 12 are switched between reading and writing in macroblock processing units as shown in the figure. The reference image data read from the reference image data buffer circuit 12 is operated by the predicted image data calculation circuit 17 to obtain the predicted image data calculation circuit output. This result is further added to the difference image data and addition circuit 13
Are added and output. The output image data of the adder circuit 13 is written in appropriate frame memories 20 to 22 through the memory access control circuit 19. As can be seen from this figure, the output data from the adder circuit is continuously obtained, and it is possible to perform the motion compensation processing at a higher speed than in the conventional example shown in FIG.

In the above description of the operation, the read / write switching control in macroblock processing units is performed in predetermined units based on the clock from the timing controller that controls the timing of the entire motion compensation circuit according to this embodiment. This is done by counting a number of pixels. Figure 6
In the configuration of the first embodiment shown in FIG. 1, between the frame memories 20 to 22 and the memory access control circuit 19, between the memory access control circuit 19 and the predicted image data calculation circuit 17, and the predicted image data calculation circuit. This is an example in which the data bus width between 17 and the buffer circuit 12 is doubled. By doubling the bus width, the read time of the reference image data from the frame memory is shortened.

The reading of the reference image data is the portion where the transfer data amount is the largest in the case of performing motion compensation, and complicated memory access control such as synchronization control needs to be performed. Therefore, this processing time should be shortened. As a result, an improvement in the overall processing speed can be expected. FIG. 7 shows the operation timing. As compared with FIG. 3, the prediction data buffer circuit 12
The writing time to the internal buffer memory, that is, the reading time of the reference image data from the frame memory is shortened. FIG. 8 shows that in the configuration of the second embodiment shown in FIG. 4, the data bus width between the frame memories 20 to 22 and the memory access control circuit 19 and between the memory access control circuit 19 and the buffer circuit 12 is doubled. This is an example of the case. The operation timing at this time is as shown in FIG. 9, and in this case as well, as in the case of FIG. 6, the read time of the reference image data from the frame memory is shortened,
It can be expected to improve the overall processing speed.

FIG. 10 shows an embodiment of a motion compensation circuit in which a circuit for displaying an image created by motion compensation is added. In the figure, symbols 11 to 13 and 18 to 22 are respectively
It is attached according to FIG. Reference numeral 15 denotes a display control circuit. The difference image data input from the input terminal 11 is written in the buffer circuit 12. This buffer circuit has two sets of buffer memories for one macroblock as shown in FIG. 2, and it is possible to write to one buffer memory and read from the other simultaneously, and write and read buffers for each macroblock. Switch memory and use. Therefore, the difference image data of the previous macroblock is sent from the buffer circuit 12 to the addition circuit 13.

Since prediction by motion compensation is not performed in I-Picture, the output of the predicted image data calculation circuit 17 is set to 0 so that the difference image data becomes the output of the addition circuit. In P-Picture and B-Picture that perform prediction, first, the address of the frame memory to be read by the memory access control circuit 41 is calculated according to the input motion vector 18. Next, necessary reference image data is read from the frame memories 20 to 22, the predicted image data calculation circuit 17 calculates the predicted image data, and the predicted image data is written in the buffer circuit 12. The buffer circuit 12 also has the same configuration as the buffer circuit for the difference image data, and the predicted image data of the previous macroblock is output to the addition circuit 13 simultaneously with the writing. The adder circuit 13 adds the difference image data and the predicted image data and outputs the result. Adder circuit 1
The image data created in 3 is written in an appropriate frame memory of the frame memories 20 to 22 through the memory access control circuit 41.

Further, the image data in any of the frame memories 20 to 22 is read by the memory access control circuit 41 in the image display order and sent to the display control circuit 15. The display control circuit 15 converts the image data into an output format and outputs the display image data. When the display control circuit 15 is provided as described above, the reference image and the display image for calculating the predicted image data may need to be read from the same frame memory. As shown in FIG. 10, between the frame memories 20 to 22 and the memory access control circuit 41, the memory access control circuit 41 and the predicted image data calculation circuit 1
During 7, the predicted image data calculation circuit 17 and the buffer circuit 1
During 2, the memory access control circuit 41 and the display control circuit 1
By doubling the data bus width between 5 and the configuration of the buffer circuit 12 in the figure, even in such a case, motion compensation and display can be performed without reducing the processing speed.

FIG. 11 shows the operation timing at this time. The buffer memory in the differential image data buffer circuit 12 and the predictive image data buffer circuit 12 is switched between reading and writing in macro block units as shown in the figure. At the time of reading, both are added and output by the adding circuit 13. The output image data of the adder circuit 13 is written in an appropriate frame memory through the memory access control circuit 41. As can be seen from this figure, the output data from the adder circuit is continuously obtained, and the motion compensation processing can be performed at a higher speed than in FIG. At this time, by partially doubling the bus width as shown in FIG. 10, the write time to the predicted image data buffer memory becomes 1/2. That is, the access time of the frame memory for creating the predicted image data becomes 1/2.
By setting the remaining 1/2 time as the readout time of the display image, it is possible to perform motion compensation and display without reducing the processing speed.

FIG. 12 shows another embodiment of the motion compensation circuit in which a circuit for displaying an image created by motion compensation is added. The difference image data input from the input terminal 11 is
As in the case of FIG. 10, written in the buffer circuit 12,
The difference image data of the previous macroblock is sent to the addition circuit 13. In the case of I-Picture, the output of the prediction data calculation circuit 17 is set to 0, as in FIG. In P-Picture and B-Picture that perform prediction, first, the address of the frame memory to be read by the memory access control circuit 41 is calculated according to the input motion vector 18, and the required reference image from the frame memories 20 to 22 is calculated. The data is read and written in the buffer circuit 12. The buffer circuit 12 also has the same configuration as the buffer circuit for the difference image data, and the reference image data of the previous macroblock is sent to the predicted image data calculation circuit 17.

The predicted image data calculation circuit 17 calculates and outputs predicted image data from the reference image data read from the buffer circuit 12. The operation of the adder circuit 13 is the same as in FIG. 10, and the difference image data and the predicted image data are added and output. The image data created by the adder circuit 13 is written in an appropriate frame memory of the frame memories 20 to 22 through the memory access control circuit 41.
Further, the image data in any of the frame memories 20 to 22 is read out in the image display order by the memory access control circuit 41 and sent to the display control circuit 15. The display control circuit 15 converts the image data into an output format and outputs the display image data. In this configuration, the capacity of the buffer circuit is as shown in FIG.
However, it is not necessary to synchronize the reading of the two reference images used to create the predicted image data on a pixel-by-pixel basis, but the access control of the frame memory becomes easier.

Further, as shown in FIG. 12, by doubling the data bus width between the frame memories 20 to 22 and the memory access control circuit 41 and between the memory access control circuit 41 and the buffer circuit 12, display is performed. Even if the image and the reference image must be read from the same frame memory, motion compensation and display can be performed without reducing the processing speed. The operation timing at this time is shown in FIG. The differential image data buffer circuit 12 and the buffer memories in the two sets of reference image data buffer circuits 12 are switched between reading and writing in macroblock processing units as shown in the figure. The reference image data read from the reference image data buffer circuit 12 is operated by the predicted image data calculation circuit 17 to obtain the predicted image data calculation circuit output. This result is further added to the difference image data by the addition circuit 13 and output.

The output image data of the adder circuit 13 is written in an appropriate frame memory through the memory access control circuit 41. At this time, by partially doubling the bus width as shown in FIG. 12, the write time to the reference image data buffer memory, that is, the frame memory access time becomes 1/2. By setting the remaining 1/2 time as the readout time of the display image, it is possible to perform motion compensation and display without reducing the processing speed. In the above description, the description has been made assuming that the number of frame memories is three. However, even when the number of frame memories is four or more, the process can be performed in exactly the same manner by appropriately selecting the frame memories in the memory access control circuit. It is possible to increase the speed.

It is needless to say that the above embodiment shows an example of the present invention, and the present invention should not be limited to this.

[0026]

As described above in detail, according to the present invention, a remarkable effect that a motion compensation circuit capable of performing processing at a higher speed can be realized can be achieved.

[Brief description of drawings]

FIG. 1 is a first embodiment of a motion compensation circuit according to the present invention.

FIG. 2 is a configuration example of a buffer circuit according to an embodiment.

FIG. 3 is a diagram showing operation timing in the configuration shown in FIG.

FIG. 4 is a second embodiment of the motion compensation circuit according to the present invention.

5 is a diagram showing operation timing in the configuration shown in FIG.

FIG. 6 is a third embodiment of the motion compensation circuit according to the present invention.

7 is a diagram showing operation timing in the configuration shown in FIG.

FIG. 8 is a fourth example of the motion compensation circuit according to the present invention.

9 is a diagram showing operation timing in the configuration shown in FIG.

FIG. 10 is a fifth example of the motion compensation circuit according to the present invention.

11 is a diagram showing operation timing in the configuration shown in FIG.

FIG. 12 is a sixth embodiment of the motion compensation circuit according to the present invention.

13 is a diagram showing operation timing in the configuration shown in FIG.

FIG. 14 is an example of a conventional motion compensation circuit.

15 is a diagram showing operation timing in the configuration shown in FIG.

[Explanation of symbols]

 12 buffer circuit 13 adder circuit 15 display control circuit 17 predicted image data creation circuit 19,41 memory access control circuit 20, 21, 22 frame memory 31 buffer memory

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koji Kudo 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division

Claims (5)

[Claims] 1. An image data obtained by reading a corresponding portion of a reference image from a frame memory according to an input motion vector to create prediction data and adding the prediction data to the input difference image data as a new reference image. In the motion compensation circuit that writes to the frame memory, has multiple buffer memories to write the difference image data,
The buffer memory for writing the input data is switched each time a certain amount of pixels is processed, and at the same time, the buffer circuit for the differential image data that reads the image data from the buffer memory that is not writing and the buffer memory for writing the prediction data are set. A motion compensation circuit having a plurality of prediction data buffer circuits, each having a plurality of buffer memories for writing and reading each time a predetermined amount of pixels are processed as in the case of differential image data. 2. The width of a data bus from the reference image frame memory to the prediction data buffer circuit is made larger than the data width of one pixel so that prediction data of two or more pixels can be created for each access. The motion compensation circuit according to claim 1, wherein 3. An image data obtained by reading a corresponding portion of a reference image from a frame memory in accordance with an input motion vector to create prediction data and adding it to the input difference image data as a new reference image. In the motion compensation circuit that writes to the frame memory, has multiple buffer memories to write the difference image data,
A buffer circuit for differential image data that switches the buffer memory that writes input data each time a certain amount of pixels is processed, and at the same time, reads the image data from the buffer memory that is not writing, and used to create prediction data. A motion characterized by having a plurality of buffer memories for writing images and having a reference image data buffer circuit that switches between writing and reading buffer memories every time a certain amount of pixels are processed, as with differential image data. Compensation circuit. 4. The width of the data bus from the reference image frame memory to the reference image data buffer circuit is made larger than the data width of one pixel so that reference data of two or more pixels can be read out for each access. The motion compensation circuit according to claim 3, wherein 5. A circuit for outputting image data in a frame memory according to a display speed is provided, and a corresponding portion of a reference image is read out from the frame memory according to an input motion vector to create prediction data, In the motion compensation circuit that writes the image data obtained by adding to the input difference image data to the frame memory as a new reference image, read for creating prediction data and read for displaying reproduced image A motion compensation circuit characterized by reading image data at high speed by controlling so that the periods do not overlap.