KR0125290B1 - Device and method for controlling digital convergence - Google Patents

Abstract

The present invention relates to a digital convergence correcting system and a method thereof which facilitates correction of a deflecting signal by preventing a screen from flashing and oscillating when changing the deflecting signal applied to a deflection yoke. This digital convergence correcting system includes a pattern generating part producing standard video data for screen control to a video processor of a TV set; a switch switching standard video data transferred to the video processor from the pattern generating part; an erasable memory storing deflecting wave form data for deflection control; an address generating part generating a sequential address signal required for the pattern generating part and the memory; a D-A converter converting the deflecting wave form data into an analog signal; a keyboard into which wave form correcting data is input; and a CPU controlling the memory and the switch.

Description

Digital convergence adjusting device and method

The present invention relates to a digital convergence adjusting device and method for adjusting a deflection signal to be supplied to a deflection yoke of a receiver, and in particular, prevents flickering and shaking of a screen when changing a shape of a deflection signal. An apparatus and method for digital convergence adjustment can be easily and quickly adjusted.

Conventional convergence adjusting devices appropriately adjust the waveform of the deflection signal supplied to the horizontal and vertical deflection yokes of the electron beam in order to display the image on the screen without distortion in the manufacture of the receiver.

The convergence adjusting device as described above will be described in detail with reference to FIG. 1.

1 is a block diagram of a conventional digital convergence adjustment device.

As shown in Fig. 1, a conventional convergence adjusting device having an address generator 10 for introducing a vertical retrace pulse and a horizontal retrace pulse via the first and second input lines 11 and 13 is shown. The address generator 10 generates a sequential address that is initialized each time the vertical retrace pulse is input and then increments by one each time the horizontal retrace pulse is applied to the pattern generator 12 and the first address. It supplies to the 1st selection contact SP1 of the control switch 18. The pattern generator 12 is a ROM having image data for a screen adjustment standard image signal. The pattern generator 12 reads standard image data stored in itself according to a sequential address from the address generator 10 and reads the standard image data read. Output to the image processor (not shown) via the clamping circuit (14). The first control switch 18 selects its second from the sequential address and central processing unit (hereinafter referred to as CPU) 30 supplied from the address generator 10 to its first selection contact SP1. The random address supplied to the contact point SP2 is selected to supply the selected address to the address port of the memory 16 via its reference contact point. The memory 16 is a random access memory (RAM) that performs write and read operations under the control of the CPU 30, and stores waveform data relating to a deflection signal in itself. During the write operation, the memory 16 stores its data via the second control switch 20 in a storage area corresponding to a random address supplied to its own address port via the first control switch 18. The correction data from the CPU 30 supplied to the port is stored. On the contrary, in the read operation, the memory 16 sequentially reads deflection waveform data stored at sequential addresses from the address generator 10 supplied to its address port via the first control switch 18 and is read. The deflection waveform data is supplied to the digital-analog (hereinafter referred to as 'D-A') converter 22 via the reference contact RP and the first selection contact SP1 of the second control switch 20. The DA converter 22 converts a deflection waveform signal having a form of a digital signal from the memory 16 introduced through the second control switch 20 into a form of an analog signal to low-pass the converted deflection signal. It is supplied to the pass filter 24. The low pass filter 24 generates a deflection signal having a smooth change by removing a noise signal of an impulse component included in the deflection signal from the DA converter 22 and converts the deflection signal having a smooth change into an amplifier. 26). The amplifier 26 amplifies the deflection signal from the low pass filter 24 to have a predetermined magnitude and applies the amplified deflection signal to a deflection yoke (not shown).

In addition, the conventional convergence adjusting device further includes a keyboard 28 for inputting a user-specified command and waveform correction data for a deflection signal to be input.

The keyboard 28 supplies the control command and waveform correction data introduced from the user to the CPU 30. The CPU 30 contacts the first and second control switches 18 and 20 to update the deflection waveform data stored in the memory 16 whenever waveform correction data is input from the keyboard 28. Control the first and second control switches 18 and 20 such that the first and second selection contacts are connected to a second selection contact point, a random address is applied to the second selection contact point SP2 of the first control switch 18, and the second The waveform correction data from the keyboard 28 is supplied to the second selection contact SP2 of the control switch 20, and a write enable signal is applied to the memory 16. The CPU 30 generates a pattern output blocking signal having a predetermined logic state and applies the clamping circuit 14 to the clamping circuit 14 via the delay circuit 32 to cause the clamping circuit 14 to be transmitted to the image processor. Block video data. The delay circuit 32 is supplied to the deflection yoke via the amount of standard image data transmitted via the clamping circuit 14 and the DA converter 22, the low pass filter 24, and the amplifier 26. The pattern output blocking signal to be transmitted from the CPU 30 to the clamping circuit 14 is delayed for a predetermined time to match the amount of deflection waveform data and the time to reach the electron gun and deflection yoke of the cathode ray tube (not shown).

As described above, the conventional convergence adjusting device is configured to update the deflection waveform data stored in the memory whenever the waveform correction data input by the user is input, regardless of the output state of the standard pattern image signal and the deflection waveform signal. Because of this, the standard image displayed on the screen of the receiver flickers or vibrates severely. In addition, due to the flickering and shaking of the standard image, the conventional convergence adjusting device makes it difficult for the user to adjust the convergence and takes a lot of adjustment time.

However, the conventional convergence adjusting device stops outputting the adjustment screen pattern and the deflection signal and updates the waveform of the deflection signal whenever the user, that is, the maker of the receiver inputs correction data for correcting the waveform of the deflection signal. There was a problem of flickering and blurring of the screen.

Therefore, due to the above problems, the conventional convergence adjustment device has a big problem that the user can not easily adjust the convergence of the receiver, and takes a lot of adjustment time.

Accordingly, an object of the present invention is to prevent the flickering and shaking of the screen when changing the shape of the deflection signal to be applied to the deflection yoke of the receiver, thereby allowing the user to easily and quickly adjust the deflection signal. An apparatus and method are provided.

1 is a block diagram of a conventional digital convergence adjustment device.

2 is a block diagram of a digital convergence adjustment apparatus according to an embodiment of the present invention.

3 is a flowchart of a digital convergence adjustment method according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10,40: address generator 11,41: first input line

12,42: pattern generator 13,43: second input line

14 clamping circuit 15,45 first output line

17,47: second output line 16,46: memory

18,48: first control switch 20,50: second control switch

22,52: digital-to-analog converter 24,54: low pass filter

26,56: amplifier 28,58: keyboard

30,60: central processing unit (CPU) 32,44: delay circuit

In order to achieve the above object, the digital convergence adjustment device of the present invention is a digital-to-analog converter for inputting a digital signal and converts it into an analog signal and outputs an impulse component included in the output signal from the digital-analog converter. A digital convergence adjusting device comprising: a low pass filter for removing a noise signal and outputting the signal; and a signal amplifier for amplifying the output signal from the low pass filter so as to have a predetermined size. And an address generating means for generating a sequential address that is initialized each time the vertical retrace pulse is input and then increments by one each time a horizontal retrace pulse is applied, and stored in itself by a sequential address from the address generating means. Pattern for reading and outputting standard image data A signal delay means for delaying a predetermined time from the pattern generating means to the image processing unit, and for storing a deflection waveform data for deflection control, a user-specified command and a deflection signal to be input. An input means for inputting waveform correction data, the waveform correction data input from the input means, and updating the deflection waveform data stored in the memory with the input waveform correction data at the time when the vertical retrace pulse is input, A control signal generating means for generating a control signal and a random address for outputting the deflection waveform data stored in the memory and the standard image data stored in the pattern generating means in a period where the vertical retrace pulse is not introduced, and the control signal generation Output of the means First switching means for selecting a sequential address supplied from said address generating means and a random address supplied from said control signal generating means by a call, and transmitting it to said memory, and said memory by an output signal of said control signal generating means; And second switching means for selecting whether to output the deflection waveform data supplied from the digital-to-analog converter or to input the deflection waveform correction data supplied from the control signal generating means into a memory. do.

In order to achieve the above object, the digital convergence adjustment method of the present invention provides a first step of inputting waveform correction data for correcting deflection waveform data for deflection control and a vertical retrace period when the data in the first step is input. In the case of non-retrace period, the second process returns temporarily to the first process after temporarily storing the waveform correction data, and replaces the waveform data with the correction data in the case of the vertical retrace period in the second process. And a third process of updating data.

Hereinafter, with reference to Figures 2 and 3 attached to an embodiment of the present invention will be described in detail.

2 is a block diagram of an apparatus for adjusting digital convergence according to an embodiment of the present invention, and FIG. 3 is a flowchart of a method for adjusting digital convergence according to an embodiment of the present invention.

As shown in FIG. 2, the digital convergence according to the embodiment of the present invention includes an address generator 40 for introducing a horizontal retrace pulse and a vertical retrace pulse via the first and second input lines 41 and 43. The adjusting device is shown. The address generator 40 generates a sequential address that is initialized each time the vertical retrace pulse is input and then increments by one each time the horizontal retrace pulse is applied to the pattern generator 12 and the first address. It supplies to the 1st selection contact SP1 of the control switch 48. The pattern generator 42 is a ROM having image data for a standard image signal for screen adjustment. The pattern generator 42 reads standard image data stored in itself according to a sequential address from the address generator 40 to read the standard image data. The output is sent to an image processor (not shown) via the delay circuit 44. The first control switch 48 is a sequential address supplied from the address generator 40 to its first selection contact SP1 and a random address supplied from the CPU 60 to its second selection contact SP2. Is selected to supply the selected address to the address port of the memory 46 via its reference contact RP. The memory 46 is a random access memory that performs write and read operations under the control of the CPU 60, and stores waveform data relating to a deflection signal in itself. During the write operation, the memory 46 stores its data via the second control switch 50 in a storage area corresponding to a random address supplied to its own address port via the first control switch 48. The degree of supply to the port stores waveform correction data from the CPU 60. On the contrary, in the read operation, the memory 46 sequentially reads deflection waveform data stored at sequential addresses from the address generator 40 supplied to its address port via the first control switch 48 and is read. The deflection waveform data is supplied to the DA converter 52 via the reference contact RP and the first selection contact SP1 of the second control switch 50. The DA converter 52 converts a deflection waveform signal having a form of a digital signal from the memory 46 introduced through the second control switch 50 into a form of an analog signal to low-pass the converted deflection signal. Supply to the pass filter 54. The low pass filter 54 generates a deflection signal having a smooth change by removing a noise signal of an impulse component included in the deflection signal from the DA converter 52 and converts the deflection signal having a smooth change into an amplifier ( 56). The amplifier 56 amplifies the deflection signal from the low pass filter 54 to have a predetermined magnitude and applies the amplified deflection signal to a deflection yoke (not shown).

In addition, the digital convergence adjusting device according to the embodiment of the present invention further includes a keyboard 58 for inputting a user-specified command and waveform correction data for a deflection signal to be input. The keyboard 58 supplies the control command and waveform correction data introduced from the user to the CPU 60. The CPU 60 inputs waveform correction data input by the user from the keyboard 58 and corrects the waveform input in a period (vertical return period) during which a vertical retrace pulse is input via the second input line 43. The deflection waveform data stored in the memory 46 is updated with data, and the deflection stored in the memory 46 in a period where the vertical retrace pulse is not introduced via the second input line 43 (vertical scanning period). The CPU 60 controls the delay circuit 44, the memory 46, and the first and second control switches 48 and 50 so that the waveform data and the standard image data stored in the pattern generator 42 are output. First, when the deflection waveform data stored in the memory 46 is updated (while a vertical retrace pulse is introduced via the second input line 43), the CPU 60 switches the first and second control switches. The first and second control switches 48 and 50 are controlled such that the reference contacts of 48 and 50 are connected to the second selection contact SP2, and the second selection contact of the first control switch 48 is controlled. SP2) supplies a random address, and supplies waveform correction data from the keyboard 58 to the second selection contact SP2 of the second control switch 50, respectively, and writes a write enable signal to the memory 46. Apply. The CPU 60 generates a pattern output blocking signal having a predetermined logic state and applies the delay signal to the delay circuit 44 so that the delay circuit 44 is transmitted from the pattern generator 42 to the image processor. Block data. On the contrary, when the standard image data and the deflection waveform data are to be output (period during which no vertical retrace pulse is applied via the second input line 43), the CPU 60 switches the first and second control switches ( The first and second control switches 48 and 50 are controlled such that the reference contacts 48 and 50 are connected to the first selection contact SP1, and a read enable signal is applied to the memory 46. The CPU 60 generates a pattern output blocking signal in a basic logic state and applies it to the delay circuit 44 so that the delay circuit 44 is transmitted from the pattern generator 42 to the image processor. Try to delay the data for a certain period of time. The delay circuit 44 may generate the pattern generator 42 for a period in which deflection waveform data output from the memory 46 is delayed by the DA converter 22, the low pass filter 24, and the amplifier 26. Delay the standard image data sent from the image processing unit to the image processing unit.

3 is a flow chart of a digital convergence adjustment method according to an embodiment of the present invention performed by the CPU 60 shown in FIG. The flow chart will be described in detail with reference to the block diagram shown in FIG. 2.

In step 62, the CPU 60 inputs waveform correction data input by the user via the keyboard 58. After performing step 62, the CPU 60 determines whether the current vertical return period is present by checking whether a vertical return pulse of a predetermined logic is input via the second input line 43 (step 64). When the vertical retrace pulse is not input via the second input line 43 in step 64, that is, when the vertical retrace period is not, the CPU 60 may apply waveform correction data input through the keyboard 58. After storing in the working memory built in the memory, the process returns to the step 62 (step 66). In this case, the reference contact RP of the first and second control switches 48 and 50 is connected to the first selection contact SP1 under the control of the CPU 60, and the memory 46 is connected to the CPU 60. The deflection waveform data stored therein is sequentially read by the read enable signal from < RTI ID = 0.0 >) < / RTI > through the reference contact RP and the first selection contact SP1 of the second control switch 50. Transfer to DA converter 52. The delay circuit 44 delays the standard image data to be transmitted from the pattern generator 42 to the image processor for a predetermined time by the pattern output cutoff signal of the base logic state from the CPU 60.

On the contrary, when the vertical retrace pulse of a predetermined logic state is input via the second input line 43 in the 64th step, that is, during the vertical retrace period, the CPU 60 deflects stored in the memory 46. Part of the waveform data is updated with waveform correction data input by the user (step 68). In order to update a part of the deflection waveform data stored in the memory 46, the CPU 60 may include the reference contacts RP of the first and second control switches 48 and 50. Control the first and second control switches 48 and 50 so as to be connected to the first and second switches; and a random address at the second selection contact SP2 of the first control switch 48, and the second control switch 50. The waveform correction data from the keyboard 58 and the waveform correction data temporarily stored in the working memory therein are supplied to the second selection contact SP2 of the keyboard 58, and a write enable signal is applied to the memory 46. In addition, the CPU 60 generates a pattern output blocking signal in a predetermined logic state and applies it to the delay circuit 44 to cause the delay circuit 44 to be transmitted from the pattern generator 42 to the image processor. Block video data.

As described above, the apparatus and method for adjusting digital convergence of the present invention records the waveform correction data input by the user in a memory in which the deflection waveform data is stored only in the vertical retrace period during which the standard video signal is not output. It provides an advantage that can prevent flickering and shaking of image. Due to the above advantages, the digital convergence adjustment apparatus and method of the present invention has an excellent effect of allowing a user to easily adjust the convergence and minimize the time required for the convergence adjustment.

Claims (3)

A digital-to-analog converter for inputting a digital signal and converting the analog signal into an analog signal; a low-pass filter unit for removing and outputting a noise signal of an impulse component included in the output signal from the digital-analog converter; A digital convergence adjusting device having a signal amplifying unit for amplifying an output signal from a pass filter so as to have a predetermined size, comprising: a horizontal retrace pulse and a vertical retrace pulse inputted, and each time the vertical retrace pulse is inputted and then horizontally Address generating means for generating a sequential address that is incremented by one each time the retrace pulse is applied, pattern generating means for reading and outputting standard image data stored therein by the sequential address from the address generating means, and The standard image data from the pattern generating means is fixed. Signal delay means for delaying the signal to be transmitted to the image processing unit, a memory for storing deflection waveform data for deflection control, input means for inputting a user-specified command and waveform correction data for a deflection signal to be input, and the input means. Accepts waveform correction data inputted from the controller, updates the deflection waveform data stored in the memory with the input waveform correction data in a period during which the vertical retrace pulse is input, and stores in the memory in a period where the vertical retrace pulse does not flow. Control signal generating means for generating a deflection waveform data and standard image data stored in the pattern generating means and a control signal generating means for generating a random address, and sequentially supplied from the address generating means by an output signal of the control signal generating means; Address And first switching means for selecting and transmitting a random address supplied from the control signal generating means to the memory, and converting the deflection waveform data supplied from the memory by the output signal of the control signal generating means into the digital-analog conversion. And second switching means for selecting whether to output to the memory or to input the deflection waveform correction data supplied from the control signal generating means into a memory. The digital convergence adjustment device according to claim 1, wherein said pattern generating means is a ROM having image data for a standard image signal for screen adjustment. A digital convergence adjustment method, comprising: a first step of inputting waveform correction data for correcting deflection waveform data for deflection control; and determining whether or not it is a vertical return period when data in the first step is input, and not in the return period. A second process of returning to the first process again after temporarily storing the waveform correction data, and a third process of updating the deflection waveform data by replacing the waveform data with the waveform correction data in the vertical retrace period in the second process Digital convergence adjustment method comprising the.