KR970007801B1 - Digital convergence data sending system - Google Patents

Abstract

A digital convergence data transmission system having a CPU, memory and address generator includes a control point generation data latch for controlling a control point generator, data latches for controlling horizontal and vertical phases, which controls the horizontal and vertical phase controllers, a pattern selection data latch for controlling a pattern selector, and an address decoder for controlling the latches, the address decoder including an AND gate 114A for ANDing the output addresses of the address generator, an AND gate 114B for ANDing the output signal of the AND gate 114A and vertical blanking signal, and a decoder 114C for decoding the output addresses of the address generator, employing the output signal of the AND gate 114B as the chip enable signal.

Description

Digital convergence data transmission system

1 is a general digital convergence correction block diagram.

2 is a block diagram of a digital convergence data transmission of the present invention.

3 is a diagram illustrating a mapping of a memory to which the present invention is applied.

4 is a waveform diagram of a vertical blanking signal.

5 is an exemplary circuit diagram of an address decoder in FIG.

6 is a waveform diagram of each part (a) to (g).

* Explanation of symbols for main parts of the drawings

101: PL 102: adjustment pattern generator

103: control point generator 104: horizontal, vertical phase controller

105: address generator 106: central processing unit

107: memory 108: digital to analog converter

109: low pass filter 110: clamp

111 amplifier 112 adder

113: pattern selector 114: address generator

115: Adjustment point data latch 116: Horizontal, vertical phase adjustment data latch

117: Pattern selection data latch

The present invention relates to a technique for adjusting digital convergence, and in particular, when the central processing unit receives an external key input and controls the system to adjust the convergence, it is suitable for transmitting the system control data of the central processing unit to the system more easily. The present invention relates to a digital convergence data transmission system.

FIG. 1 is a general digital convergence correction block diagram. As shown in FIG. 1, a clock signal synchronized with horizontal and vertical blanking signals H _BLK and V _BLK is generated and adjusted to the adjustment pattern generator 2 and the adjustment point generator. (3), the PEL (1) for supplying the horizontal and vertical phase regulator (4) and the address generator (5), the adjustment pattern generator (2) for generating the adjustment pattern, and the output from the central processing unit (6) The control point generator 3 adjusts the position of the control point on the screen using data, and the clock signal output from the PEL 1 and the output data of the central processing unit 6 are used. Horizontal and vertical phase controllers (4) to determine the reset time, set the horizontal and vertical position on the screen, and compensate for the delay time of the entire system generated by digital convergence, and the output signal of the PEL (1) and horizontal , Output signal of vertical phase controller (4) An address generator 5 for generating an address of the memory 7 by using a controller and a central processing unit 6 for receiving an external key signal input through a remote controller or a keyboard to manipulate convergence correction data of the memory 7. And a memory 7 for storing the output data of the CPU 6 and outputting the stored data according to the output address of the address generator 5, and the output data of the memory 7 as analog. A digital-to-analog converter 8 for converting a signal roll, a low-pass filter 9 for converting the output waveform of the digital-analog converter 8 into a gentle waveform, and a vertical position of the scan line at the time of vertical retrace In order to eliminate the effects of the low-pass filter (9) during the vertical blanking period clamp 10 and the output signal of the clamp 10 amplified to a suitable level by deflecting the nose An amplifier 11 flowing into the CY, an adder 12 for synthesizing the output component of the adjustment pattern generator 2 and the output component of the adjustment point generator 102, and the control of the central processing unit 6; It is composed of a pattern selector 13 for receiving a pattern to be output from the adder 12, the operation of the conventional system configured as described above is as follows.

When the operator inputs an adjustment key signal by using a remote controller or a keyboard to move the convergence adjustment point, the central processing unit 6 determines the key signal, and transmits the data different from the current convergence data to the adjustment point generator 3 side. The control point generator 3 adjusts the adjustment point to a position designated by the input data.

At this time, the horizontal and vertical phase adjuster 4 also adjusts the phase in the same manner as above, wherein the pattern selection refers to selecting all or one or two of red, blue, and green on the screen or selecting a dot pattern. .

However, in such a conventional convergence adjustment system, the central processing unit reads the key value input by the operator and executes the corresponding loop to output the random data accordingly. Since the correction data of the memory has to be manipulated, the configuration of the program and the system becomes complicated, and thus, a large number of data input ports are required when gate arraying each block.

In order to solve this problem, the present invention is designed to store only the address of a memory in which control data is stored and to adjust the convergence only by adjusting the data of the address, which will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a digital convergence data transmission system of the present invention. As shown in FIG. 2, an adjustment pattern generator 102 generates phase-locked clock signals to horizontal and vertical blanking signals H _BLK and V _BLK . ), The control point generator 103, the horizontal and vertical phase controller 104 and the PEL 101 to be supplied to the address generator 105, the adjustment pattern generator 102 to generate the adjustment pattern, and the PEL 101 The control point generator 103 for adjusting the position of the adjustment point of the screen using the output of the control point and the control point control data output from the control point generation data latch 115, the clock signal output from the Pl 101 and By using the output data of the horizontal and vertical phase adjustment data latch 116, the reset time of the address generator 105 is determined to set the horizontal and vertical positions on the screen, and compensates for the delay time of the entire system generated by digital convergence. An address generator 105 for generating an address of the memory 107 using a horizontal and vertical phase controller 104 and an output signal of the PLL 101 and an output signal of the horizontal and vertical phase controller 104. The central processing unit 106 changes the address of the memory 107 in which the system control data is stored according to the external key signal input through the remote controller or the keyboard, and the convergence correction data according to the address output from the address generator 105. And output convergence correction data according to the address output from the central processing unit 106, and in the vertical blanking (V _BLK ) section according to the address output from the central processing unit 106. A memory 107 for outputting control data, a digital to analog converter 108 for converting the output data of the memory 107 into an analog signal, and The low pass filter 109 converts the output waveform of the digital / analog converter 108 into a smooth waveform, and the output of the low pass filter 109 in order to eliminate the influence of the vertical position of the scanning line during the vertical retrace. During the vertical blanking period, the clamp 10 which makes the DC zero, the amplifier 111 which amplifies the output signal of the clamp 10 to an appropriate level and flows the deflection coil Y ', and the vertical blanking signal V _BLK ) and the output address of the address generator 105 are supplied to the control point generation data latch 115, the horizontal and vertical phase adjustment data latch 116, and the pattern selection data latch 117 to provide clock signals at different timings. An address decoder 114 for supplying, an adjustment point generation data latch 115 for latching adjustment point generation data output from the memory 107 and transferring it to the adjustment point generator 103, and the memory 107. Output from Latches the horizontal and vertical phase adjustment data latches 116 for latching the horizontal and vertical phase adjustment data and transmits them to the horizontal and vertical phase adjusters 104, and latches the pattern selection data output from the memory 107 to perform the latching. A pattern selection data latch 117 to be transmitted to the pattern selector 113, an adder 112 for synthesizing the output component of the adjustment pattern generator 102 and the output component of the adjustment point generator 103, and the pattern selection data. The pattern selector 113 selects a pattern output from the adder 112 under the control of the latch 117.

FIG. 5 is an exemplary detailed circuit diagram of the address decoder 114 in FIG. ₂ and an AND gate 114A for AND combining the output addresses a _{2-a n} of the address generator 105 as shown therein. And the address generator using an AND gate 114B for AND combining the output signal of the AND gate 114A and the vertical blanking signal V _BLK , and the output signal of the AND gate 114B as a chip enable signal CE. A decoder 114C that decodes the output addresses a ₀ and a ₁ of 105 is described in detail with reference to FIGS. 4 to 6 attached to the operation and effect of the present invention configured as described above. Is as follows.

The address decoder 114 uses the output of the address generator 105 and the vertical blanking signal V _BLK to adjust the control point generation data latch 115, the horizontal and vertical phase adjustment data latch 116, and the pattern selection data latch 117. In the pulse supply, the control point generation data latch 115, the horizontal and vertical phase adjustment data latch 116, and the pattern selection data latch 116 are supplied at different timings. ) Latches the output data of the memory 107, and the latched data is supplied to the adjustment point generator 103, the horizontal and vertical phase controllers 104, and the pattern selector 113 to adjust the convergence of the screen. .

For example, when the operator inputs a predetermined adjustment key signal to move the convergence adjustment point, the central processing unit 106 scans the key signal to change the address of the memory 107 in which the adjustment point generation data is stored. Accordingly, data output from another address of the memory 107 is input to the adjustment point generator 103 by the address decoder 114 and the adjustment point generation data latch 115, and the adjustment point data generated therefrom is changed. .

In addition, the data output from the horizontal and vertical phase adjuster 104 and the pattern selector 113 may also pass through the respective paths as described above, that is, the memory 107 → the horizontal and vertical phase adjust data latches 116 and the memory ( 107) → pattern selection data latch 117 is adjusted respectively.

However, the adjustment point generation data, phase adjustment data, and pattern selection data should not be output through the digital / analog converter 108 because they are independent of the convergence correction data.

However, if this data is moved during the vertical blanking (V _BLK ) period, most digital convergence systems use the clamp 110 to control the system during the vertical blanking (V _BLK ) period. Since the system clamps the signal, even if this system control signal is output through the digital-to-analog converter 108, it does not affect the screen. In addition, it can be seen that the vertical blanking period V _BLK gives sufficient data movement time as shown in FIG. 4.

5 and 6 show an embodiment of the address decoder 114 and its output waveform, respectively, in which the system control data is 4 bytes and this data is the lowest address of the memory 107, that is, FFFC _H ? The case where the data is stored up to FFF _H is taken as an example. The output addresses a _{2-a n} of the address generator 105 are supplied to the AND gate 114A, and then combined with each other. When the output signal and the vertical blanking signal V _BLK are AND-combined with (A) in FIG. 6 at the AND gate 114B, and the 2 to 4 decoders 114 are enabled by this signal, the decoder 114C is used. ) Decodes the output addresses (a ₀ ) and (a ₁ ) of the address generator 105 to generate clock signals as shown in (d) to (g) of FIG. 115, 116, and 117, respectively.

As described in detail above, in the present invention, the central processing unit stores only the address of the memory in which the system control data is stored, and the convergence is adjusted by only operating the data of the address so that the configuration of the program and the circuit of the central processing unit is improved. Not only is it easy to process, but it also has the effect of reducing many data ports when gate arraying the digital part.

Claims (2)

A system for transmitting digital convergence data, including a central processing unit, a memory, and an address generator, comprising: an adjustment point generation data latch for controlling an adjustment point generator, a horizontal and vertical phase adjustment data latch for controlling a horizontal and vertical phase adjuster; And a pattern selection data latch for controlling the pattern selector, and an address decoder for controlling the latches. The address decoder of claim 1, wherein the address decoder includes an AND gate 114A for AND-combining the output addresses a _{2-a n} of the address generator, an output signal of the AND gate 114A, and a vertical blanking signal V _BLK . A decoder 114C which decodes the output addresses a ₀ and a ₁ of the address generator using an AND gate 114B for AND combining and an output signal of the AND gate 114B as a chip enable signal CE. Digital convergence data transmission system characterized by the above-mentioned.