JPWO2024262220A1 - - Google Patents
Info
- Publication number
- JPWO2024262220A1 JPWO2024262220A1 JP2025527597A JP2025527597A JPWO2024262220A1 JP WO2024262220 A1 JPWO2024262220 A1 JP WO2024262220A1 JP 2025527597 A JP2025527597 A JP 2025527597A JP 2025527597 A JP2025527597 A JP 2025527597A JP WO2024262220 A1 JPWO2024262220 A1 JP WO2024262220A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W44/00—Electrical arrangements for controlling or matching impedance
- H10W44/501—Inductive arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/10—Configurations of laterally-adjacent chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
- H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023101092 | 2023-06-20 | ||
| PCT/JP2024/018676 WO2024262220A1 (ja) | 2023-06-20 | 2024-05-21 | 半導体モジュール |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPWO2024262220A1 true JPWO2024262220A1 (https=) | 2024-12-26 |
Family
ID=93935672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025527597A Pending JPWO2024262220A1 (https=) | 2023-06-20 | 2024-05-21 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20260101828A1 (https=) |
| JP (1) | JPWO2024262220A1 (https=) |
| WO (1) | WO2024262220A1 (https=) |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1989004113A1 (en) * | 1987-10-20 | 1989-05-05 | Irvine Sensors Corporation | High-density electronic modules, process and product |
| US5362986A (en) * | 1993-08-19 | 1994-11-08 | International Business Machines Corporation | Vertical chip mount memory package with packaging substrate and memory chip pairs |
| US5567654A (en) * | 1994-09-28 | 1996-10-22 | International Business Machines Corporation | Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging |
| US7562271B2 (en) * | 2005-09-26 | 2009-07-14 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
| JP5671200B2 (ja) * | 2008-06-03 | 2015-02-18 | 学校法人慶應義塾 | 電子回路 |
| US9305606B2 (en) * | 2009-08-17 | 2016-04-05 | Micron Technology, Inc. | High-speed wireless serial communication link for a stacked device configuration using near field coupling |
| JP5635759B2 (ja) * | 2009-10-15 | 2014-12-03 | 学校法人慶應義塾 | 積層半導体集積回路装置 |
| JP2011233842A (ja) * | 2010-04-30 | 2011-11-17 | Toshiba Corp | 不揮発性半導体記憶装置 |
| WO2013081633A1 (en) * | 2011-12-02 | 2013-06-06 | Intel Corporation | Stacked memory allowing variance in device interconnects |
| US9065722B2 (en) * | 2012-12-23 | 2015-06-23 | Advanced Micro Devices, Inc. | Die-stacked device with partitioned multi-hop network |
| CN113056819B (zh) * | 2019-11-11 | 2022-06-03 | 超极存储器股份有限公司 | 半导体模块、dimm模块以及它们的制造方法 |
| WO2024057707A1 (ja) * | 2022-09-12 | 2024-03-21 | 先端システム技術研究組合 | 半導体モジュール及びその製造方法 |
-
2024
- 2024-05-21 WO PCT/JP2024/018676 patent/WO2024262220A1/ja not_active Ceased
- 2024-05-21 JP JP2025527597A patent/JPWO2024262220A1/ja active Pending
-
2025
- 2025-12-02 US US19/405,996 patent/US20260101828A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024262220A1 (ja) | 2024-12-26 |
| US20260101828A1 (en) | 2026-04-09 |