JPWO2024043087A1 - - Google Patents

Info

Publication number
JPWO2024043087A1
JPWO2024043087A1 JP2024542741A JP2024542741A JPWO2024043087A1 JP WO2024043087 A1 JPWO2024043087 A1 JP WO2024043087A1 JP 2024542741 A JP2024542741 A JP 2024542741A JP 2024542741 A JP2024542741 A JP 2024542741A JP WO2024043087 A1 JPWO2024043087 A1 JP WO2024043087A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024542741A
Other languages
Japanese (ja)
Other versions
JPWO2024043087A5 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2024043087A1 publication Critical patent/JPWO2024043087A1/ja
Publication of JPWO2024043087A5 publication Critical patent/JPWO2024043087A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
JP2024542741A 2022-08-26 2023-08-08 Pending JPWO2024043087A1 (https=)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022135011 2022-08-26
PCT/JP2023/028998 WO2024043087A1 (ja) 2022-08-26 2023-08-08 ホスト装置、不揮発性記憶装置およびメモリシステム

Publications (2)

Publication Number Publication Date
JPWO2024043087A1 true JPWO2024043087A1 (https=) 2024-02-29
JPWO2024043087A5 JPWO2024043087A5 (https=) 2025-05-07

Family

ID=90013136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024542741A Pending JPWO2024043087A1 (https=) 2022-08-26 2023-08-08

Country Status (3)

Country Link
US (1) US20250190343A1 (https=)
JP (1) JPWO2024043087A1 (https=)
WO (1) WO2024043087A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12608312B2 (en) * 2024-03-13 2026-04-21 Genesys Logic, Inc. Data access control method of memory card and computer system

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016009280A (ja) * 2014-06-24 2016-01-18 キヤノン株式会社 記録装置
JP2019020989A (ja) * 2017-07-14 2019-02-07 キヤノン株式会社 記録装置
JP2019057229A (ja) * 2017-09-22 2019-04-11 パナソニックＩｐマネジメント株式会社 通信形式判定方法
US20210064551A1 (en) * 2019-09-03 2021-03-04 Realtek Semiconductor Corp. Method and control chip for performing access control of memory device
US20210382621A1 (en) * 2020-06-08 2021-12-09 Western Digital Technologies, Inc. Attribute Mapping in Multiprotocol Devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016009280A (ja) * 2014-06-24 2016-01-18 キヤノン株式会社 記録装置
JP2019020989A (ja) * 2017-07-14 2019-02-07 キヤノン株式会社 記録装置
JP2019057229A (ja) * 2017-09-22 2019-04-11 パナソニックＩｐマネジメント株式会社 通信形式判定方法
US20210064551A1 (en) * 2019-09-03 2021-03-04 Realtek Semiconductor Corp. Method and control chip for performing access control of memory device
US20210382621A1 (en) * 2020-06-08 2021-12-09 Western Digital Technologies, Inc. Attribute Mapping in Multiprotocol Devices

Also Published As

Publication number Publication date
WO2024043087A1 (ja) 2024-02-29
US20250190343A1 (en) 2025-06-12

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