JPWO2024024069A1 - - Google Patents

Info

Publication number
JPWO2024024069A1
JPWO2024024069A1 JP2024536717A JP2024536717A JPWO2024024069A1 JP WO2024024069 A1 JPWO2024024069 A1 JP WO2024024069A1 JP 2024536717 A JP2024536717 A JP 2024536717A JP 2024536717 A JP2024536717 A JP 2024536717A JP WO2024024069 A1 JPWO2024024069 A1 JP WO2024024069A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2024536717A
Other languages
Japanese (ja)
Other versions
JP7769804B2 (ja
JPWO2024024069A5 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2024024069A1 publication Critical patent/JPWO2024024069A1/ja
Publication of JPWO2024024069A5 publication Critical patent/JPWO2024024069A5/ja
Application granted granted Critical
Publication of JP7769804B2 publication Critical patent/JP7769804B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W78/00—Detachable holders for supporting packaged chips in operation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/20—Inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2024536717A 2022-07-29 2022-07-29 インターポーザおよびインターポーザの製造方法 Active JP7769804B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/029224 WO2024024069A1 (ja) 2022-07-29 2022-07-29 インターポーザおよびインターポーザの製造方法

Publications (3)

Publication Number Publication Date
JPWO2024024069A1 true JPWO2024024069A1 (https=) 2024-02-01
JPWO2024024069A5 JPWO2024024069A5 (https=) 2025-01-31
JP7769804B2 JP7769804B2 (ja) 2025-11-13

Family

ID=89705828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024536717A Active JP7769804B2 (ja) 2022-07-29 2022-07-29 インターポーザおよびインターポーザの製造方法

Country Status (3)

Country Link
US (1) US20250157905A1 (https=)
JP (1) JP7769804B2 (https=)
WO (1) WO2024024069A1 (https=)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011058945A1 (ja) * 2009-11-11 2011-05-19 株式会社村田製作所 積層セラミック電子部品
US20130285256A1 (en) * 2010-11-22 2013-10-31 Andreas Fischer Method and an apparatus for forming electrically conductive vias in a substrate, an automated robot-based manufacturing system, a component comprising a substrate with via holes, and an interposer device
JP2014143312A (ja) * 2013-01-24 2014-08-07 Napura:Kk 受動素子内蔵基板
JP2017157792A (ja) * 2016-03-04 2017-09-07 イビデン株式会社 電子部品内蔵基板及びその製造方法
WO2018139046A1 (ja) * 2017-01-27 2018-08-02 株式会社村田製作所 インターポーザ基板、回路モジュール、インターポーザ基板の製造方法
JP2021061264A (ja) * 2019-10-02 2021-04-15 味の素株式会社 インダクタ機能を有する配線基板及びその製造方法
JP2021061387A (ja) * 2019-10-08 2021-04-15 インテル コーポレイション 予め製造されたフェライトコアを有する同軸磁性インダクタ
JP2021086856A (ja) * 2019-11-25 2021-06-03 イビデン株式会社 インダクタ内蔵基板、インダクタ内蔵基板の製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011058945A1 (ja) * 2009-11-11 2011-05-19 株式会社村田製作所 積層セラミック電子部品
US20130285256A1 (en) * 2010-11-22 2013-10-31 Andreas Fischer Method and an apparatus for forming electrically conductive vias in a substrate, an automated robot-based manufacturing system, a component comprising a substrate with via holes, and an interposer device
JP2014143312A (ja) * 2013-01-24 2014-08-07 Napura:Kk 受動素子内蔵基板
JP2017157792A (ja) * 2016-03-04 2017-09-07 イビデン株式会社 電子部品内蔵基板及びその製造方法
WO2018139046A1 (ja) * 2017-01-27 2018-08-02 株式会社村田製作所 インターポーザ基板、回路モジュール、インターポーザ基板の製造方法
JP2021061264A (ja) * 2019-10-02 2021-04-15 味の素株式会社 インダクタ機能を有する配線基板及びその製造方法
JP2021061387A (ja) * 2019-10-08 2021-04-15 インテル コーポレイション 予め製造されたフェライトコアを有する同軸磁性インダクタ
JP2021086856A (ja) * 2019-11-25 2021-06-03 イビデン株式会社 インダクタ内蔵基板、インダクタ内蔵基板の製造方法

Also Published As

Publication number Publication date
US20250157905A1 (en) 2025-05-15
JP7769804B2 (ja) 2025-11-13
WO2024024069A1 (ja) 2024-02-01

Similar Documents

Publication Publication Date Title
JPWO2024024027A1 (https=)
BR102023014872A2 (https=)
BR102023012440A2 (https=)
BR102023010976A2 (https=)
BR102023009641A2 (https=)
BR102023008688A2 (https=)
BR102023007252A2 (https=)
BR102023005164A2 (https=)
BR102023001987A2 (https=)
JPWO2024024069A1 (https=)
BR202022009269U2 (https=)
BR202022005961U2 (https=)
BR202022001779U2 (https=)
BR202022000931U2 (https=)
BY13142U (https=)
BY13166U (https=)
BY13138U (https=)
BY13137U (https=)
BY13136U (https=)
CN307048188S (https=)
CN307048020S (https=)
CN307047648S (https=)
CN307046976S (https=)
CN307046549S (https=)
BY13140U (https=)

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20241112

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20241112

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20250805

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250929

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20251021

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20251031

R150 Certificate of patent or registration of utility model

Ref document number: 7769804

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150