JPWO2023157624A5 - - Google Patents

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Publication number
JPWO2023157624A5
JPWO2023157624A5 JP2024501072A JP2024501072A JPWO2023157624A5 JP WO2023157624 A5 JPWO2023157624 A5 JP WO2023157624A5 JP 2024501072 A JP2024501072 A JP 2024501072A JP 2024501072 A JP2024501072 A JP 2024501072A JP WO2023157624 A5 JPWO2023157624 A5 JP WO2023157624A5
Authority
JP
Japan
Prior art keywords
layer structure
interposer
outer layer
insulating resin
inner layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024501072A
Other languages
English (en)
Japanese (ja)
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JPWO2023157624A1 (https=
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/JP2023/002842 external-priority patent/WO2023157624A1/ja
Publication of JPWO2023157624A1 publication Critical patent/JPWO2023157624A1/ja
Publication of JPWO2023157624A5 publication Critical patent/JPWO2023157624A5/ja
Pending legal-status Critical Current

Links

JP2024501072A 2022-02-15 2023-01-30 Pending JPWO2023157624A1 (https=)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2022021044 2022-02-15
JP2022188815 2022-11-28
PCT/JP2023/002842 WO2023157624A1 (ja) 2022-02-15 2023-01-30 インターポーザ、半導体パッケージ及びそれらの製造方法

Publications (2)

Publication Number Publication Date
JPWO2023157624A1 JPWO2023157624A1 (https=) 2023-08-24
JPWO2023157624A5 true JPWO2023157624A5 (https=) 2025-04-22

Family

ID=87578489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024501072A Pending JPWO2023157624A1 (https=) 2022-02-15 2023-01-30

Country Status (5)

Country Link
US (1) US20250029930A1 (https=)
JP (1) JPWO2023157624A1 (https=)
KR (1) KR20240155879A (https=)
TW (1) TW202347639A (https=)
WO (1) WO2023157624A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026058684A1 (ja) * 2024-09-11 2026-03-19 Toppanホールディングス株式会社 インターポーザ及び半導体パッケージ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4929784B2 (ja) * 2006-03-27 2012-05-09 富士通株式会社 多層配線基板、半導体装置およびソルダレジスト
JP4832369B2 (ja) * 2007-06-25 2011-12-07 富士通株式会社 回路基板、半導体装置、回路基板の製造方法、半導体装置の製造方法
JP5079475B2 (ja) * 2007-12-05 2012-11-21 新光電気工業株式会社 電子部品実装用パッケージ
JP5295596B2 (ja) * 2008-03-19 2013-09-18 新光電気工業株式会社 多層配線基板およびその製造方法
WO2013065287A1 (ja) 2011-11-01 2013-05-10 住友ベークライト株式会社 半導体パッケージの製造方法
JP2020088069A (ja) * 2018-11-20 2020-06-04 凸版印刷株式会社 半導体パッケージ基板およびその製造方法

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