JPWO2023132064A1 - - Google Patents
Info
- Publication number
- JPWO2023132064A1 JPWO2023132064A1 JP2023572320A JP2023572320A JPWO2023132064A1 JP WO2023132064 A1 JPWO2023132064 A1 JP WO2023132064A1 JP 2023572320 A JP2023572320 A JP 2023572320A JP 2023572320 A JP2023572320 A JP 2023572320A JP WO2023132064 A1 JPWO2023132064 A1 JP WO2023132064A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/44—Conductive materials thereof
- H10W20/4484—Superconducting materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/66—Conductive materials thereof
- H10W70/668—Superconducting materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Computing Systems (AREA)
- Evolutionary Computation (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Artificial Intelligence (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Photovoltaic Devices (AREA)
- Recrystallisation Techniques (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2022/000385 WO2023132064A1 (ja) | 2022-01-07 | 2022-01-07 | 量子演算装置及び量子演算装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2023132064A1 true JPWO2023132064A1 (https=) | 2023-07-13 |
| JPWO2023132064A5 JPWO2023132064A5 (https=) | 2024-08-02 |
| JP7666653B2 JP7666653B2 (ja) | 2025-04-22 |
Family
ID=87073573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023572320A Active JP7666653B2 (ja) | 2022-01-07 | 2022-01-07 | 量子演算装置及び量子演算装置の製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| EP (2) | EP4730215A3 (https=) |
| JP (1) | JP7666653B2 (https=) |
| WO (1) | WO2023132064A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2025046715A1 (ja) * | 2023-08-28 | 2025-03-06 | 富士通株式会社 | 量子ビットデバイス及び量子ビットデバイスの製造方法 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04338683A (ja) * | 1991-05-16 | 1992-11-25 | Fujitsu Ltd | 超伝導集積回路素子とその実装方法 |
| JPH11177157A (ja) * | 1997-12-08 | 1999-07-02 | Agency Of Ind Science & Technol | 超電導集積回路構造及びその製造方法 |
| US20180013052A1 (en) * | 2015-07-23 | 2018-01-11 | Massachusetts Institute Of Technology | Qubit and Coupler Circuit Structures and Coupling Techniques |
| JP2019532505A (ja) * | 2016-09-13 | 2019-11-07 | グーグル エルエルシー | 積層量子デバイス内の損失の低減 |
| JP2021072351A (ja) * | 2019-10-30 | 2021-05-06 | 日本電気株式会社 | 超伝導回路装置、スペーサ、及び超伝導回路装置の製造方法 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9836699B1 (en) * | 2015-04-27 | 2017-12-05 | Rigetti & Co. | Microwave integrated quantum circuits with interposer |
| WO2017155531A1 (en) * | 2016-03-10 | 2017-09-14 | Technische Universiteit Delft | Superconducting microwave-frequency vias for mult-planar quantum circuits |
| US10804399B2 (en) * | 2016-09-24 | 2020-10-13 | Intel Corporation | Double-sided quantum dot devices |
| WO2019059879A1 (en) * | 2017-09-19 | 2019-03-28 | Google Llc | PILLARS AS FALLS FOR PRECISE CHIP CHIP SEPARATION |
| US10347605B2 (en) | 2017-11-28 | 2019-07-09 | International Business Machines Corporation | System and method for routing signals in complex quantum systems |
| US11165010B2 (en) | 2019-02-11 | 2021-11-02 | International Business Machines Corporation | Cold-welded flip chip interconnect structure |
-
2022
- 2022-01-07 EP EP26150016.9A patent/EP4730215A3/en active Pending
- 2022-01-07 JP JP2023572320A patent/JP7666653B2/ja active Active
- 2022-01-07 EP EP22918653.1A patent/EP4475177A4/en active Pending
- 2022-01-07 WO PCT/JP2022/000385 patent/WO2023132064A1/ja not_active Ceased
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04338683A (ja) * | 1991-05-16 | 1992-11-25 | Fujitsu Ltd | 超伝導集積回路素子とその実装方法 |
| JPH11177157A (ja) * | 1997-12-08 | 1999-07-02 | Agency Of Ind Science & Technol | 超電導集積回路構造及びその製造方法 |
| US20180013052A1 (en) * | 2015-07-23 | 2018-01-11 | Massachusetts Institute Of Technology | Qubit and Coupler Circuit Structures and Coupling Techniques |
| JP2019532505A (ja) * | 2016-09-13 | 2019-11-07 | グーグル エルエルシー | 積層量子デバイス内の損失の低減 |
| JP2021072351A (ja) * | 2019-10-30 | 2021-05-06 | 日本電気株式会社 | 超伝導回路装置、スペーサ、及び超伝導回路装置の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023132064A1 (ja) | 2023-07-13 |
| EP4475177A4 (en) | 2025-07-16 |
| EP4730215A3 (en) | 2026-05-06 |
| EP4475177A1 (en) | 2024-12-11 |
| JP7666653B2 (ja) | 2025-04-22 |
| EP4730215A2 (en) | 2026-04-22 |
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