JPWO2023106249A5 - - Google Patents

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Publication number
JPWO2023106249A5
JPWO2023106249A5 JP2023566302A JP2023566302A JPWO2023106249A5 JP WO2023106249 A5 JPWO2023106249 A5 JP WO2023106249A5 JP 2023566302 A JP2023566302 A JP 2023566302A JP 2023566302 A JP2023566302 A JP 2023566302A JP WO2023106249 A5 JPWO2023106249 A5 JP WO2023106249A5
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JP
Japan
Prior art keywords
pulse signal
input
output
terminal
block circuit
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JP2023566302A
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English (en)
Japanese (ja)
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JPWO2023106249A1 (https=
JP7659852B2 (ja
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Priority claimed from PCT/JP2022/044655 external-priority patent/WO2023106249A1/ja
Publication of JPWO2023106249A1 publication Critical patent/JPWO2023106249A1/ja
Publication of JPWO2023106249A5 publication Critical patent/JPWO2023106249A5/ja
Application granted granted Critical
Publication of JP7659852B2 publication Critical patent/JP7659852B2/ja
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JP2023566302A 2021-12-07 2022-12-05 モジュール回路、及びレザバー回路 Active JP7659852B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021198579 2021-12-07
JP2021198579 2021-12-07
PCT/JP2022/044655 WO2023106249A1 (ja) 2021-12-07 2022-12-05 モジュール回路、及びレザバー回路

Publications (3)

Publication Number Publication Date
JPWO2023106249A1 JPWO2023106249A1 (https=) 2023-06-15
JPWO2023106249A5 true JPWO2023106249A5 (https=) 2024-07-30
JP7659852B2 JP7659852B2 (ja) 2025-04-10

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ID=86730344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023566302A Active JP7659852B2 (ja) 2021-12-07 2022-12-05 モジュール回路、及びレザバー回路

Country Status (3)

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US (1) US12525968B2 (https=)
JP (1) JP7659852B2 (https=)
WO (1) WO2023106249A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025239025A1 (ja) * 2024-05-17 2025-11-20 ソニーセミコンダクタソリューションズ株式会社 電子回路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0390226A1 (en) * 1984-07-31 1990-10-03 Yamaha Corporation Jitter absorption circuit
US6819190B2 (en) * 2002-12-10 2004-11-16 Intersil Americas Inc. Robust fractional clock-based pulse generator for digital pulse width modulator
JP4780921B2 (ja) 2004-03-17 2011-09-28 キヤノン株式会社 並列パルス信号処理装置、及びその制御方法
US7271754B2 (en) * 2005-02-22 2007-09-18 The Regents Of The University Of Colorado, A Body Corporate Digital pulse-width modulator
US10396807B1 (en) * 2016-02-08 2019-08-27 Auburn University Multi-ring coupled ring oscillator with improved phase noise
US20180191356A1 (en) * 2017-01-03 2018-07-05 Allegro Microsystems, Llc Control circuit
US10803383B2 (en) 2017-01-25 2020-10-13 Electronics And Telecommunications Research Institute Neuromorphic arithmetic device

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