JPWO2021256433A1 - - Google Patents

Info

Publication number
JPWO2021256433A1
JPWO2021256433A1 JP2022531812A JP2022531812A JPWO2021256433A1 JP WO2021256433 A1 JPWO2021256433 A1 JP WO2021256433A1 JP 2022531812 A JP2022531812 A JP 2022531812A JP 2022531812 A JP2022531812 A JP 2022531812A JP WO2021256433 A1 JPWO2021256433 A1 JP WO2021256433A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2022531812A
Other versions
JP7320886B2 (ja
JPWO2021256433A5 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2021256433A1 publication Critical patent/JPWO2021256433A1/ja
Publication of JPWO2021256433A5 publication Critical patent/JPWO2021256433A5/ja
Application granted granted Critical
Publication of JP7320886B2 publication Critical patent/JP7320886B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7555—Mechanical means, e.g. for planarising, pressing, stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/759—Means for monitoring the connection process
    • H01L2224/7592—Load or pressure adjusting means, e.g. sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
JP2022531812A 2020-06-15 2021-06-14 半導体装置の製造装置および製造方法 Active JP7320886B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2020103333 2020-06-15
JP2020103333 2020-06-15
PCT/JP2021/022561 WO2021256433A1 (ja) 2020-06-15 2021-06-14 半導体装置の製造装置および製造方法

Publications (3)

Publication Number Publication Date
JPWO2021256433A1 true JPWO2021256433A1 (ja) 2021-12-23
JPWO2021256433A5 JPWO2021256433A5 (ja) 2023-02-22
JP7320886B2 JP7320886B2 (ja) 2023-08-04

Family

ID=79268052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022531812A Active JP7320886B2 (ja) 2020-06-15 2021-06-14 半導体装置の製造装置および製造方法

Country Status (5)

Country Link
US (1) US20230230853A1 (ja)
JP (1) JP7320886B2 (ja)
CN (1) CN115699277A (ja)
TW (1) TWI801873B (ja)
WO (1) WO2021256433A1 (ja)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09153525A (ja) * 1995-11-30 1997-06-10 Toshiba Corp ボンディング装置およびボンディング方法
JPH11145197A (ja) * 1997-11-10 1999-05-28 Matsushita Electric Ind Co Ltd 半田バンプ付電子部品の熱圧着方法
JP2000195907A (ja) * 1998-12-25 2000-07-14 Matsushita Electric Ind Co Ltd 部品実装方法と装置
JP2003179100A (ja) * 2001-10-05 2003-06-27 Nec Corp 電子部品の製造装置および電子部品の製造方法
JP2006073873A (ja) * 2004-09-03 2006-03-16 Matsushita Electric Ind Co Ltd 電子部品実装方法及び装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW501242B (en) * 2000-09-15 2002-09-01 Hitachi Ltd Semiconductor package and flip chip bonding method of semiconductor package
US9685478B2 (en) * 2012-11-16 2017-06-20 Sharp Kabushiki Kaisha Flip-chip bonding method and solid-state image pickup device manufacturing method characterized in including flip-chip bonding method
US9426898B2 (en) * 2014-06-30 2016-08-23 Kulicke And Soffa Industries, Inc. Thermocompression bonders, methods of operating thermocompression bonders, and interconnect methods for fine pitch flip chip assembly

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09153525A (ja) * 1995-11-30 1997-06-10 Toshiba Corp ボンディング装置およびボンディング方法
JPH11145197A (ja) * 1997-11-10 1999-05-28 Matsushita Electric Ind Co Ltd 半田バンプ付電子部品の熱圧着方法
JP2000195907A (ja) * 1998-12-25 2000-07-14 Matsushita Electric Ind Co Ltd 部品実装方法と装置
JP2003179100A (ja) * 2001-10-05 2003-06-27 Nec Corp 電子部品の製造装置および電子部品の製造方法
JP2006073873A (ja) * 2004-09-03 2006-03-16 Matsushita Electric Ind Co Ltd 電子部品実装方法及び装置

Also Published As

Publication number Publication date
KR20230006011A (ko) 2023-01-10
TW202213574A (zh) 2022-04-01
US20230230853A1 (en) 2023-07-20
TWI801873B (zh) 2023-05-11
CN115699277A (zh) 2023-02-03
JP7320886B2 (ja) 2023-08-04
WO2021256433A1 (ja) 2021-12-23

Similar Documents

Publication Publication Date Title
BR112023005462A2 (ja)
BR112023012656A2 (ja)
BR112021014123A2 (ja)
BR112022009896A2 (ja)
BR112023009656A2 (ja)
BR112022024743A2 (ja)
BR112023006729A2 (ja)
BR102021018859A2 (ja)
BR102021015500A2 (ja)
BR102021007058A2 (ja)
BR112023008622A2 (ja)
BR102020022030A2 (ja)
BR112023011738A2 (ja)
BR112023016292A2 (ja)
BR112023004146A2 (ja)
BR112023011610A2 (ja)
BR112023011539A2 (ja)
BR112023008976A2 (ja)
BR102021020147A2 (ja)
BR102021018926A2 (ja)
BR102021018167A2 (ja)
BR102021017576A2 (ja)
BR102021016837A2 (ja)
BR102021016551A2 (ja)
BR102021016375A2 (ja)

Legal Events

Date Code Title Description
A529 Written submission of copy of amendment under article 34 pct

Free format text: JAPANESE INTERMEDIATE CODE: A5211

Effective date: 20221025

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20221025

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230627

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230718

R150 Certificate of patent or registration of utility model

Ref document number: 7320886

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150