JPWO2021245915A1 - - Google Patents

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Publication number
JPWO2021245915A1
JPWO2021245915A1 JP2022528375A JP2022528375A JPWO2021245915A1 JP WO2021245915 A1 JPWO2021245915 A1 JP WO2021245915A1 JP 2022528375 A JP2022528375 A JP 2022528375A JP 2022528375 A JP2022528375 A JP 2022528375A JP WO2021245915 A1 JPWO2021245915 A1 JP WO2021245915A1
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Japan
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JP2022528375A
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JPWO2021245915A5 (ja
JP7286016B2 (ja
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    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/1624—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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JP2010021338A (ja) * 2008-07-10 2010-01-28 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2010027813A (ja) * 2008-07-18 2010-02-04 Mitsubishi Electric Corp 電力用半導体装置
JP2012004226A (ja) * 2010-06-15 2012-01-05 Mitsubishi Electric Corp 電力用半導体装置
WO2012011210A1 (ja) * 2010-07-22 2012-01-26 パナソニック株式会社 半導体装置及びその製造方法
JP2013102112A (ja) * 2011-10-12 2013-05-23 Fuji Electric Co Ltd 半導体装置及び半導体装置の製造方法
JP2016092233A (ja) * 2014-11-05 2016-05-23 富士電機株式会社 半導体装置
JP2019110284A (ja) * 2017-12-19 2019-07-04 富士電機株式会社 半導体モジュール及び半導体モジュールの製造方法

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JP2010021338A (ja) * 2008-07-10 2010-01-28 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2010027813A (ja) * 2008-07-18 2010-02-04 Mitsubishi Electric Corp 電力用半導体装置
JP2012004226A (ja) * 2010-06-15 2012-01-05 Mitsubishi Electric Corp 電力用半導体装置
WO2012011210A1 (ja) * 2010-07-22 2012-01-26 パナソニック株式会社 半導体装置及びその製造方法
JP2013102112A (ja) * 2011-10-12 2013-05-23 Fuji Electric Co Ltd 半導体装置及び半導体装置の製造方法
JP2016092233A (ja) * 2014-11-05 2016-05-23 富士電機株式会社 半導体装置
JP2019110284A (ja) * 2017-12-19 2019-07-04 富士電機株式会社 半導体モジュール及び半導体モジュールの製造方法

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