JPWO2021192788A1 - - Google Patents
Info
- Publication number
- JPWO2021192788A1 JPWO2021192788A1 JP2022509432A JP2022509432A JPWO2021192788A1 JP WO2021192788 A1 JPWO2021192788 A1 JP WO2021192788A1 JP 2022509432 A JP2022509432 A JP 2022509432A JP 2022509432 A JP2022509432 A JP 2022509432A JP WO2021192788 A1 JPWO2021192788 A1 JP WO2021192788A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Device Packages (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020050705 | 2020-03-23 | ||
PCT/JP2021/006842 WO2021192788A1 (ja) | 2020-03-23 | 2021-02-24 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
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JPWO2021192788A1 true JPWO2021192788A1 (ja) | 2021-09-30 |
Family
ID=77891179
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2022509432A Pending JPWO2021192788A1 (ja) | 2020-03-23 | 2021-02-24 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20230098414A1 (ja) |
JP (1) | JPWO2021192788A1 (ja) |
CN (1) | CN115315822A (ja) |
WO (1) | WO2021192788A1 (ja) |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3682468B2 (ja) * | 1995-12-11 | 2005-08-10 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
JP3913138B2 (ja) * | 2002-08-16 | 2007-05-09 | ローム株式会社 | 半導体チップを使用した半導体装置 |
JP2005197360A (ja) * | 2004-01-05 | 2005-07-21 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP4940900B2 (ja) * | 2006-11-08 | 2012-05-30 | 日亜化学工業株式会社 | 実装用部品、および半導体装置 |
JP6892261B2 (ja) * | 2016-12-22 | 2021-06-23 | ローム株式会社 | Ledパッケージ |
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2021
- 2021-02-24 US US17/911,359 patent/US20230098414A1/en active Pending
- 2021-02-24 JP JP2022509432A patent/JPWO2021192788A1/ja active Pending
- 2021-02-24 CN CN202180023324.5A patent/CN115315822A/zh active Pending
- 2021-02-24 WO PCT/JP2021/006842 patent/WO2021192788A1/ja active Application Filing
Also Published As
Publication number | Publication date |
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CN115315822A (zh) | 2022-11-08 |
US20230098414A1 (en) | 2023-03-30 |
WO2021192788A1 (ja) | 2021-09-30 |
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