JPWO2021101972A5 - - Google Patents
Download PDFInfo
- Publication number
- JPWO2021101972A5 JPWO2021101972A5 JP2022528942A JP2022528942A JPWO2021101972A5 JP WO2021101972 A5 JPWO2021101972 A5 JP WO2021101972A5 JP 2022528942 A JP2022528942 A JP 2022528942A JP 2022528942 A JP2022528942 A JP 2022528942A JP WO2021101972 A5 JPWO2021101972 A5 JP WO2021101972A5
- Authority
- JP
- Japan
- Prior art keywords
- delay
- output
- delay line
- adaptive loop
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/687,147 US10897245B1 (en) | 2019-11-18 | 2019-11-18 | Clockless delay adaptation loop for random data |
US16/687,147 | 2019-11-18 | ||
PCT/US2020/061021 WO2021101972A1 (en) | 2019-11-18 | 2020-11-18 | Clockless delay adaptation loop for random data |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2023504360A JP2023504360A (ja) | 2023-02-03 |
JPWO2021101972A5 true JPWO2021101972A5 (de) | 2023-11-07 |
Family
ID=74180665
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2022528942A Pending JP2023504360A (ja) | 2019-11-18 | 2020-11-18 | ランダムデータのためのクロックレス遅延適応ループ |
Country Status (4)
Country | Link |
---|---|
US (2) | US10897245B1 (de) |
EP (1) | EP4062612A4 (de) |
JP (1) | JP2023504360A (de) |
WO (1) | WO2021101972A1 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10897245B1 (en) * | 2019-11-18 | 2021-01-19 | Texas Instruments Incorporated | Clockless delay adaptation loop for random data |
US11323109B2 (en) * | 2020-06-29 | 2022-05-03 | Texas Instruments Incorporated | Self-referenced clockless delay adaptation for random data |
US20230308316A1 (en) * | 2022-03-28 | 2023-09-28 | Mediatek Inc. | Decision-feedback equalizer using feedback filter with controllable delay circuit and associated method |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5570052A (en) | 1995-06-07 | 1996-10-29 | Philips Electronics North America Corporation | Detection circuit with differential input and hysteresis proportional to the peak input voltage |
US6680634B1 (en) * | 2002-12-03 | 2004-01-20 | Nokia Corporation | Self calibrating digital delay-locked loop |
US8081021B2 (en) | 2006-09-29 | 2011-12-20 | Hynix Semiconductor Inc. | Delay locked loop |
US8385401B2 (en) * | 2008-10-20 | 2013-02-26 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd | Equalizer and method for performing equalization |
KR101123073B1 (ko) | 2009-05-21 | 2012-03-05 | 주식회사 하이닉스반도체 | 지연고정루프회로 및 이를 이용한 반도체 메모리 장치 |
GB201015730D0 (en) | 2010-09-20 | 2010-10-27 | Novelda As | Continuous time cross-correlator |
US9231793B1 (en) * | 2014-05-19 | 2016-01-05 | Albert Vareljian | Full bridge decision feedback equalizer |
TWI537965B (zh) * | 2014-11-07 | 2016-06-11 | Phison Electronics Corp | 取樣電路模組、記憶體控制電路單元及資料取樣方法 |
DK178680B1 (en) | 2015-04-10 | 2016-11-07 | Pr Electronics As | Zero drift, limitless and adjustable reference voltage generation |
US9900121B1 (en) | 2016-09-08 | 2018-02-20 | Futurewei Technologies, Inc. | Apparatus, system, and method for reducing a number of intersymbol interference components to be suppressed |
US10236897B1 (en) | 2018-07-26 | 2019-03-19 | Texas Instruments Incorporated | Loss of lock detector |
US10897245B1 (en) * | 2019-11-18 | 2021-01-19 | Texas Instruments Incorporated | Clockless delay adaptation loop for random data |
-
2019
- 2019-11-18 US US16/687,147 patent/US10897245B1/en active Active
-
2020
- 2020-11-18 EP EP20890912.7A patent/EP4062612A4/de active Pending
- 2020-11-18 JP JP2022528942A patent/JP2023504360A/ja active Pending
- 2020-11-18 WO PCT/US2020/061021 patent/WO2021101972A1/en unknown
- 2020-12-11 US US17/119,050 patent/US11239834B2/en active Active
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4021738A (en) | Adaptive equalizer with fast convergence properties | |
US8761237B2 (en) | Low nonlinear distortion variable gain amplifier | |
US8331513B2 (en) | Clock data restoration device | |
US4052562A (en) | System for control of speech direction in duplex telephone circuits | |
US7843859B1 (en) | Analog echo canceller with filter banks | |
JPH07183852A (ja) | 光ファイバ伝送装置 | |
JPS6231227A (ja) | 適応等化器及びその方法 | |
US3757221A (en) | Automatic equalizer system for phase modulated data signals | |
US11323109B2 (en) | Self-referenced clockless delay adaptation for random data | |
US20080212607A1 (en) | Data Transfer Circuit | |
TWI693811B (zh) | 多位準脈衝振幅調變接收裝置 | |
US7508882B2 (en) | Electrical backplane transmission using duobinary signaling | |
JPWO2021101972A5 (de) | ||
WO2008095990A1 (en) | Loopback circuit | |
US11239834B2 (en) | Clockless delay adaptation loop for random data | |
EP2122475B1 (de) | Datentransferschaltung | |
CN110493152B (zh) | 基于频谱平衡方法的自适应均衡电路 | |
CN108206697A (zh) | 具有动态元件匹配的模数转换器 | |
US6438162B1 (en) | Implementation method for adaptive equalizer in CMOS | |
EP2119002B1 (de) | Mehrraten-tracking-schaltung | |
DE102004014448A1 (de) | Vorwärtsentzerrer und Verfahren zum analogen Entzerren eines Datensignals | |
CN117221056A (zh) | 高速SerDes中的模拟自适应三抽头判决反馈均衡器电路 | |
JP4706043B2 (ja) | イコライザ回路 | |
Vo | Analysis of LMS gain variation in DTC-based fractional-N digital PLLs | |
JP3008625B2 (ja) | ブリッジタップ自動等化器 |