JPWO2021059579A1 - - Google Patents

Info

Publication number
JPWO2021059579A1
JPWO2021059579A1 JP2021548323A JP2021548323A JPWO2021059579A1 JP WO2021059579 A1 JPWO2021059579 A1 JP WO2021059579A1 JP 2021548323 A JP2021548323 A JP 2021548323A JP 2021548323 A JP2021548323 A JP 2021548323A JP WO2021059579 A1 JPWO2021059579 A1 JP WO2021059579A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2021548323A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2021059579A1 publication Critical patent/JPWO2021059579A1/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007Fail-safe circuits
    • H03K19/0075Fail-safe circuits by using two redundant chains
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/3562Bistable circuits of the master-slave type
    • H03K3/35625Bistable circuits of the master-slave type using complementary field-effect transistors
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/31816Soft error testing; Soft error rate evaluation; Single event testing

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2021548323A 2019-09-27 2020-05-14 Pending JPWO2021059579A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019177834 2019-09-27
PCT/JP2020/019301 WO2021059579A1 (ja) 2019-09-27 2020-05-14 半導体装置

Publications (1)

Publication Number Publication Date
JPWO2021059579A1 true JPWO2021059579A1 (ja) 2021-04-01

Family

ID=75165974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021548323A Pending JPWO2021059579A1 (ja) 2019-09-27 2020-05-14

Country Status (4)

Country Link
US (1) US20220200595A1 (ja)
JP (1) JPWO2021059579A1 (ja)
CN (1) CN114365284A (ja)
WO (1) WO2021059579A1 (ja)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08306867A (ja) * 1995-05-11 1996-11-22 Yamaha Corp 半導体集積回路
JP2008102666A (ja) * 2006-10-18 2008-05-01 Toshiba Corp 半導体回路設計装置、半導体回路設計方法および半導体装置
US20130038348A1 (en) * 2008-01-17 2013-02-14 Klas Olof Lilja Layout method for soft-error hard electronics, and radiation hardened logic cell
JP2010092963A (ja) * 2008-10-06 2010-04-22 Nec Electronics Corp 半導体装置
JP5716298B2 (ja) * 2010-06-22 2015-05-13 富士通セミコンダクター株式会社 半導体装置
KR102567233B1 (ko) * 2016-11-08 2023-08-17 에스케이하이닉스 주식회사 다이스 래치들을 갖는 반도체 장치
JP6858941B2 (ja) * 2016-12-26 2021-04-14 国立大学法人東北大学 不揮発性ラッチ装置及び不揮発性フリップフロップ装置
JP7283697B2 (ja) * 2017-06-12 2023-05-30 国立研究開発法人宇宙航空研究開発機構 シングルイベントアップセット耐性のラッチ回路及びフリップフロップ回路

Also Published As

Publication number Publication date
CN114365284A (zh) 2022-04-15
US20220200595A1 (en) 2022-06-23
WO2021059579A1 (ja) 2021-04-01

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Legal Events

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Effective date: 20230428

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