JPWO2021059579A1 - - Google Patents
Info
- Publication number
- JPWO2021059579A1 JPWO2021059579A1 JP2021548323A JP2021548323A JPWO2021059579A1 JP WO2021059579 A1 JPWO2021059579 A1 JP WO2021059579A1 JP 2021548323 A JP2021548323 A JP 2021548323A JP 2021548323 A JP2021548323 A JP 2021548323A JP WO2021059579 A1 JPWO2021059579 A1 JP WO2021059579A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/007—Fail-safe circuits
- H03K19/0075—Fail-safe circuits by using two redundant chains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
- H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/31816—Soft error testing; Soft error rate evaluation; Single event testing
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019177834 | 2019-09-27 | ||
PCT/JP2020/019301 WO2021059579A1 (ja) | 2019-09-27 | 2020-05-14 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPWO2021059579A1 true JPWO2021059579A1 (ja) | 2021-04-01 |
Family
ID=75165974
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2021548323A Pending JPWO2021059579A1 (ja) | 2019-09-27 | 2020-05-14 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20220200595A1 (ja) |
JP (1) | JPWO2021059579A1 (ja) |
CN (1) | CN114365284A (ja) |
WO (1) | WO2021059579A1 (ja) |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08306867A (ja) * | 1995-05-11 | 1996-11-22 | Yamaha Corp | 半導体集積回路 |
JP2008102666A (ja) * | 2006-10-18 | 2008-05-01 | Toshiba Corp | 半導体回路設計装置、半導体回路設計方法および半導体装置 |
US20130038348A1 (en) * | 2008-01-17 | 2013-02-14 | Klas Olof Lilja | Layout method for soft-error hard electronics, and radiation hardened logic cell |
JP2010092963A (ja) * | 2008-10-06 | 2010-04-22 | Nec Electronics Corp | 半導体装置 |
JP5716298B2 (ja) * | 2010-06-22 | 2015-05-13 | 富士通セミコンダクター株式会社 | 半導体装置 |
KR102567233B1 (ko) * | 2016-11-08 | 2023-08-17 | 에스케이하이닉스 주식회사 | 다이스 래치들을 갖는 반도체 장치 |
JP6858941B2 (ja) * | 2016-12-26 | 2021-04-14 | 国立大学法人東北大学 | 不揮発性ラッチ装置及び不揮発性フリップフロップ装置 |
JP7283697B2 (ja) * | 2017-06-12 | 2023-05-30 | 国立研究開発法人宇宙航空研究開発機構 | シングルイベントアップセット耐性のラッチ回路及びフリップフロップ回路 |
-
2020
- 2020-05-14 JP JP2021548323A patent/JPWO2021059579A1/ja active Pending
- 2020-05-14 WO PCT/JP2020/019301 patent/WO2021059579A1/ja active Application Filing
- 2020-05-14 CN CN202080062985.4A patent/CN114365284A/zh active Pending
-
2022
- 2022-03-09 US US17/690,600 patent/US20220200595A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
CN114365284A (zh) | 2022-04-15 |
US20220200595A1 (en) | 2022-06-23 |
WO2021059579A1 (ja) | 2021-04-01 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20230428 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20240514 |