JPWO2020230317A1 - - Google Patents

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Publication number
JPWO2020230317A1
JPWO2020230317A1 JP2021519227A JP2021519227A JPWO2020230317A1 JP WO2020230317 A1 JPWO2020230317 A1 JP WO2020230317A1 JP 2021519227 A JP2021519227 A JP 2021519227A JP 2021519227 A JP2021519227 A JP 2021519227A JP WO2020230317 A1 JPWO2020230317 A1 JP WO2020230317A1
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2021519227A
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Publication date
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Publication of JPWO2020230317A1 publication Critical patent/JPWO2020230317A1/ja
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/0242Crystalline insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02461Phosphides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02463Arsenides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02483Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02488Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/02546Arsenides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02565Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639Preparation of substrate for selective deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
JP2021519227A 2019-05-16 2019-05-16 Pending JPWO2020230317A1 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/019489 WO2020230317A1 (ja) 2019-05-16 2019-05-16 半導体積層構造

Publications (1)

Publication Number Publication Date
JPWO2020230317A1 true JPWO2020230317A1 (ja) 2020-11-19

Family

ID=73290283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021519227A Pending JPWO2020230317A1 (ja) 2019-05-16 2019-05-16

Country Status (3)

Country Link
US (1) US20220254633A1 (ja)
JP (1) JPWO2020230317A1 (ja)
WO (1) WO2020230317A1 (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001102303A (ja) * 1999-09-28 2001-04-13 Kyocera Corp 化合物半導体基板の製造方法
JP2001345266A (ja) * 2000-02-24 2001-12-14 Matsushita Electric Ind Co Ltd 半導体装置,その製造方法及び半導体基板の製造方法
JP2008546181A (ja) * 2005-05-17 2008-12-18 アンバーウェーブ システムズ コーポレイション 転位欠陥密度の低い格子不整合半導体構造およびこれに関連するデバイス製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621414A (en) * 1985-03-04 1986-11-11 Advanced Micro Devices, Inc. Method of making an isolation slot for integrated circuit structure
US6830976B2 (en) * 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6939730B2 (en) * 2001-04-24 2005-09-06 Sony Corporation Nitride semiconductor, semiconductor device, and method of manufacturing the same
AU2003274922A1 (en) * 2002-08-23 2004-03-11 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups and related methods
JP2004304167A (ja) * 2003-03-20 2004-10-28 Advanced Lcd Technologies Development Center Co Ltd 配線、表示装置及び、これらの形成方法
JP2004363241A (ja) * 2003-06-03 2004-12-24 Advanced Lcd Technologies Development Center Co Ltd 結晶化半導体層の形成方法及び形成装置ならびに半導体装置の製造方法
US8193538B2 (en) * 2007-01-22 2012-06-05 Diamond Microwave Devices Limited Electronic field effect devices
JP4531071B2 (ja) * 2007-02-20 2010-08-25 富士通株式会社 化合物半導体装置
US8274097B2 (en) * 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8759203B2 (en) * 2009-11-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Growing III-V compound semiconductors from trenches filled with intermediate layers
KR20120032329A (ko) * 2010-09-28 2012-04-05 삼성전자주식회사 반도체 소자
US9373688B2 (en) * 2011-05-04 2016-06-21 Infineon Technologies Austria Ag Normally-off high electron mobility transistors
EP3154092B1 (en) * 2013-02-15 2021-12-15 AZUR SPACE Solar Power GmbH P-doping of group iii-nitride buffer layer structure on a heterosubstrate
US9245991B2 (en) * 2013-08-12 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, high electron mobility transistor (HEMT) and method of manufacturing
US10792106B2 (en) * 2016-10-28 2020-10-06 Covidien Lp System for calibrating an electromagnetic navigation system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001102303A (ja) * 1999-09-28 2001-04-13 Kyocera Corp 化合物半導体基板の製造方法
JP2001345266A (ja) * 2000-02-24 2001-12-14 Matsushita Electric Ind Co Ltd 半導体装置,その製造方法及び半導体基板の製造方法
JP2008546181A (ja) * 2005-05-17 2008-12-18 アンバーウェーブ システムズ コーポレイション 転位欠陥密度の低い格子不整合半導体構造およびこれに関連するデバイス製造方法

Also Published As

Publication number Publication date
US20220254633A1 (en) 2022-08-11
WO2020230317A1 (ja) 2020-11-19

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