JPWO2020175684A1 - - Google Patents

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Publication number
JPWO2020175684A1
JPWO2020175684A1 JP2021502652A JP2021502652A JPWO2020175684A1 JP WO2020175684 A1 JPWO2020175684 A1 JP WO2020175684A1 JP 2021502652 A JP2021502652 A JP 2021502652A JP 2021502652 A JP2021502652 A JP 2021502652A JP WO2020175684 A1 JPWO2020175684 A1 JP WO2020175684A1
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Japan
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JP2021502652A
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JP7267394B2 (ja
JPWO2020175684A5 (ja
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    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)
  • Recrystallisation Techniques (AREA)
JP2021502652A 2019-02-28 2020-02-28 半導体素子の製造方法および半導体素子体 Active JP7267394B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019036097 2019-02-28
JP2019036097 2019-02-28
PCT/JP2020/008399 WO2020175684A1 (ja) 2019-02-28 2020-02-28 半導体素子の製造方法および半導体素子体

Publications (3)

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JPWO2020175684A1 true JPWO2020175684A1 (ja) 2020-09-03
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007096114A (ja) * 2005-09-29 2007-04-12 Sanyo Electric Co Ltd 半導体発光素子及び半導体発光素子の製造方法
JP2011066390A (ja) * 2009-08-20 2011-03-31 Pawdec:Kk 半導体素子の製造方法

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JPS4638958B1 (ja) 1962-03-20 1971-11-16
JP4731180B2 (ja) * 2005-02-21 2011-07-20 三洋電機株式会社 窒化物系半導体素子の製造方法
JP5070247B2 (ja) * 2009-06-23 2012-11-07 株式会社沖データ 半導体装置の製造方法、及び半導体装置
JP5466479B2 (ja) * 2009-10-27 2014-04-09 スタンレー電気株式会社 半導体素子の製造方法
CN106233429B (zh) * 2014-04-16 2019-06-18 耶鲁大学 获得平坦的半极性氮化镓表面的方法
US20230260943A1 (en) * 2022-02-17 2023-08-17 Micron Technology, Inc. Semiconductor die assemblies with flexible interconnects and associated methods and systems

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007096114A (ja) * 2005-09-29 2007-04-12 Sanyo Electric Co Ltd 半導体発光素子及び半導体発光素子の製造方法
JP2011066390A (ja) * 2009-08-20 2011-03-31 Pawdec:Kk 半導体素子の製造方法

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