JPWO2020150013A5

JPWO2020150013A5 -

Info

Publication number: JPWO2020150013A5
Application number: JP2021540807A
Authority: JP
Publication date: 2023-01-04
Anticipated expiration: 2040-01-04

Claims

A computer-implemented method comprising:
receiving source code expressed in a multithreaded programming language, the source code including branching statements directing execution to one of a plurality of source code paths;
compiling the source code into a circuit description including a pipeline, the pipeline including a plurality of code paths associated with the plurality of source code paths, the compiling comprising:
determining the number of pipeline stages in one of the plurality of code paths having the maximum number of pipeline stages;
adding pipeline stages to at least one of the plurality of code paths until each of the plurality of code paths has the number of pipeline stages ;
generating a synchronous digital circuit comprising a circuit implementation based on the circuit description.

2. The computer-implemented method of claim 1, wherein threads enter the pipeline in a first order and wherein threads exit the pipeline in the first order.

adding pipeline stages to one or more of the plurality of code paths comprises determining a number of pipeline stages in the longest code path; and adding a number of pipeline stages to each code path equal to the number of pipeline stages in the longest code path minus the number of pipeline stages.

The pipeline comprises a first pipeline, the circuit description comprises a second pipeline, and threads executing the first pipeline execute by pushing local variables onto a first-in-first-out queue. to the second pipeline, which maintains thread execution order throughout the pipeline by reading local variables from a first-in-first-out queue in the order they were pushed. computer-implemented method.

The source code includes a permuted block construct that wraps a programming construct that does not preserve thread execution order, the permuted block construct comprising:
record the order of execution of incoming threads,
allow threads to perform constructions that do not preserve the thread's order of execution,
2. The computer-implemented method of claim 1, mapping to a circuit implementation that blocks restarting a thread until all subordinate threads have restarted.

2. The computer-implemented method of claim 1 , wherein at least one of said additional pipeline stages comprises a computation unit and is configured to store results produced by said computation unit in a register .

2. The computer-implemented method of claim 1, wherein the pipeline comprises stages that are executed in order, and wherein multiple threads maintain execution order by passing through the stages in order.

a computing device,
one or more processors;
When executed by the one or more processors, to the computing device:
receive source code expressed in a multithreaded programming language;
A circuit comprising said source code into a first pipeline, a second pipeline, and a first-in-first-out (FIFO) queue storing a set of local thread variables to be passed from said first pipeline to said second pipeline. Having the description compiled, the first pipeline stores a set of local thread variables into the FIFO queue in thread execution order, and the second pipeline stores a set of local thread variables from the FIFO queue in thread execution order. maintaining execution order of the threads by obtaining a set of local thread variables, the source code including branching statements directing execution to one of a plurality of source code paths; includes a plurality of code paths associated with the plurality of source code paths, wherein one or more pipeline stages are associated with the plurality of code paths such that the plurality of code paths have the same number of pipeline stages. added to one or more of the paths, wherein at least one of said added pipeline stages includes a computation unit and is configured to store a result produced by said computation unit in a register;
and at least one computer storage medium storing computer-executable instructions for generating a synchronous digital circuit comprising a circuit implementation based on the circuit description.

Adding pipeline stages to one or more of the plurality of code paths comprises: determining a number of pipeline stages in a longest code path; determining the number of pipeline stages in that code path; adding a number of pipeline stages to each code path equal to the number of pipeline stages in the longest code path minus the number of pipeline stages.

The source code includes a permuted block construct that wraps a programming construct that does not preserve thread execution order, the permuted block construct comprising:
record the order of execution of incoming threads,
allow threads to perform constructions that do not preserve the thread's order of execution,
9. The computing device of claim 8, mapping to a circuit implementation that blocks restarting a thread until all subordinate threads have restarted.

11. The computing device of claim 10 , wherein threads exit the reorder block in the order they entered.

9. The computing device of claim 8, wherein a thread comprises a set of local thread variables provided to said first pipeline for execution.

9. The computing device of claim 8, wherein the first pipeline comprises stages that are executed in sequence, and wherein multiple threads maintain execution order by passing through the stages in sequence.

To a computing device when executed by one or more processors:
receiving source code expressed in a multithreaded programming language, said source code comprising constructs for mapping to a circuit implementation, said constructs comprising a reordering block and constructs that do not preserve thread execution order, said The circuit implementation is
a reordering buffer that registers thread identifiers in the order in which the threads were received;
a circuit that executes for an unknown number of clock cycles for each of the plurality of threads, wherein the reorder buffer blocks thread restart until all threads with lower execution order have been restarted;
compiling the construction into a circuit description;
At least one computer storage medium storing computer-executable instructions for generating a synchronous digital circuit comprising the circuit implementation based on the circuit description.

The source code includes branch statements directing execution to one of a plurality of source code paths, the circuit description includes a pipeline including a plurality of code paths, the plurality of code paths having the same number of 15. The at least one computer storage medium of claim 14, wherein one or more pipeline stages are added to one or more of the plurality of code paths to have pipeline stages .

Adding pipeline stages to one or more of the plurality of code paths comprises: determining the number of pipeline stages in the longest code path; adding a number of pipeline stages to each code path equal to the number of pipeline stages in the longest code path minus the number of pipeline stages.

16. At least one computer storage medium according to claim 15, wherein a thread comprises a set of local thread variables provided to a first of said pipelines for execution.

16. At least one computer as recited in claim 15, wherein a first of said pipelines comprises stages that are executed in order, and wherein by passing through said stages in said order, multiple threads maintain execution order. storage medium.

The pipeline includes a first pipeline, the circuit description includes a second pipeline, and a thread executing the first pipeline initiates execution by pushing local variables into a first-in-first-out queue. 16. At least as recited in claim 15, passing to a second pipeline, which maintains thread execution order throughout the pipeline by reading local variables from a first-in-first-out queue in the order they were pushed. A computer storage medium.