JP4390211B2 - Custom LSI development platform, instruction set architecture, logic circuit configuration information generation method, and program - Google Patents

Description

  The present invention relates to a technology for designing, developing, and manufacturing a custom LSI for a specific application, and in particular, an application program written in a high-level language and an instruction set architecture (hereinafter referred to as ISA). The present invention relates to a technique for generating a series of logic circuit configuration information of a processor that executes an application program. The present invention also relates to a custom LSI development platform technology that makes it possible to design, develop, and manufacture a custom LSI for a specific application in a short time by applying the generated ISA and logic circuit configuration information to a dynamically reconfigurable processor.

  In the field of using custom LSIs including application specific integrated circuits (ASICs), a field in which the configuration of the logic circuit inside the processor can be freely changed in order to shorten specification changes and product development periods. Programmable logic circuits such as a programmable gate array (FPGA) and a programmable logic device (PLD) are widely used.

  However, since the logic circuit configuration required for a custom LSI has become complicated and the scale has increased, there is a problem that a large number of arithmetic logic units (ALU) must be incorporated into an FPGA or PLD. .

  A logic reconfigurable processor that dynamically reconfigures a logic circuit of a processor, paying attention to the fact that not all logic circuits with increased scales are always operating, for example, the following patent document 1 and proposed in Patent Document 2.

  When designing and developing a custom LSI system, the functional division of how much is realized by hardware and how much is realized by software is a big problem. If all of the applications can be realized by hardware, it is possible to realize operation speed and low power consumption. However, 1) chip manufacturing cost, 2) design period, 3) securing of hardware designers, etc. related to design / development increase.

  On the other hand, if all are realized by software operating on a general-purpose processor, it is difficult to satisfy the required system performance, but there is an advantage that design and development costs can be reduced.

As a challenge for software developers to develop custom LSIs, hardware description languages (HDL) that are not familiar to software developers such as “Verilog-HDL” and “VHDL” are used to describe the specifications of custom LSIs. There is a problem that it must be used. Since such HDL code has a large amount of description, it takes a long time to create, and it also takes a long time to compile and simulate.

  In studying algorithms to be mounted on LSI, a high-level language with a high degree of abstraction such as C language or a modeling tool is often used. However, in order to create a logic circuit using an algorithm created in a high-level language, it is necessary to rewrite the studied algorithm in HDL, which has a problem that it takes a lot of time. Moreover, once the logic circuit configuration is described in HDL, there is a problem that it is difficult to change the algorithm.

In addition, it is a great barrier for software developers to consider hardware-specific restrictions in the behavioral synthesis stage.
JP 2003-198362 A JP 2003-029969 A

  Therefore, the problem of the present invention is that if a software developer creates an application program in a high-level description language such as C language, the ISA and logic circuit configuration information are automatically generated based on the application program, and the generated ISA and An object of the present invention is to provide a custom LSI development platform in which logic circuit configuration information is automatically reflected in a reconfigurable processor, and thereby a reconfigurable processor manufactured semi-generally can be created as a custom LSI.

  Another object of the present invention is to provide a software program that generates ISA and logic circuit configuration information from an application program created in a high-level description language, for example, C language, and the generated ISA and logic circuit configuration information. It is to provide a reconfigurable processor that is automatically reflected.

  Another object of the present invention is to provide a program for generating ISA and logic circuit configuration information from an application program created in a high-level description language such as C language.

(1) The present invention includes converting means for converting the source over scan program in the program object code and logic circuitry object code, the program object code and logic circuits for each step on the basis of the logic circuitry object code a custom LSI development platform that includes a dynamically reconfigurable processor including means for re-setting the configuration, the dynamically reconfigurable processors have a controller and reconfigurable logic circuit for performing overall management And the controller determines whether the instruction of the program object code is an instruction using the reconfigurable logic circuit, and the instruction of the program object code is an instruction using the reconfigurable logic circuit. A configuration to the reconfigurable logic circuit When the data is loaded and the reconfigurable logic circuit determines the logic circuit configuration, the reconfigurable logic circuit processes the input data. The converting means includes an ISA generator, a logic circuit configuration generator, a compiler, and an assembler. And the ISA generator compares the extracted instruction pattern with the custom instruction pattern stored in the library, and extracts the instruction pattern of the source program and the custom instruction pattern stored in the library. Means for generating intermediate code by replacing with instructions and / or combinations of custom instructions, and generating an instruction set architecture comprising custom instructions and logic element connection information , wherein the logic circuit configuration generator comprises: , Logic element connection information and logic circuit of the dynamically reconfigurable processor Means for generating logic circuit configuration information of the dynamically reconfigurable processor from arrangement arrangement information of programmable elements to be configured, and the compiler compiles the intermediate code and the custom instruction and converts them into assembler code The assembler uses the assembler code as a program / object code, and converts the logic circuit configuration information into a logic circuit configuration / object code .

(2) It is preferable that the intermediate code includes a function call for calling a custom instruction stored in the library and a control instruction for the processor .

(3) Preferably, the dynamically reconfigurable processor includes means for simulating performance of executing the source program based on the program object code and the logic circuit reconfiguration / object code .

(4) When an instruction that has not been replaced with a custom instruction can be synthesized with an existing custom instruction, it is preferable to provide means for defining a new custom instruction pattern and updating the custom instruction in the library .

(5) The present invention provides a conversion means for converting a source program into a program / object code and a logic circuit configuration / object code, and a logic circuit for each step based on the program / object code and the logic circuit configuration / object code. A custom LSI development platform comprising a dynamically reconfigurable processor including means for resetting the configuration, wherein the dynamic reconfigurable processor has a controller for overall management and a reconfigurable logic circuit. And the controller determines whether the instruction of the program object code is an instruction using the reconfigurable logic circuit, and the instruction of the program object code is an instruction using the reconfigurable logic circuit. A configuration to the reconfigurable logic circuit When the data is loaded and the logic circuit configuration is determined, the reconfigurable logic circuit performs processing on the input data, and the conversion means includes an ISA generator and an object code generating means. The ISA generator compares the extracted instruction pattern with a custom instruction pattern stored in a library by means for extracting the instruction pattern of the source program, and compares the extracted instruction with the custom instruction, And / or means for generating an intermediate code by replacing with a combination of custom instructions and generating an instruction set architecture comprising the custom instructions and logic element connection information, and means for generating the object code , Program object code from the intermediate code and the custom instruction Form, and generates a logic circuitry object code from the arrangement sequence information of the programmable elements constituting a logic circuit of the logic element connection information and the dynamically reconfigurable processors.

(6) The present invention provides a conversion means for converting a source program into a program / object code and a logic circuit configuration / object code, and a logic circuit for each step based on the program / object code and the logic circuit configuration / object code. A custom LSI development platform comprising a dynamically reconfigurable processor including means for resetting the configuration, wherein the dynamic reconfigurable processor has a controller for overall management and a reconfigurable logic circuit. And the controller determines whether the instruction of the program object code is an instruction using the reconfigurable logic circuit, and the instruction of the program object code is an instruction using the reconfigurable logic circuit. A configuration to the reconfigurable logic circuit When the data is loaded and the logic circuit configuration is determined, the reconfigurable logic circuit performs processing on the input data, and the conversion means includes an ISA generator and an object code generating means. The ISA generator analyzes the instruction structure of the source program and extracts a process having a data dependency relationship, a process having the extracted data dependency relationship, and a pattern of custom instructions stored in a library, Means for synthesizing a plurality of processes having data dependencies and replacing with a custom instruction to generate an intermediate code, and generating an instruction set architecture comprising the custom instruction and logic element connection information; And the means for generating the object code is programmed from the intermediate code and the custom instruction. It generates a beam object code, and generates a logic circuitry object code from the arrangement sequence information of the programmable elements constituting a logic circuit of the logic element connection information and the dynamically reconfigurable processors.

(7) The present invention provides a program / object code and a logic circuit configuration / object code used for executing a source program in a dynamically reconfigurable processor including means for resetting a logic circuit configuration for each step. A custom LSI development platform having conversion means for converting into a dynamic LSI, wherein the dynamically reconfigurable processor includes a controller that performs overall management and a reconfigurable logic circuit, and the controller includes the program object code If the instruction of the program object code is an instruction using the reconfigurable logic circuit, it is determined whether the instruction of the program object code is an instruction using the reconfigurable logic circuit. The data is loaded and the reconfigurable logic circuit is Is determined, the input data is processed, and the conversion means includes an ISA generator, a compiler, a logic circuit configuration generator, and an assembler, and the ISA generator extracts an instruction pattern of the source program. And the extracted instruction pattern and the custom instruction pattern stored in the library are compared, and the extracted instruction is replaced with the custom instruction and / or a combination of custom instructions to generate an intermediate code. And means for generating an instruction set architecture comprising custom instructions and logic element connection information, wherein the compiler compiles the intermediate code and the custom instructions and converts them into assembler code, The circuit configuration generator includes the logic element connection information and the previous Means for generating logic circuit configuration information of the dynamically reconfigurable processor from arrangement arrangement information of programmable elements constituting the logic circuit of the dynamically reconfigurable processor, wherein the assembler programs the assembler code; An object code is used, and the logic circuit configuration information is converted into a logic circuit configuration / object code .

(8) The present invention relates to a program used to execute a dynamically reconfigurable processor including means for converting a source program and resetting a logic circuit configuration for each step in a custom LSI development platform. A generation method for generating an object code , wherein the dynamically reconfigurable processor includes a controller that performs overall management and a reconfigurable logic circuit, and the controller includes instructions for the program object code to be reconfigured. Determining whether or not the instruction uses a reconfigurable logic circuit, and if the instruction of the program object code is an instruction using the reconfigurable logic circuit, load configuration data into the reconfigurable logic circuit; The reconfigurable logic circuit outputs input data when the logic circuit configuration is determined. Are those to perform processing, the custom LSI development platform, which comprises converting means having ISA generator and logic circuitry generator and compiler and assembler, the means for ISA generator comprises, in the source program The step of extracting an instruction pattern and the means provided in the ISA generator compare the extracted instruction pattern with a custom instruction pattern stored in a library, and use the extracted instruction as the custom instruction and / or Or generating an intermediate code by replacing with a combination of custom instructions and generating an instruction set architecture comprising custom instructions and logic element connection information; and means provided in the logic circuit configuration generator includes the logic element connection Information and said dynamic The logic circuit configuration information of the dynamically reconfigurable processor is generated from the arrangement / arrangement information of the programmable elements constituting the logic circuit of the configurable processor, and the compiler compiles the intermediate code and the custom instruction to assembler code And the assembler uses the assembler code as the program object code and converts the logic circuit configuration information into a logic circuit configuration / object code, whereby the program object code and the logic circuit configuration / The method includes generating an object code .

(9) said means provided in the ISA generator, wherein when the custom instruction has not been extracted as an instruction can be combined into an existing custom instruction is defined as a pattern of a new custom instruction, the custom instruction in said library Preferably includes a step of updating .

( 10 ) The present invention relates to a program, object code, and logic circuit configuration, used for executing a computer in a dynamically reconfigurable processor including means for resetting a logic circuit configuration for each step. A program for functioning as a conversion means for converting into object code , wherein the dynamically reconfigurable processor includes a controller that performs overall management and a reconfigurable logic circuit, and the controller includes the program object It is determined whether the instruction of the code is an instruction using the reconfigurable logic circuit, and when the instruction of the program object code is an instruction using the reconfigurable logic circuit, the reconfigurable logic circuit is configured. Load reconfiguration data and the reconfigurable logic circuit When the circuit arrangement is fixed, which processing is performed on input data, said conversion means, and a ISA generator and compiler and logic circuitry generator and assembler, the ISA generator, before Kiso Supurogura arm means for extracting a pattern of instructions, compares the pattern of the custom instruction stored in the pattern and library instruction that the extracted, replacing the instruction that the extraction with the combination of the custom instruction, and / or custom instructions Generating an intermediate code and generating an instruction set architecture including custom instructions and logic element connection information, and the compiler compiles the intermediate codes and the custom instructions and converts them into assembler code. And the logic circuit configuration generator includes the logic element connection information. Means for generating logic circuit configuration information of the dynamically reconfigurable processor from information and arrangement information of programmable elements constituting the logic circuit of the dynamically reconfigurable processor, and the assembler includes the assembler The code is a program / object code, and the logic circuit configuration information is converted into a logic circuit configuration / object code .

  According to the present invention, a software developer can develop an application (computer program) without being conscious of the part related to the characteristics of hardware. As a result, the total number of execution cycles required for development can be reduced, and an LSI specialized for a desired application can be developed in a short time.

  In addition, assets for developing custom LSIs can be shared (platformed), and design and development assets can be standardized.

[Definition of terms]
In this specification, a dynamic logic circuit reconfigurable processor refers to a processor having a function of performing processing while dynamically reconfiguring a logic circuit in the processor according to an instruction.

  The custom LSI refers to an LSI including an application specific integrated circuit (ASIC) designed and manufactured according to needs.

  A custom instruction is an instruction executed by a processor and defined by a user.

  The instruction set is also called an instruction set (IS) and is a set of custom instructions provided in the processor.

  The instruction set architecture (ISA) includes an instruction set and logic element connection information necessary for generating logic circuit configuration information of the processor.

  The logic element connection information is, for example, information in which information such as an OR circuit is next to an AND circuit and then an XOR circuit is defined. Therefore, information on where to place the AND circuit, where to place the OR circuit or XOR circuit, and which wiring to connect them is not included on the logic circuit of the reconfigurable processor.

  A custom logic circuit refers to a logic circuit that implements a custom instruction, and is a circuit or function that cannot be implemented or cannot be implemented on a general-purpose processor for performance reasons.

  A platform is a system composed of common hardware (reconfigurable processor) and software programs that can be used to implement different custom logic circuits.

  A data path is a logic circuit of a processor that executes a custom instruction.

  A programmable element is an element that constitutes a logic circuit such as an AND circuit, an OR circuit, an XOR circuit, or an ALU.

  FIG. 1 is a block diagram showing the overall configuration of a custom LSI development platform 1 according to the present invention. The custom LSI development platform 1 includes a reconfigurable processor 20 and a software program 10.

  The software program 10 is a logic circuit for dynamically changing the ISA of the reconfigurable processor 20 and the reconfigurable logic circuit 24 (reconfigurable data path) in the reconfigurable processor 20 for each custom instruction. It consists of a series of programs that generate configuration information and the like.

  When the software developer describes the source program 100 in the C language, the ISA generator 110 generates the intermediate code 111 and the ISA 112, and compiles them to thereby generate the program object code 141 and the logic circuit configuration / object code 142. And generate

  Based on the program / object code 141 and the logic circuit configuration / object code 142, the reconfigurable processor 20 operates the input data 27 while changing the reconfigurable logic circuit 24 for each custom instruction, and obtains a final result. As a result, data 28 is output.

  FIG. 2 shows a detailed block diagram of the software program 10. When the C source program 100 is given, the ISA generator 110 is activated and analyzes the instruction structure of the C source program 100. The library 160 stores a plurality of custom instructions defined in advance.

  The ISA generator 110 extracts the pattern of instructions used in the C source program 100 or the pattern of instructions used repeatedly, compares it with the pattern of custom instructions in the library 160, and stores the pattern in the C source program 100. The instructions are replaced with custom instructions to generate intermediate code 111 and ISA 112.

  The intermediate code 111 is composed of a function call of a custom instruction and a control instruction, and the ISA 112 is composed of a custom instruction and logic element connection information.

  The intermediate code 111 is compiled into an assembler code 121 by the compiler 120, and then becomes a program object code 141 by the assembler 140. The compiler 120 compiles the intermediate code 111 and a custom instruction of the ISA 112, for example, a custom instruction in which multiplication is defined by “x” into the assembler code 121.

  The custom instruction of the ISA 112 is converted into the assembler code 121 together with the intermediate code 111 by the compiler 120 and then becomes the program object code 141 by the assembler 140.

  The logic circuit configuration generator 130 generates logic circuit configuration information 1311 from the logic element connection information of the ISA 112 and the arrangement / arrangement information 1310 of the programmable elements (PE) of the reconfigurable logic circuit 24, and this is generated by the assembler 140. The logic circuit configuration / object code 142 is converted.

  FIG. 3 shows a detailed block diagram of the ISA generator 110. The patterning module 1110 shown in FIG. 3 extracts an instruction used in the C source program 100 or an instruction used repeatedly while referring to the library 160 and stores the extracted instruction pattern and the library 160 in the library 160. Is compared with the pattern of the custom instruction being used, and the matching instruction is replaced with the custom instruction.

  Miscellaneous instructions that were not extracted as custom instructions by the patterning module 1110 (not previously prepared as custom instructions) can be newly defined and created by the creator 150 or can be synthesized into existing custom instructions. Synthesize and define as a new custom instruction. The custom instructions in the library 160 are constantly updated by adding and synthesizing custom instructions.

  The patterning module 1110 replaces instructions in the C source program with custom instructions until the entire C source program is executable. The patterning module 1110 refers to logic element connection information (stored in the library 160 in association with a custom instruction) and PE arrangement array information, and can be reconfigured for each custom instruction. 24 pieces of logic circuit configuration information are generated.

  FIG. 4 is a block diagram of the reconfigurable processor 20 according to the embodiment of the present invention. The dynamically reconfigurable processor 20 includes a reconfigurable data path (reconfigurable logic circuit) 24 and executes a program by order control. The reconfigurable processor 20 executes the processing contents of the C source program 100 while resetting the logic circuit configuration for each step. Note that a step is a period required to execute one instruction, which is a combination of setting of a logic circuit configuration and execution of an operation. The logic circuit configuration information is configuration information of a reconfigurable logic circuit for executing a custom instruction.

  The reconfigurable processor 20 includes a controller 21, a stack 22, a configuration memory 23, a reconfigurable data path 24, a register file 25, and a memory 26.

  The controller 21 performs overall management of the reconfigurable processor 20 such as loading configuration data and loading data in the memory 26. There are seven 22-bit index registers 211 inside, and the memory 26 can be accessed using the values in the index registers 211. Further, it is connected to the stack 22 that stores the value in the index register 211.

  The memory 26 is a storage device that holds instructions of the reconfigurable processor 20.

  FIG. 5 is a diagram showing a configuration of an instruction format held in the memory 26. As shown in FIG.

In FIG. 5, in the Exe_Non column, when an instruction is operated by the reconfigurable data path 24, or only the value in the index register 211 is manipulated without using the reconfigurable data path 24. Which of these is to be selected.

  In the case of an instruction that performs an operation in the reconfigurable data path 24, an address of the configuration memory 23 in which appropriate configuration data is stored and a register file 25 used for the operation are specified. In the case of an instruction for manipulating a value in the index register 211, an operation content and an index register 211 used for the operation are designated.

  For example, if a memory address is designated in the Dt_Adr column, data can be exchanged between the memory 26 and the index register 211.

In the Flow_Code column, the execution order control of the program can be specified. If the branch condition is specified here, the processing can be branched using the operation result in the reconfigurable data path 24. is there.

  Dt_Adr is used to specify an absolute address, and the Rel_Adr column is used to specify a relative address.

Work_Rate can be used to designate the number of clock cycles when performing processing in the reconfigurable data path 24 as 1, 2, 4, 8 clock cycles depending on the processing content.

  The configuration memory 23 is a memory that stores configuration data. Up to 128 custom instruction configurations can be retained.

  The register file 25 is a register that stores an operation result in each PE of the reconfigurable data path 24 and passes it to a different function. One word is 256 bits wide. The register file 25 is connected to the PE of the reconfigurable data path 24, and the bit position in the register file 25 to be stored is determined by the position of the PE from which data is output.

  FIG. 6 shows an embodiment of the configuration of the reconfigurable data path 24. In the reconfigurable data path 24, PEs are arranged in 16 rows and 8 columns. PE has 6 inputs and 2 outputs, and an arbitrary logical function can be assigned to the inputs. Each PE is connected by a vertical line (VL) and a horizontal line (HL).

  A VL is connected to each PE in a row, and each VL is connected by HL. The switch (SW) controls the signal transfer from VL to HL or from HL to VL. There are 8 VLs with a 64-bit width, and 7 HLs with a 64-bit width. Also, 64-bit data can be loaded from the memory to the configurable data path 24 at a time.

  In the reconfigurable processor 20, first, the controller 21 reads a program from the memory 26, and determines whether the instruction uses the reconfigurable data path 24 or the instruction operates only on the value in the index register 211. .

  When using the reconfigurable data path 24, the controller 21 reads the appropriate configuration data from the address of the configuration memory 23 specified in the program, and this data is transferred to the reconfigurable data path 24. Load it.

  When the configuration (logic circuit configuration) is determined, the reconfigurable data path 24 processes the input data. The operation result executed by each PE is output to VL and can be written to the register file 25. Data can be passed to another function for use as an intermediate result. By using the register file 25, a large process can be divided into a plurality of functions and executed.

  When using the value in the index register 211, since an arithmetic circuit is prepared in the index register 211, an operation designated in the program is performed by the arithmetic circuit, and the process proceeds to the next instruction.

  An AES (Advanced Encryption Standard) encryption custom LSI has been developed using the software program 10 and the reconfigurable processor 20 according to an embodiment of the present invention.

  AES is selected as a standard encryption method to replace DES (Data Encryption Standard). An ISA was generated from an AES program created in C language, and an AES encryption process was mounted on the reconfigurable processor 20 for performance evaluation.

  In AES, the number of bits in plain text and the number of bits in the key can be selected. In this embodiment, both are set to 128 bits.

  FIG. 7 shows the flow of AES encryption processing. First, a two-dimensional array data format plaintext called State is arranged. A round key is generated (S1), and exclusive OR is performed between State and the round key (S2). Execute the round function a specified number of times. In this example, the test was performed nine times under the following conditions. The round function is executed by the following four transformations. First, so-called s-box conversion processing (byte-sub) of 8-bit input and 8-bit output is executed (S3).

  Next, a shift row (Shift-Row) for performing a periodic shift in units of bytes on the row is executed (S4). Next, a mix column (Mix-Column), which is the execution of matrix operation for each column, is performed (S5). Then, exclusive logic (Add-Round-key) is executed with the State and the round key (S6). Steps S3 to S6 are repeated 9 times.

  Finally, byte-sub (S7), shift-row (S8), round key processing (Add-Round-Key) (S9) is executed, and the encrypted text (Encrypted) Is obtained (S10).

    There are four main encryption processes: Byte-sub, Shift-Row, Mix-Column, and Round-Key processing (Add-Round-Key). It is a conversion process. In realizing these four conversion processes, a custom instruction for realizing each conversion process was created.

  In this embodiment, Byte-Sub is 32 bits, Shift-Row is 128 bits, Mix-Column is 64 bits, and round key processing (Add-Round- Key) is implemented by processing in units of 128 bits. For this reason, instructions for splitting and combining data before and after them have also been added.

  8 and 9 are described in C language including Byte-sub, Shift-Row, Mix-Column, and Round-Key processing (Add-Round-Key). It is an example of description of the intermediate code 111 of the encryption process of AES.

  As shown in FIGS. 8 and 9, the main routine of AES encryption is the “Encrypt” function. In the intermediate code in FIG. 8, the custom instruction is a portion having “vu1_” at the head.

  As a result, 309 cycles were obtained for the entire processing, and 79 cycles were obtained for the encryption processing portion.

  DES is an encryption standard standardized by the US Bureau of Commerce Standards Bureau. In common key cryptography that uses the same key for encryption and decryption, 64 bits of plaintext and 56 bits of key are input to output 64 bits of ciphertext.

  In the DES encryption process, a 64-bit bit string is first input, and initial transposition is performed based on the transposition table. The transposed bit string is divided by 32 bits. The divided bit strings are encrypted with the key and the encryption function F, respectively. The key uses a 48-bit round key generated from the input 56-bit key.

  This process is performed 16 times, and the created left and right bit strings are combined to perform final transposition, and the result is output as ciphertext.

  FIG. 10 shows a flowchart of the DES encryption process. The DES encryption processing on the dynamic logic circuit reconfigurable processor 20 required six custom instructions.

  Table 1 shows the custom instructions used for DES encryption processing and their contents.

    First, 56 bits of the key is input from the memory to the reconfigurable data path 24 by the instruction 0 and transposed at the same time. Similarly, the plaintext 64 bits are input by the instruction 1 and the initial transposition is performed at the same time. Next, depending on the number of rounds, the key is cyclically shifted by the instruction 2 or the instruction 3. Command 4 performs key contraction transposition and encryption F function with one command.

  All data exchange between instructions is performed via the register file 25. Repeat this round 16 times. In FIG. 10, the iteration is a conditional branch process, but in this embodiment, the iteration is expanded and the sequential processing is performed. This is because it is necessary to create an extra circuit for determining the number of rounds for execution by conditional branch processing, and to reduce the circuit scale to be designed. Finally, the reverse transposition of the initial transposition is performed to output 64 bits of ciphertext to the memory.

  Table 2 shows the operating frequency and throughput when the reconfigurable processor 20 performs DES encryption processing.

The operating frequency of the DES encryption process in this example was 6.25MH _Z. As a comparison target, Table 2 also shows the results when DES encryption processing is performed on Intel Pentium (registered trademark) 4. Implementation of the DES encryption processing on the Intel Pentium (registered trademark) 4 was performed by compiling a DES encryption processing specification faithfully written in C language. -O2 was used as a compile option.

  From Table 2, the DES encryption processing on the reconfigurable processor 20 showed 3.8 times higher performance than the DES encryption processing on the Intel Pentium® 4. This is because the PE, which is a component of the dynamically reconfigurable processor 20, can make use of the characteristic that an arbitrary logical function can be assigned to the input in units of 1 bit in the DES encryption processing. is there.

  In the DES encryption process, transposition and substitution in units of 1 bit are repeated. In a 32-bit microprocessor such as Intel Pentium (registered trademark) 4, when processing is performed in units of 1 bit, processing for extracting 1 bit is required. The PE of the dynamically reconfigurable processor 20 fetches data from the register file 25 to the reconfigurable data path 24, moves it to a specified bit position and transfers it again to the register file 25 in the 1-bit transposition processing. Store. This makes it possible to transpose a large amount of data with a single instruction.

  In addition, since any logical function can be assigned to the input in PE, it is possible to reduce the number of execution clock cycles by synthesizing multiple data-dependent processes and executing them with a single instruction. Met. In the DES encryption processing on the reconfigurable data path 24, the number of clock cycles required for encryption of 64-bit plaintext was 70 cycles.

  The present invention can be used as a platform when designing and developing a custom LSI. Further, it can be used for manufacturing custom LSIs specialized for applications, and has industrial applicability.

1 is an overall configuration block diagram of a custom LSI development platform 1 of the present invention. FIG. 1 shows a detailed block diagram of a software program 10. FIG. A detailed block diagram of the ISA generator 110 is shown. 1 is a block diagram of a reconfigurable processor 20 according to an embodiment of the present invention. It is the figure which showed the structure of the instruction format. An embodiment of the configuration of the reconfigurable data path 24 is shown. It is the figure which showed the flow of the process of AES encryption. It is an example of description of the intermediate code of the encryption process of AES. It is an example of description of the intermediate code of the encryption process of AES. 6 is a flowchart of DES encryption processing.

Explanation of symbols

1 Custom LSI development platform
10 Software programs
20 Reconfigurable processors
21 Controller 22 Stack 23 Configuration Memory 24 Reconfigurable Logic Circuit (Reconfigurable Data Path)
25 Register file 26 Memory 100 C source program
110 ISA Generator 111 Intermediate Code 112 Instruction Set Architecture (ISA)
130 Logic Circuit Configuration Generator 131 Logic Circuit Configuration Information 141 Program Object Code 142 Logic Circuit Configuration Object Code 160 Library

Claims (10)

Means for performing conversion means, the resetting of logic circuitry for each step on the basis of the program object code and the logic circuitry object code that converts source over scan program in the program object code and logic circuitry object code A custom LSI development platform with a dynamically reconfigurable processor including
The dynamically reconfigurable processor has a controller that performs overall management and a reconfigurable logic circuit;
The controller determines whether the instruction of the program object code is an instruction that uses the reconfigurable logic circuit, and when the instruction of the program object code is an instruction that uses the reconfigurable logic circuit, Load configuration data into the reconfigurable logic circuit;
The reconfigurable logic circuit performs processing on input data when the logic circuit configuration is determined,
The converting means includes an ISA generator, a logic circuit configuration generator, a compiler, and an assembler.
The ISA generator
Means for extracting a pattern of instructions of the source program;
Comparing the extracted instruction pattern with a custom instruction pattern stored in a library, replacing the extracted instruction with the custom instruction and / or a combination of custom instructions to generate intermediate code; and Generating an instruction set architecture comprising custom instructions and logic element connection information ;
The logic circuit configuration generator generates logic circuit configuration information of the dynamically reconfigurable processor from the logic element connection information and arrangement / arrangement information of programmable elements that configure the logic circuit of the dynamically reconfigurable processor. Having means,
The compiler compiles the intermediate code and the custom instruction into an assembler code,
The custom LSI development platform , wherein the assembler uses the assembler code as a program / object code and converts the logic circuit configuration information into a logic circuit configuration / object code . The intermediate code, and function calls that call custom instructions stored in the library, including the control commands of the processor
Custom LSI development platform according to 請 Motomeko 1. Wherein said program object code based on the logic circuit reconfiguration object code, according to claim 1 wherein the dynamically reconfigurable processor, comprising the means for simulating the performance of executing the source program or 2. Custom LSI development platform described in 2 . The ISA generator
If the instruction has not been replaced previously asked custom instruction can be combined into an existing custom instruction, that defines as a pattern of a new custom instruction, comprising means for updating the custom instruction in said library The custom LSI development platform according to claim 1, wherein the platform is a custom LSI development platform. Means for performing a converting means, the resetting of logic circuitry for each step on the basis of the program object code and the logic circuitry object code that converts source over scan program in the program object code and logic circuitry object code A custom LSI development platform with a dynamically reconfigurable processor including
The dynamically reconfigurable processor has a controller that performs overall management and a reconfigurable logic circuit;
The controller determines whether the instruction of the program object code is an instruction that uses the reconfigurable logic circuit, and when the instruction of the program object code is an instruction that uses the reconfigurable logic circuit, Load configuration data into the reconfigurable logic circuit;
The reconfigurable logic circuit performs processing on input data when the logic circuit configuration is determined,
The converting means includes an ISA generator and means for generating an object code,
The ISA generator
Means for extracting a pattern of instructions of the source program;
Comparing the extracted instruction pattern with a custom instruction pattern stored in a library, replacing the extracted instruction with the custom instruction and / or a combination of custom instructions to generate intermediate code; and Generating an instruction set architecture comprising custom instructions and logic element connection information ;
The means for generating the object code generates a program object code from the intermediate code and the custom instruction, and an arrangement array of programmable elements constituting the logic element connection information and the logic circuit of the dynamically reconfigurable processor A custom LSI development platform characterized by generating logic circuit configuration and object code from information . Means for performing a converting means, the resetting of logic circuitry for each step on the basis of the program object code and the logic circuitry object code that converts source over scan program in the program object code and logic circuitry object code A custom LSI development platform with a dynamically reconfigurable processor including
The dynamically reconfigurable processor has a controller that performs overall management and a reconfigurable logic circuit;
The controller determines whether the instruction of the program object code is an instruction that uses the reconfigurable logic circuit, and when the instruction of the program object code is an instruction that uses the reconfigurable logic circuit, Load configuration data into the reconfigurable logic circuit;
The reconfigurable logic circuit performs processing on input data when the logic circuit configuration is determined,
The converting means includes an ISA generator and means for generating an object code,
The ISA generator
It analyzes the command structure of the source program, means for extracting the processing that data dependencies,
Comparing the pattern of custom instructions stored in the processing and libraries of the extracted data dependence, it generates an intermediate code and substituting custom instruction by combining a plurality of processes of the data dependence And a means for generating an instruction set architecture comprising custom instructions and logic element connection information ,
The means for generating the object code generates a program object code from the intermediate code and the custom instruction, and an arrangement array of programmable elements constituting the logic element connection information and the logic circuit of the dynamically reconfigurable processor A custom LSI development platform characterized by generating logic circuit configuration and object code from information . Means for performing a converting means, the resetting of logic circuitry for each step on the basis of the program object code and the logic circuitry object code that converts source over scan program in the program object code and logic circuitry object code A custom LSI development platform with a dynamically reconfigurable processor including
The dynamically reconfigurable processor has a controller that performs overall management and a reconfigurable logic circuit;
The controller determines whether the instruction of the program object code is an instruction that uses the reconfigurable logic circuit, and when the instruction of the program object code is an instruction that uses the reconfigurable logic circuit, Load configuration data into the reconfigurable logic circuit;
The reconfigurable logic circuit performs processing on input data when the logic circuit configuration is determined,
The converting means includes an ISA generator, a logic circuit configuration generator, a compiler, and an assembler.
The ISA generator
It analyzes the command structure of the source program, means for extracting the processing that data dependencies,
Comparing the pattern of custom instructions stored in the processing and libraries of the extracted data dependence, it generates an intermediate code and substituting custom instruction by combining a plurality of processes of the data dependence And a means for generating an instruction set architecture comprising custom instructions and logic element connection information ,
The logic circuit configuration generator generates logic circuit configuration information of the dynamically reconfigurable processor from the logic element connection information and arrangement / arrangement information of programmable elements that configure the logic circuit of the dynamically reconfigurable processor. Having means,
The compiler compiles the intermediate code and the custom instruction into an assembler code,
The custom LSI development platform , wherein the assembler uses the assembler code as a program / object code and converts the logic circuit configuration information into a logic circuit configuration / object code . Generating method for generating a program / object code used in a dynamically reconfigurable processor including means for converting a source program and resetting a logic circuit configuration for each step in a custom LSI development platform Because
The dynamically reconfigurable processor has a controller that performs overall management and a reconfigurable logic circuit;
The controller determines whether the instruction of the program object code is an instruction that uses the reconfigurable logic circuit, and when the instruction of the program object code is an instruction that uses the reconfigurable logic circuit, Load configuration data into the reconfigurable logic circuit;
The reconfigurable logic circuit performs processing on input data when the logic circuit configuration is determined,
The custom LSI development platform includes a conversion means having an ISA generator, a compiler, a logic circuit configuration generator, and an assembler.
A step wherein the means provided in the ISA generator, which extracts the patterns of instructions of the source program,
The ISA generator means provided in, compared with the pattern of the custom instruction stored in the pattern and library instruction that the extracted, the custom instruction instruction that the extraction, and / or substituted with a combination of custom instructions Generating intermediate code and generating an instruction set architecture comprising custom instructions and logic element connection information ;
The means included in the logic circuit configuration generator is configured to obtain logic circuit configuration information of the dynamically reconfigurable processor from the logic element connection information and arrangement information of programmable elements constituting the logic circuit of the dynamically reconfigurable processor. Generating and compiling the intermediate code and the custom instructions into assembler code;
The assembler generates the program / object code and the logic circuit configuration / object code by using the assembler code as the program / object code and converting the logic circuit configuration information into a logic circuit configuration / object code.
Generating how to characterized in that it comprises a. When an instruction that is not extracted as the custom instruction can be synthesized into an existing custom instruction, the means included in the ISA generator defines a new custom instruction pattern and updates the custom instruction in the library. Including steps
The generation method according to claim 8. Conversion means for converting a computer into a program, object code, and logic circuit configuration / object code used to execute a source program in a dynamically reconfigurable processor including means for resetting a logic circuit configuration step by step Is a program for functioning as
The dynamically reconfigurable processor has a controller that performs overall management and a reconfigurable logic circuit;
The controller determines whether the instruction of the program object code is an instruction that uses the reconfigurable logic circuit, and when the instruction of the program object code is an instruction that uses the reconfigurable logic circuit, Load configuration data into the reconfigurable logic circuit;
The reconfigurable logic circuit performs processing on input data when the logic circuit configuration is determined,
The converting means includes an ISA generator, a compiler, a logic circuit configuration generator, and an assembler.
The ISA generator
It means for extracting a pattern of instructions before Kiso Supurogura arm,
Comparing the pattern of the custom instruction stored in the pattern and library instruction that the extracted, the custom instruction instruction that the extraction, and / or substituted with a combination of custom instructions to generate an intermediate code, and, Means for generating an instruction set architecture comprising custom instructions and logic element connection information;
The compiler compiles the intermediate code and the custom instruction into an assembler code,
The logic circuit configuration generator generates logic circuit configuration information of the dynamically reconfigurable processor from the logic element connection information and arrangement / arrangement information of programmable elements that configure the logic circuit of the dynamically reconfigurable processor. Having means,
The assembler uses the assembler code as a program / object code and converts the logic circuit configuration information into a logic circuit configuration / object code.
A program characterized by that .

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