JP2793342B2 - Arithmetic processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to an arithmetic processing device provided with a plurality of pipeline processing mechanisms that can operate in parallel.

(Prior Art) In recent years, there are provided n (n is an integer of 2 or more) pipeline processing mechanisms for processing instructions, and the n pipeline processing mechanisms are used to convert instructions from an instruction stream of one load module into n. Arithmetic processing units that execute the programs one by one in parallel have been developed. This type of arithmetic processing device (parallel arithmetic processing device) can execute n instructions in one cycle, and thus can achieve high processing performance.

The arithmetic processing unit requires a condition code register used to hold a code (condition code) representing a condition for conditional branching. Conventionally, this condition code register has been realized by allocating a part of a PSW (program status word) register in an arithmetic processing device having the above-mentioned n pipeline processing mechanisms.
That is, there was one condition code register. The setting of the condition code in the condition code register is specified by one of n instructions executed in parallel by the n pipeline processing mechanisms. The conditional branch is processed according to the condition code set in the condition code register.

On the other hand, there is also known an arithmetic processing device which does not have a condition code register but stores a condition code of an operation result in a general-purpose register. In such an arithmetic processing unit, a conditional branch instruction is processed in accordance with a condition code specified in an instruction word or stored in a general-purpose register having a predetermined number.

(Problems to be Solved by the Invention) As described above, in a conventional arithmetic processing device having n (n ≧ 2) pipeline processing mechanisms operable in parallel,
There is only one condition code register, and therefore, the number of instructions for which a condition code can be set is limited to one out of n instructions processed simultaneously. That is, even if n instructions can be executed in parallel and each can generate a condition code, only one can be used as a condition code. Therefore, in order to branch under a plurality of conditions, it is necessary to repeat branching under one condition for each cycle, and there is a problem that n pipeline processing mechanisms cannot be used efficiently.

On the other hand, in a conventional arithmetic processing device in which a condition code is stored in a general-purpose register without having a condition code register, a general-purpose register for storing a condition code is different for each pipeline processing mechanism, whereby n condition codes are stored. Can be set at the same time. However, since the registers referred to by the conditional branch instruction are specified as one in the instruction word or in advance (implicitly), even if a plurality of condition generations can be performed in parallel, the conditions are not changed. In order to perform the branch based on the combined condition, it is necessary to repeat the conditional branch as in the case of the arithmetic processing device having one condition code register described above.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide n (n is an integer of 2 or more) pipeline processing mechanisms for processing instructions, and to provide one pipeline processing mechanism using the n pipeline processing mechanisms. In an arithmetic processing unit that executes n instructions in parallel from an instruction stream, a condition code is generated in parallel by each pipeline processing mechanism, and one composite condition code obtained by combining the generated condition codes is obtained. An object of the present invention is to make it possible to perform condition processing based on a complex condition at high speed by selecting a process according to the complex condition code.

[Configuration of the Invention] (Means for Solving the Problems) A configuration according to a first aspect of the present invention includes n pipeline processing mechanisms (n is an integer of 2 or more) for processing instructions, and the n pipeline processing mechanisms are provided. In an arithmetic processing unit that executes n instructions from one instruction stream in parallel using one pipeline processing mechanism, a condition provided for each pipeline processing mechanism and generated by the corresponding pipeline processing mechanism A condition code register for holding a code, and one of the following complex condition generating means, that is, one of the n pipeline processing mechanisms, which is stored in the condition code register for each of the pipeline processing mechanisms. Includes common specification bit data for specifying a common condition of a logical operation to be performed on each condition code, and combines the above condition codes into one composite condition code. When a conditional branch instruction having a branch condition to execute is executed, each condition code held in the condition code register of each pipeline processing mechanism is included in the branch condition of the conditional branch instruction. A common logical operation corresponding to the common designation bit data is performed, and each condition code after the logical operation is grouped according to other bit data of the branch condition of the conditional branch instruction to form one composite condition code. A composite condition generating means for generating the condition is provided, and the pipeline processing mechanism executing the conditional branch instruction determines whether the branch is taken / not taken according to the compound condition code generated by the compound condition generating means.

According to a second aspect of the present invention, there is provided a configuration according to the first aspect, wherein the conditional branch instruction applied in the configuration according to the first aspect is replaced by a condition code stored in a condition code register for each pipeline processing mechanism. A conditional branch instruction including individually designated bit data for individually designating conditions of a logical operation to be performed on the code, and having a branch condition for generating one composite condition code by combining the condition codes; When the conditional branch instruction is executed by one of the pipeline processing mechanisms, the complex condition generating means performs the above-described processing on each condition code held in the condition code register for each of the pipeline processing mechanisms. Performs an independent logical operation according to the individually specified bit data included in the branch condition of the conditional branch instruction, and replaces each condition code after the logical operation with the condition code. Characterized in that so as generate a single composite condition codes are summarized in accordance with the other bit data of 岐命 old branch condition.

(Operation) According to the present invention, the n pipeline processing mechanisms include:
When an instruction word capable of generating a condition code is fetched and each instruction word is executed in parallel, a condition code is generated by each pipeline processing mechanism. Condition codes generated in parallel by each pipeline processing mechanism are set in corresponding condition code registers. The condition code set in each condition code register is supplied to the complex condition generating means. The complex condition generating means is configured to execute a branch condition set in (a branch condition field of) a conditional branch instruction fetched by any one of the n pipeline processing mechanisms (for example, the first pipeline processing mechanism). A common logical operation (or an independent logical operation) is performed on the condition code set in each of the condition code registers according to the condition specified by the common specified bit data (or the individually specified bit data), and the logical operation after the logical operation is performed. Each condition code is grouped according to other bit data in the branch condition of the conditional branch instruction to generate one composite condition code. Then, the conditional branch instruction is executed by the pipeline processing mechanism in accordance with the composite condition code, so that the conditional processing based on the composite condition is efficiently performed.

(Embodiment) FIG. 1 is a block diagram of an arithmetic processing unit according to an embodiment of the present invention. In the figure, reference numeral 11 denotes an instruction buffer in which an instruction stream prefetched from a main memory (not shown) is stored, and instruction processing for executing n instructions, for example, four instructions in parallel, in the instruction stream stored in the instruction buffer 11 Mechanism. The instruction processing mechanism 12 has four pipeline processing mechanisms (hereinafter, simply referred to as pipelines) 13-1 (#
1), 13-2 (# 2), 13-3 (# 3), 13-4 (# 4)
have. 14-1 to 14-4 are pipelines 13-1 to
Result register (R) for temporarily holding the operation result of 13-4, 15-1 to 15-4 are pipelines 13-1 to 13-4
Is a condition code register for holding the condition code generated in step (1). This condition code includes G bits that are true when the operation result is larger than 0, and L bits that are true when the operation result is smaller than 0. 16 is the result register 14-1
A register file used for storing the operation results of the pipelines 13-1 to 13-4 held in 14-4, and 17 is a condition code held in the condition code registers 15-1 to 15-4. For example, it is a composite condition generation circuit that collects according to a branch condition BC in a conditional branch instruction executed in the pipeline 13-1, and newly generates one condition code (hereinafter, referred to as a composite condition code). The branch instruction is executed in the pipeline 13-1 according to the complex condition code generated by the complex condition generation circuit 17.

FIG. 2 shows a format of a conditional branch instruction capable of specifying a complex condition. The conditional branch instruction shown in FIG. 2 has an instruction code OP for designating a conditional branch instruction, a branch condition BC, and a branch destination address BA for designating a branch destination when the condition is satisfied. ing. The branch condition BC is determined by the bit b0
It consists of 10 bits of ~ b9. b0 is the condition code register 15−
A bit (MG bit) commonly specifying masking (selection) of G bits 1 to 15-4, and b1 commonly specifying masking of L bits of condition code registers 15-1 to 15-4. Each bit is used as a bit (ML bit). b2 is a bit (A / O bit) that commonly specifies an operation (AND or OR operation) to combine the masked G and L bits into one bit for each pipeline, and b3 is a bit for each pipeline by specifying bit b2 These bits are used as bits (N bits) commonly specifying the level inversion of the given bit. b4 to b7 are bits (M1 to M4 bits) for specifying masking of another bit of the pipeline 13-1 to 13-4 processed by the specification of the bit b3, and b8 is each bit after masking for each pipeline (A / O bit) that specifies the operation (AND or OR operation) to combine the data into one bit, b9
Are used as bits (N bits) for designating the level inversion of the bits combined by the designation of the bit b8.

FIG. 3 shows the internal configuration of the complex condition generation circuit 17. Third
The complex condition generation circuit 17 shown in the figure
AND gates 31-1 to 31-4 for masking (selecting) the G bits -1 to 15-4 with bit b0 (MG bit) of the branch condition BC in the conditional branch instruction shown in FIG. 2, and a condition code register AND masking L bits 15-1 to 15-4 with bit b1 (ML bit) of branch condition BC shown in FIG.
It has gates 32-1 to 32-4 and AND / OR circuits 33-1 to 33-4. AND / OR circuits 33-i (i = 1 to 4) are AND gates 31-i and 32-i (corresponding to the pipeline 13-i).
AND or OR operation between the output bits is performed according to the bit b2 (A / O bit) of the branch condition BC shown in FIG. The composite condition generating circuit 17 of FIG.
EXOR gates (exclusive OR gates) 34-1 to 34-4 for inverting output bits -1 to 33-4 in accordance with the bit b3 (N bit) of the branch condition BC shown in FIG. 2, and an EXOR gate 34−
AND gates 35-1 to 35-4 for masking output bits 1 to 34-4 in accordance with bits b4 to b7 (M1 to M4 bits) of the branch condition BC shown in FIG. The complex condition generation circuit 17 of FIG. 3 further performs an AND or OR operation between the output bits of the AND gates 35-1 to 35-4 according to the bit b8 (A / O bit) of the branch condition BC shown in FIG. And an output bit of the AND / OR circuit 36 to be combined into one bit.
It has an EXOR gate 37 that inverts according to the bit b9 (N bits) of the branch condition BC shown in the figure. This EXOR gate 37
Is supplied to the pipeline 13-1 as a complex condition card.

 Next, the operation of the embodiment of the present invention will be described.

First, for example, four comparison instructions capable of generating a condition code from the instruction stream prefetched in the instruction buffer 11 are taken out by the instruction processing unit 12, and each of the comparison instructions is extracted by the instruction processing unit 12.
Inside the pipelines 13-1 to 13-4. As a result, each of the pipelines 13-1 to 13-4 executes the comparison instruction taken into its own pipeline in parallel, and generates a condition code consisting of two bits of G and L according to the comparison result. The condition codes generated by the pipelines 13-1 to 13-4 are held in corresponding condition code registers 15-1 to 15-4, respectively. The condition codes held in the condition code registers 15-1 to 15-4 are supplied to the complex condition generation circuit 17.

The comparison instruction processing in the pipelines 13-1 to 13-4 is performed by pipeline processing including each stage of instruction decoding, operand fetch, operation, and result writing (to the register file 16). When the decode stage of the comparison instruction is completed, four instructions starting with the conditional branch instruction shown in FIG. 2 (here, the following three instructions are assumed to be no operation instructions) are stored in the instruction buffer 11.
To the instruction processing mechanism 12. The first conditional branch instruction is taken into the pipeline 13-1, and the remaining three instructions are respectively assigned to the corresponding pipelines 13-2 to 13-13.
It is taken into 4. From this, each pipeline 13-1 to 13-13
At -4, the operand fetch stage of the comparison instruction is performed, and the decoding stage of the subsequent instruction is performed. Here, the conditional branch instruction processing in the pipeline 13-1 is performed by pipeline processing including an instruction decode, an operand fetch, a branch destination address calculation stage based on the branch destination address BA, and a branch destination instruction fetch stage. Therefore, pipelines 13-1 to 13-4
When the operation stage of the comparison instruction is completed and the condition code generated in the stage is held in the corresponding condition code registers 15-1 to 15-4 as described above, the pipeline 13-1 executes the subsequent conditional branch. The instruction address calculation stage is started.

In the address calculation stage of the conditional branch instruction processing, the calculation of the branch destination address and the generation of a complex condition code using the complex condition generation circuit 17 are performed as described below.
First, in the address calculation stage of the conditional branch instruction processing, the branch condition BC (see FIG. 2) in the conditional branch instruction is supplied from the pipeline 13-1 to the complex condition generation circuit 17. The complex condition generation circuit 17 includes condition code registers 15-1 to 15-15.
-4, that is, each condition code corresponding to the comparison result of the preceding comparison instruction is also supplied. Complex condition generation circuit 17
Performs an operation associated with the branch condition BC provided from the pipeline 13-1 on each condition code held in the condition code registers 15-1 to 15-4 (see FIG. 3). (Here, 1 bit). This composite condition code is supplied to the pipeline 13-1, and the address calculation stage ends.

In the pipeline 13-1, when the address calculation stage of the conditional branch instruction processing ends, the branch destination instruction fetch stage starts. In this branch destination instruction fetch stage,
It is determined whether the branch is taken / not taken according to the complex condition code supplied from the complex condition generating circuit 17, and if the branch is taken, four instructions starting with the branch destination instruction are taken out.
Therefore, according to the present embodiment, for example, A> B and C> D
In addition, the branch processing when a plurality of conditions such as E> F and G> H is satisfied can be executed by one conditional branch.

In the branch condition BC shown in FIG.
The same condition as b3 (common designation bit data) is applied to all condition codes. However, bits b0 to b3, b4 to b7, b8 to b11, b12-b
Pipeline 13 like 15 (individually specified bit data)
Independent condition generation for each condition code (contents held in condition code registers 15-1, 15-2, 15-3, 15-4) generated by -1, 13-2, 13-3, 13-4 Can also be specified. That is, the branch condition BC 'shown in FIG. 4 can be applied to the arithmetic processing unit shown in FIG. 1 instead of the branch condition BC shown in FIG. In this case, it is necessary to use a composite condition generation circuit 17 'having the configuration shown in FIG.

The complex condition generation circuit 17 'in FIG.
Each of the condition codes held in 15-1 to 15-4 is combined into one composite condition code according to the branch condition BC 'shown in FIG. 4, and the condition code registers 15-1, 15-2, 15-3, 15−
4 G bits into the bits b0, b4, b8, b12 in the branch condition BC '
AND gate 51 masks (selects) according to (MG bit)
-1,51-2,51-3,51-4 and condition code register 15-1,
AND gates 52-1, 52-2, 52- that mask the L bits of 15-2, 15-3, 15-4 according to bits b1, b5, b9, b13 (ML bits) in branch condition BC ' 3,52-4. The complex condition generation circuit 17 'also provides a signal between the output bits of the AND gates 51-1 and 52-1, a signal between the output bits of the AND gates 51-2 and 52-2, and a signal between the output bits of the AND gates 51-3 and 52-3. , AND gate 51−4, 52−
AND / OR circuits 53-1 and 53 for performing AND and OR operations between the four output bits according to bits b2, b6, b10 and b14 (A / O bits) in the branch condition BC 'into one bit. −2,53−
3,53-4. The composite condition generation circuit 17 'further includes
An EXOR gate 54-which inverts according to the bits b3, b7, b11, b15 (N bits) in the branch condition BC 'of the output bits of the AND / OR circuits 53-1, 53-2, 53-3, 53-4. 1,54-2,54-3,54-4,
Between the output bits of the EXOR gates 54-1, 54-2, 54-3, 54-4
An AND / OR circuit 55 that performs an AND or OR operation in accordance with the bit b16 (A / O bit) in the branch condition BC 'to combine the result into a 1-bit composite condition code.

The branch condition BC shown in FIG. 2 and the branch condition BC 'shown in FIG.
When the branch condition BC applies the same condition to all the condition codes as the bits b0 to b3, the bits b4 to b4 to select the condition codes to be incorporated in the complex condition code generation
Although b7 (M1 to M4 bits) is required, the total number of constituent bits is smaller than the branch condition BC '. On the other hand, branch condition B
C 'requires a larger number of bits than the branch condition BC in order to specify independent condition generation for each condition code, but allows detailed specification of condition generation.

In the above, the case where there are four pipelines (pipeline processing mechanisms) that can operate in parallel has been described. However, the present invention is applicable to all types of arithmetic processing devices having a plurality of pipelines. Also, the case where the composite condition code is 1 bit has been described, but it is also possible to generate a composite condition code having a plurality of bits and perform multidirectional branching in one branching process.

[Effects of the Invention] As described above in detail, according to the present invention, there are provided n (n ≧ 2) pipeline processing mechanisms for processing instructions.
In an arithmetic processing unit for executing n instructions from one instruction stream in parallel using one pipeline processing mechanism, a condition code is generated in parallel by each pipeline processing mechanism, and a corresponding condition code register is generated. In accordance with the bit data or individually specified bit data in the common specification included in the branch condition in the conditional branch instruction,
Since a common logical operation or an independent logical operation is performed, and each condition code after the logical operation is collectively generated according to other bit data in the branch condition, one composite condition code is generated. By selecting a process according to the complex condition code, the condition process based on the complex condition can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an arithmetic processing unit according to an embodiment of the present invention, FIG. 2 is a format diagram of a conditional branch instruction applied in the embodiment, and FIG. 3 is a complex diagram applied in the embodiment. FIG. 4 is a diagram showing the internal configuration of the condition generating circuit, FIG. 4 is a format diagram showing a modified example of the branch condition in the conditional branch instruction shown in FIG. 2, and FIG. 5 applies a branch condition in the format shown in FIG. FIG. 9 is a diagram illustrating an internal configuration of a complex condition generation circuit in the case. 11: Instruction buffer, 12: Instruction processing mechanism, 13-1 to 13
-4 ... Pipeline (pipeline processing mechanism), 15-
1 to 15-4: condition code register, 16: register file, 17, 17 ': complex condition generation circuit, BC, BC': branch condition.

Claims (2)

(57) [Claims] 1. A pipeline processing mechanism for processing an instruction is represented by n
(N is an integer equal to or greater than 2) in an arithmetic processing device that executes instructions from an instruction stream in parallel by n at a time using the n pipeline processing mechanisms. And a condition code register for holding a condition code generated by a corresponding pipeline processing mechanism; and one of the n pipeline processing mechanisms, wherein the condition code for each of the pipeline processing mechanisms is provided. A branch condition for generating common compound condition codes by combining common condition bit data for specifying common conditions of a logical operation to be performed on each condition code held in a register. When a conditional branch instruction having the following condition is executed, each condition code stored in the condition code register of each pipeline processing mechanism is stored. Performs a common logical operation in accordance with the common designation bit data included in the branch condition of the conditional branch instruction to de,
A complex condition generating means for combining each condition code after the logical operation in accordance with other bit data of the branch condition of the conditional branch instruction to generate one complex condition code, and executing the conditional branch instruction The arithmetic processing device, wherein the pipeline processing mechanism is configured to determine whether a branch is taken / not taken according to a complex condition code generated by the complex condition generating means. 2. A pipeline processing mechanism for processing an instruction is represented by n
(N is an integer equal to or greater than 2) in an arithmetic processing device that executes instructions from an instruction stream in parallel by n at a time using the n pipeline processing mechanisms. And a condition code register for holding a condition code generated by a corresponding pipeline processing mechanism; and a condition code register for each of the pipeline processing mechanisms in one of the n pipeline processing mechanisms. Contains individually designated bit data for individually designating the condition of the logical operation to be performed on each condition code held therein, and includes a branch condition for generating one composite condition code by combining the above condition codes. When the conditional branch instruction having the condition code is executed, each condition code stored in the condition code register for each of the pipeline processing mechanisms is provided. Performs an independent logical operation according to the individually specified bit data included in the branch condition of the conditional branch instruction, and replaces each condition code after the logical operation with another bit of the branch condition of the conditional branch instruction. Compound condition generating means for collectively generating one compound condition code in accordance with data, wherein the pipeline processing mechanism executing the conditional branch instruction includes a compound condition code generated by the compound condition generating means. An arithmetic processing device configured to determine whether a branch is taken / not taken according to the following.