WO2016201699A1

WO2016201699A1 - Instruction processing method and device

Info

Publication number: WO2016201699A1
Application number: PCT/CN2015/081954
Authority: WO
Inventors: 蔡卫光; 顾雄礼; 方磊
Original assignee: 华为技术有限公司
Priority date: 2015-06-19
Filing date: 2015-06-19
Publication date: 2016-12-22
Also published as: CN106537331A; CN106537331B

Abstract

An embodiment of the present invention provides an instruction processing method and device, and relates to the field of computers. The method comprises: determining at least one key instruction in executable instructions, the key instruction being a long-delay instruction or an instruction located in a key instruction chain, the key instruction chain comprising N steps of instructions, wherein, an i-th step instruction of the N steps of instructions is a producer instruction of an i + 1 step instruction. In the producer instruction, a target register of an i-th-step instruction is a source register of an i + 1 step instruction, and an N-th step instruction of the key instruction chain is a long-delay instruction, where N is a positive integer greater than 1, and i is a positive integer greater than 0 but less than N; and prioritizing execution of the at least one key instruction in the executable instructions. The present invention advances an execution time of a long delay instruction, further improving a processing function of a processor.

Description

Instruction processing method and device

Technical field

The present invention relates to the field of computers, and in particular, to an instruction processing method and device.

Background technique

In the computer world, in order for a device to implement a certain function, an application needs to be installed on the device. In order to run the application, the instructions included in the application need to be processed.

At present, the process of the instruction processing may be: the processor included in the device fetches instructions from the instruction cache according to the instruction sequence, and obtains a plurality of instructions, where the order of the instructions is the sequence in which the application sequentially runs the multiple instructions. . The plurality of instructions are decoded, and the decoded plurality of instructions are executed in the order of the instructions. During execution of the decoded plurality of instructions, if a long delay instruction causing a long delay operation is executed, during execution of the long delay instruction, execution may be performed after the long delay instruction and independent of the long delay instruction The instructions are based on the target register numbers of the plurality of instructions, and the execution results of the plurality of instructions are submitted to the corresponding target registers according to the instruction sequence, thereby implementing processing of the plurality of instructions.

During the execution of the instruction of the long delay operation, after all the instructions after the long delay instruction and not related to the long delay instruction are executed, if the long delay instruction has not been executed, the processor still needs to be executed. Waiting for the execution of the long delay instruction is completed before other operations can be processed, reducing the processing performance of the processor.

Summary of the invention

In order to improve the processing performance of the processor, an embodiment of the present invention provides an instruction processing method and device. The technical solution is as follows:

In a first aspect, an instruction processing method is provided, the method comprising:

Determining a key instruction in at least one executable instruction, the key instruction being a long delay instruction or an instruction located on a critical instruction chain, the key instruction chain comprising an Nth order instruction, wherein the ith of the Nth order instructions The order instruction is a producer instruction of the i+1th order instruction, and the producer instruction means that the target register of the i th order instruction is a source register of the i+1th order instruction, and the Nth of the key instruction chain The order instruction is a long delay instruction, N is a positive integer greater than 1, and i is a positive integer greater than 0 and less than N;

The key instructions of the at least one executable instruction are preferentially executed.

In conjunction with the first aspect, in the first possible implementation manner of the foregoing first aspect, before the determining the key instruction in the at least one executable instruction, the method further includes:

Extracting a plurality of to-be-executed instructions from the instruction cache;

From the plurality of to-be-executed instructions, at least one executable instruction is determined.

With reference to the first aspect, in the second possible implementation manner of the foregoing first aspect, the determining the key instruction in the at least one executable instruction includes:

Determining, for any executable instruction of the at least one executable instruction, whether the key instruction identifier of the any executable instruction is valid or whether the any executable instruction is a long delay instruction;

When the critical instruction identification of any of the executable instructions is valid or the any executable instruction is a long delay instruction, it is determined that the any executable instruction is a key instruction.

With reference to the first aspect to the second possible implementation of the first aspect, in a third possible implementation manner of the foregoing first aspect, the method further includes:

When there is a producer instruction in the key instruction, and the producer instruction of the key instruction is not marked as a key instruction, the key instruction identifier of the producer instruction of the key instruction is set to be valid.

In a fourth possible implementation manner of the foregoing first aspect, the method further includes:

When the key instruction identifier of the key instruction is invalid and the key instruction is a long delay instruction, the key instruction identifier of the long delay instruction is set to be valid.

Combining the third possible implementation of the first aspect or the fourth possible implementation of the first aspect In a fifth possible implementation manner of the foregoing first aspect, the method further includes:

The identity of the critical instruction is written into the instruction cache each time a critical instruction identification of an instruction is set to be valid.

With reference to the second possible implementation of the first aspect, in the sixth possible implementation manner of the foregoing first aspect, the determining whether the any executable instruction is a long delay instruction comprises:

Decoding any of the executable instructions to obtain an instruction type of any of the executable instructions;

Determining whether the stored key type library contains the instruction type of any of the executable instructions;

If the key type library contains an instruction type of any of the executable instructions, it is determined that the any executable instruction is a long delay instruction.

In conjunction with the second possible implementation of the first aspect, in the seventh possible implementation manner of the foregoing first aspect, the determining whether the any executable instruction is a long delay instruction comprises:

Determining whether the stored key address library contains the instruction address of any of the executable instructions;

If the key address library contains an instruction address of any of the executable instructions, it is determined that the any executable instruction is a long delay instruction.

With reference to the first aspect to any one of the possible implementations of the seventh possible implementation of the first aspect, in an eighth possible implementation manner of the foregoing first aspect, After executing the instructions, it also includes:

Allocating a storage space for each of the plurality of to-be-executed instructions, where each storage space is used to store an execution result of each of the to-be-executed instructions;

Correspondingly, the method further comprises:

When the execution result of the instruction to be executed is obtained, the execution result of the instruction to be executed is written into the corresponding storage space;

After the execution of the plurality of to-be-executed instructions is ended, in accordance with the instruction sequence of the plurality of instructions, the execution result in the storage space corresponding to each of the plurality of to-be-executed instructions is sequentially written into each of the The target register corresponding to the instruction to be executed.

In a second aspect, a computing device readable medium is provided, comprising: a computing device executing instructions that, when a processor of a computing device executes the computing device to execute an instruction, the computing device performs the first aspect to the first aspect A method as described in any of the possible implementations of the eight possible implementations.

In a third aspect, an instruction processing device is provided, the device comprising: a processor, a memory, a bus, and a communication interface;

The memory is configured to store a computer execution instruction, the processor is coupled to the memory via the bus, and when the data storage device is in operation, the processor executes the computer-executed instruction stored in the memory to The instruction processing device is caused to perform the method of any one of the first aspect to the eighth possible implementation of the first aspect.

In a fourth aspect, an instruction processing device is provided, the device comprising:

Determining a module for determining a key instruction in the at least one executable instruction, the key instruction being a long delay instruction or an instruction located on a key instruction chain, the key instruction chain comprising an Nth order instruction, wherein the Nth order The i-th order instruction in the instruction is a producer instruction of the (i+1)th instruction, and the producer instruction is that the target register of the i-th order instruction is a source register of the (i+1)th instruction, the key instruction The Nth order instruction on the chain is a long delay instruction, N is a positive integer greater than 1, and i is a positive integer greater than 0 and less than N;

And an execution module, configured to preferentially execute the key instruction in the at least one executable instruction.

With reference to the fourth aspect, in a first possible implementation manner of the foregoing fourth aspect, the device further includes an instruction fetching module,

The fetching module is configured to fetch a plurality of to-be-executed instructions from the instruction cache;

The determining module is further configured to determine at least one executable instruction from the plurality of to-be-executed instructions.

With reference to the fourth aspect, in a second possible implementation manner of the foregoing fourth aspect, the determining module is configured to determine a key instruction in the at least one executable instruction, including:

a determining unit, configured to determine, according to any one of the at least one executable instructions, the determining module is configured to determine whether the key instruction identifier of the any executable instruction is valid or whether the any executable instruction is A long delay instruction; when the key instruction identifier of any of the executable instructions is valid or the any executable instruction is a long delay instruction, it is also used to determine that any of the executable instructions is a key instruction.

With reference to any of the possible implementations of the fourth aspect to the second possible implementation of the fourth aspect, in a third possible implementation manner of the foregoing fourth aspect, the device further includes:

a first setting module, configured to set a key instruction identifier of a producer instruction of the key instruction to be valid when a producer instruction is present in the key instruction, and a producer instruction of the key instruction is not marked as a key instruction .

With reference to the third aspect, the third possible implementation manner of the fourth aspect, in the fourth possible implementation manner of the foregoing fourth aspect, the device further includes:

And a second setting module, configured to: when the key instruction identifier of the critical instruction is invalid and the key instruction is a long delay instruction, set a key instruction identifier of the long delay instruction to be valid.

In conjunction with the third possible implementation of the fourth aspect, or the fourth possible implementation of the fourth aspect, in a fifth possible implementation manner of the foregoing fourth aspect, the device further includes:

The first write module is configured to write an identifier of the key instruction into the instruction cache every time a key instruction identifier of an instruction is set to be valid.

In conjunction with the second possible implementation of the fourth aspect, in the sixth possible implementation manner of the foregoing fourth aspect, the determining, the determining, by the determining, the determining, whether the any executable instruction is a long delay instruction, includes:

The determining module is configured to decode any one of the executable instructions to obtain an instruction type of the any executable instruction;

And used to determine whether the stored key type library contains the instruction type of any of the executable instructions;

If the key type library contains the instruction type of any of the executable instructions, it is also used to Any of the executable instructions is a long delay instruction.

With reference to the second possible implementation of the fourth aspect, in the seventh possible implementation manner of the foregoing fourth aspect, the determining, the determining, the determining, by the determining,

The determining module is configured to determine whether the stored key address library includes an instruction address of the any executable instruction;

If the key address library contains an instruction address of any of the executable instructions, it is used to determine that any of the executable instructions is a long delay instruction.

With reference to any of the possible implementations of the fourth aspect to the seventh possible implementation manner of the fourth aspect, in the eighth possible implementation manner of the foregoing fourth aspect, the device further includes:

An allocation module, configured to respectively allocate a storage space for each of the plurality of to-be-executed instructions, where each storage space is used to store an execution result of each of the to-be-executed instructions;

Correspondingly, the device further includes:

a second write module, configured to write an execution result of the to-be-executed instruction into a corresponding storage space every time an execution result of an instruction to be executed is obtained; and to be used after the execution of the plurality of to-be-executed instructions ends And executing, in an instruction sequence of the plurality of instructions, an execution result in a storage space corresponding to each of the plurality of to-be-executed instructions in a target register corresponding to each to-be-executed instruction.

The technical solution provided by the embodiment of the present invention has the beneficial effects that: in the embodiment of the present invention, the key instruction in the at least one executable instruction is determined, and when the at least one executable instruction is executed, the at least one executable may be preferentially executed. The key instruction in the instruction, because the key instruction includes the long delay instruction, the priority execution of the key instruction in the at least one executable instruction can delay the execution time of the instruction in advance, and during the execution of the long delay instruction, it can be guaranteed There are enough irrelevant instructions to execute, which reduces the processor's latency and improves the processor's processing performance.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention. Other drawings may also be obtained from those of ordinary skill in the art in light of the inventive work.

FIG. 1 is a flowchart of an instruction processing method according to an embodiment of the present invention.

FIG. 2 is a flowchart of another instruction processing method according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of an instruction processing process according to an embodiment of the present invention.

FIG. 4 is a schematic structural diagram of an instruction processing apparatus according to an embodiment of the present invention.

FIG. 5 is a schematic structural diagram of another instruction processing apparatus according to an embodiment of the present invention.

FIG. 6 is a schematic structural diagram of still another instruction processing apparatus according to an embodiment of the present invention.

detailed description

The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

Before the embodiments of the present invention are explained in detail, the application scenarios of the embodiments of the present invention are first introduced. While the device is running the application, the processor of the device needs to process the multiple instructions included in the application. In the process of processing instructions, some instructions will cause long delay operations, such as division instructions, transcendental instructions, etc. When the processor encounters these long delay operations, it may need to wait for the long delay operation to complete before executing other Operation reduces the performance of the processor. Therefore, an embodiment of the present invention provides an instruction processing method to improve performance of a processor.

FIG. 1 is a flowchart of an instruction processing method according to an embodiment of the present invention. Referring to Figure 1, the method includes:

Step 101: Determine a key instruction in at least one executable instruction, where the key instruction refers to a long delay instruction or an instruction located on a key instruction chain, where the key instruction chain includes an N-th order instruction, wherein the N-th order instruction The i-th order instruction is a producer instruction of the i+1th order instruction, and the producer instruction means that the target register of the i-th order instruction is a source register of the i+1th order instruction, the key instruction The Nth order instruction on the chain is a long delay instruction, N is a positive integer greater than 1, and i is a positive integer greater than 0 and less than N.

Step 102: Preferential execution of the key instruction in the at least one executable instruction.

In the embodiment of the present invention, a key instruction in the at least one executable instruction is determined, and when the at least one executable instruction is executed, the key instruction in the at least one executable instruction may be preferentially executed, because the key instruction includes a long delay instruction Therefore, preferential execution of the key instruction in the at least one executable instruction may delay the execution time of the instruction in advance, and during the execution of the long delay instruction, ensure that there are enough irrelevant instructions to be executed, thereby reducing processing. The wait time of the device, thereby improving the processing performance of the processor.

If the target register of instruction 1 is the source register of instruction 2, that is, instruction 2 is to be operated using the calculation result of instruction 1, then instruction 1 is the producer instruction of instruction 2, and instruction 2 is the consumer instruction of instruction 1, indicating instruction 1 There is a logical sequential execution relationship with instruction 2, and instruction 1 is executed prior to instruction 2.

Optionally, before determining the key instructions in the at least one executable instruction, the method further includes:

Optionally, determining key instructions in the at least one executable instruction, including:

When the key instruction identifier of any of the executable instructions is valid or the executable instruction is a long delay instruction, it is determined that the executable instruction is a key instruction.

Optionally, the method further includes:

When the key instruction identifier of the key instruction is invalid and the key instruction is a long delay instruction, the length is The critical instruction ID of the delayed instruction is set to be valid.

Optionally, the method further includes:

The identity of the key instruction is written to the instruction cache each time a critical instruction flag of an instruction is set to be valid.

Optionally, determining whether the any executable instruction is a long delay instruction comprises:

Decoding any executable instruction to obtain an instruction type of any executable instruction;

Determining whether the stored key type library contains the instruction type of any executable instruction;

If the key type library contains an instruction type of any of the executable instructions, it is determined that the executable instruction is a long delay instruction.

Determining whether the stored key address library contains an instruction address of any executable instruction;

If the key address library contains the instruction address of any of the executable instructions, then it is determined that the executable instruction is a long delay instruction.

Optionally, after the multiple execution instructions are taken from the instruction cache, the method further includes:

Allocating a storage space for each of the plurality of to-be-executed instructions, where each storage space is used to store an execution result of each to-be-executed instruction;

Correspondingly, the method further comprises:

When the execution result of an instruction to be executed is obtained, the execution result of the instruction to be executed is written into the corresponding storage space;

After the execution of the plurality of to-be-executed instructions is ended, in accordance with the instruction sequence of the plurality of instructions, the execution result in the storage space corresponding to each of the plurality of to-be-executed instructions is sequentially written to each to-be-executed instruction. Target register.

The optional embodiments of the present invention may be used in any combination to form an optional embodiment of the present invention.

FIG. 2 is a flowchart of a method for processing an instruction according to an embodiment of the present invention. See Figure 2, the party The law includes:

Step 201: Extract a plurality of to-be-executed instructions from the instruction cache according to the instruction sequence.

In the embodiment of the present invention, when the processor processes the instruction, a plurality of to-be-executed instructions may be fetched from the instruction cache according to the instruction sequence. The order of the instructions is the order in which the application runs the multiple instructions one after another.

For example, as shown in Table 1 below, the instruction cache includes seven instructions, namely an ADD instruction, a SUB instruction, an AND instruction, an XOR instruction, an LSL instruction, an LSR instruction, and a LOAD instruction, and the application sequentially runs the seven instructions. The instruction sequence is ADD instruction, SUB instruction, AND instruction, XOR instruction, LSL instruction, LSR instruction and LOAD instruction. Therefore, the processor fetches a plurality of to-be-executed instructions from the instruction cache into an ADD instruction, a SUB instruction, an AND instruction, an XOR instruction, an LSL instruction, an LSR instruction, and a LOAD instruction according to the instruction sequence.

Table 1

In the embodiment of the present invention, for each of the plurality of to-be-executed instructions, the processor may fetch the plurality of to-be-executed instructions one by one from the instruction cache according to the instruction sequence, where the embodiment of the present invention This is not specifically limited.

Optionally, in the embodiment of the present invention, the processor may also remove the multiple to-be-executed instructions from the instruction cache without following the instruction sequence, that is, the processor may fetch the instruction from the instruction cache out of order. The embodiment of the present invention does not specifically limit this.

Step 202: Determine at least one executable instruction from the plurality of to-be-executed instructions.

For any one of the plurality of to-be-executed instructions, the processor may determine whether the operand of the any instruction to be executed is ready, and if the operand of the to-be-executed instruction is ready, determine the standby The execution instruction is an executable instruction, and any of the execution instructions can be executed immediately without waiting for the execution of the instruction before the execution of any of the execution instructions. If the operand of any of the to-be-executed instructions is not ready, it is determined that the any instruction to be executed is an unexecutable instruction. At this time, it is necessary to wait until the operand of any of the to-be-executed instructions is ready to execute any of the to-be-executed instruction. The operand of any of the to-be-executed instructions is data stored in a source register of the any instruction to be executed.

Alternatively, for any of the plurality of to-be-executed instructions, the processor may determine whether the source register of the any to-be-executed instruction is valid, and if the source register of the any to-be-executed instruction is valid, determine the Once the execution instruction is an executable instruction, the any execution instruction can be executed immediately without waiting for the execution of the instruction before the execution of the any execution instruction. If the source register of any of the to-be-executed instructions is invalid, it is determined that any of the to-be-executed instructions is an unexecutable instruction, and at this time, it is necessary to wait until the source register of any of the to-be-executed instructions is valid, .

In order to advance the execution time of the long delay instruction, that is, to preferentially execute the long delay instruction and improve the processing performance of the processor, a storage space may be allocated for each of the plurality of to-be-executed instructions. Each storage space is used to store the execution result of each instruction to be executed. Correspondingly, each time an execution result of an instruction to be executed is obtained, the execution result of the instruction to be executed can be written into a corresponding storage space. Further, the storage space corresponding to the instruction to be executed is set to be valid, that is, the target register of the instruction to be executed is set to be valid.

The processor may allocate a storage number to each of the plurality of to-be-executed instructions, respectively, when a storage space is allocated for each of the plurality of to-be-executed instructions, the storage number The number corresponding to the storage space. Since the plurality of storage spaces include a pointer, the initial position of the pointer points to the first storage space. Therefore, when a storage number is respectively assigned to the plurality of to-be-executed instructions, the storage number pointed to by the pointer may be assigned to the storage space. a plurality of instructions to be executed, and each time a memory number is assigned, the pointer is shifted down by one bit, thereby obtaining the plurality of to-be-executed instructions Storage number. That is, in the embodiment of the present invention, a plurality of memory numbers may be allocated to the plurality of instructions to be executed in the order of instructions.

For example, the initial position of the pointer points to the first storage space. Therefore, the number 1 of the first storage space is assigned to the ADD instruction. At this time, the pointer moves down one bit, that is, the pointer points to the second Storage space, therefore, assign the number 2 of the second storage space to the SUB instruction. Similarly, assign the number 3 of the third storage space to the AND instruction, and assign the number 4 of the fourth storage space to the XOR instruction. The fifth storage space number 5 is assigned to the LSL instruction, the sixth storage space number 6 is assigned to the LSR instruction, and the seventh storage space number 7 is assigned to the LOAD instruction.

It should be noted that the storage number may be a Re-Order Buffer (ROB) number, and the storage space may be each entry in the ROB, which is not specifically limited in this embodiment of the present invention.

Step 203: Determine a key instruction in the at least one executable instruction, where the key instruction refers to a long delay instruction or an instruction located in a key instruction chain, where the key instruction chain includes an Nth order instruction, wherein the ith order in the Nth order instruction The instruction is a producer instruction of the i+1th order instruction, and the producer instruction is that the target register of the i th order instruction is a source register of the i+1th order instruction, and the Nth order instruction on the key instruction chain is a long delay The instruction, N is a positive integer greater than 1, and i is a positive integer greater than 0 and less than N.

It should be understood that a certain order key instruction on a key instruction chain may have a positive integer number greater than one. For example, if an addition instruction is a key instruction, and the addition instruction has N source registers, the addition instruction may have N A producer instruction, so there are N upper-order key instructions of the addition instruction.

Specifically, for any executable instruction of the at least one executable instruction, determining whether the key instruction identifier of the any executable instruction is valid or whether the any executable instruction is a long delay instruction; When the key instruction identifier of the instruction is valid or the executable instruction is a long delay instruction, determining that the executable instruction is a key instruction, thus determining a key instruction in the at least one executable instruction.

In the embodiment of the present invention, when each instruction to be executed is executed, if the instruction to be executed has a producer instruction, the instruction to be executed and the producer instruction of the instruction to be executed constitute an instruction. a chain, and when the instruction to be executed is a key instruction, and the producer instruction of the key instruction is not marked as a key instruction, setting the key instruction identifier of the producer instruction of the key instruction to be valid, that is, executing After a key instruction, the producer instruction of the key instruction can be marked as a key instruction. If the key instruction identifier of the key instruction is invalid and the key instruction is a long delay instruction, the key instruction identifier of the long delay instruction is set to be valid, that is, the long delay instruction is marked as a key instruction. Then, when the next instruction to be executed is executed, if the producer instruction of the next instruction to be executed is the last instruction in the chain, the next instruction to be executed is added to the end of the chain until the traversal A number of pending instructions. In addition, when a long delay instruction is included in the instruction chain, the instruction chain is referred to as a key instruction chain.

It should be noted that the to-be-executed instruction located on the same instruction chain has a relationship between the producer instruction and the consumer instruction, that is, when the target register of the i-th to-be-executed instruction on the instruction chain is the (i+1)th. When the source register of the instruction is to be executed, the i-th order to-be-executed instruction may be referred to as the producer instruction of the i+1th-order to-be-executed instruction, and the i-th order-to-be-executed instruction is referred to as the i-th order to-be-executed instruction. Consumer instruction.

Further, the key instruction identifier is used to identify whether the instruction to be executed is a key instruction or a non-key instruction, that is, when the key instruction identifier of an instruction to be executed is valid, it may be determined that the instruction to be executed is a key instruction, and when When the key instruction identifier of the instruction to be executed is invalid, it may be determined that the instruction to be executed is a non-critical instruction. The key operation identifier can be set to a valid operation by setting the key instruction identifier to the first value. When the key instruction identifier is invalid, the key instruction identifier can be set to the second value. The first value and the second value may be set in advance. For example, the first value may be 1 and the second value may be 0, which is not specifically limited in the embodiment of the present invention.

In addition, each critical instruction identification can be stored in the instruction cache whenever a critical instruction identification of an instruction to be executed is set to be valid. In this way, when the instruction to be executed is taken out from the instruction cache next time, the key instruction can be directly learned, and the efficiency of the instruction processing is improved.

In the embodiment of the present invention, whether the executable instruction is a long delay instruction may be determined in two ways, including:

The first way is to decode the executable instruction to obtain the instruction type of the executable instruction; determine whether the stored key type library contains the instruction type of the executable instruction; if the key type The library contains the type of instruction for any of the executable instructions, and then determines that any of the executable instructions is a long delayed instruction. If the type of the instruction of the executable instruction is not included in the key type library, it is determined that the executable instruction is a long delay instruction.

For example, the executable instruction is a LOAD instruction, and the executable instruction is decoded, and the instruction type of the executable instruction is the memory access instruction. In this case, the executable instruction may be The instruction type is compared with the instruction type included in the key type library shown in Table 2 below, and the instruction type of the executable instruction is determined in the key type library. At this time, it is determined that the executable instruction is a long delay. instruction.

Table 2

指令类型Instruction type
指令类型Instruction type	除法指令Division instruction
访存指令Fetch instruction	除法指令Division instruction
访存指令Fetch instruction	超越函数指令Transcendental function instruction
加解密指令Encryption instruction	超越函数指令Transcendental function instruction
加解密指令Encryption instruction	……......

Optionally, in the embodiment of the invention, not only the key type library may be set to include an instruction type, but also whether the any executable instruction is a long delay instruction based on the foregoing method. Of course, in practical applications, it is also possible to determine whether any of the executable instructions is a long delay instruction by other means. For example, the processor decodes any of the executable instructions to obtain the type of instruction for any of the executable instructions. Then, based on the instruction type of the executable instruction, the corresponding identification value is obtained from the stored key type library, and if the acquired identification value is the first value, determining that the executable instruction is a long delay instruction, if Obtaining the identifier value as the second value, determining that the executable instruction is not a long delay instruction. The key type library may include a correspondence between the instruction type and the identifier value. Of course, in an actual application, the instruction type corresponding to each identifier value in the key type library may be agreed in advance. At this time, the key The value of the identifier may be included in the type library, which is not specifically limited in the embodiment of the present invention.

It should be noted that the process of decoding the executable instruction by the processor may be referred to the related art, which is not described in detail in the embodiment of the present invention.

For convenience of description, in the embodiment of the present invention, the correspondence between the key type library including the instruction type and the identification value is taken as an example for description. For example, if the first value is 1, the executable instruction is a LOAD instruction, and the executable instruction is decoded, and the instruction type of the executable instruction is the memory access instruction. Based on the instruction type of the executable instruction, the corresponding identification value is 1 from the correspondence between the stored instruction type and the identification value shown in Table 3 below. At this time, the executable instruction is determined. For long delay instructions.

table 3

指令类型Instruction type	标识数值Identification value
指令类型Instruction type	标识数值Identification value
加法指令Addition instruction	00
加法指令Addition instruction	00	减法指令 Subtraction instruction	00
逻辑与指令Logic and instruction	00	减法指令 Subtraction instruction	00
逻辑与指令Logic and instruction	00	异或指令 XOR instruction	00
移位指令 Shift instruction	00	异或指令 XOR instruction	00
移位指令 Shift instruction	00	左移指令 Left shift instruction	00
访存指令Fetch instruction	11	左移指令 Left shift instruction	00
访存指令Fetch instruction	11	除法指令 Division instruction	11
加解密指令 Encryption instruction	00	除法指令 Division instruction	11
加解密指令 Encryption instruction	00	超越函数指令 Transcendental function instruction	11
……......	……......	超越函数指令 Transcendental function instruction	11

The second method determines whether the stored address address of the executable instruction is included in the stored key address library; if the command address of the executable instruction is included in the critical address library, determining that the executable instruction is long Delayed instruction. If the instruction address of any of the executable instructions is not included in the critical address library, it is determined that the executable instruction is not a long delay instruction.

For example, any of the executable instructions is a LOAD instruction, and the instruction address of the LOAD instruction is 0x1f00_0340. At this time, the processor compares the instruction address of the LOAD instruction with the key address library shown in Table 4 below, and determines that the instruction address of the LOAD instruction is included in the key address library, and therefore, determining that any executable instruction is long Delayed instruction.

Table 4

指令地址Instruction address
指令地址Instruction address	0x1f00_00000x1f00_0000
0x1f00_02000x1f00_0200	0x1f00_00000x1f00_0000
0x1f00_02000x1f00_0200	0x1f00_02800x1f00_0280
0x1f00_03400x1f00_0340	0x1f00_02800x1f00_0280
0x1f00_03400x1f00_0340	……......

It should be noted that the instruction address of the instruction is the storage address of the instruction, which is not specifically limited in this embodiment of the present invention. In addition, the key type library and the key address library are configured in advance, and the key type library and the key address library can be dynamically modified, which is not specifically limited in the embodiment of the present invention.

Step 204: Priority execution of key instructions in the at least one executable instruction.

Wherein, when the processor preferentially executes the key instruction in the at least one executable instruction, if the long delay instruction is executed, the unrelated instruction may be executed during the execution of the long delay instruction, thereby executing the multiple instruction to obtain The execution result of the multiple instructions. The irrelevant instruction is an instruction other than the instruction included in the key instruction chain of the long delay instruction in the plurality of instructions.

Since the key instruction can include a long delay instruction, when executing the multiple instruction, the key instruction in the at least one executable instruction is preferentially executed, so that there are enough irrelevant instructions in the execution of the long delay instruction. Execute, reduce processor wait time, and improve processing Processing performance.

Further, in the embodiment of the present invention, when the execution result of an instruction to be executed is obtained, the execution result of the instruction to be executed may be written into the corresponding storage space.

For example, when the execution result of the AND instruction is 01110110, the execution result may be stored in the third storage space in the ROB. When the execution result of the LSL instruction is 11101100, the execution result may be stored in the ROB. The fifth storage space, in the same way, stores the execution result of the LOAD instruction in the seventh storage space in the ROB, stores the execution result of the ADD instruction in the first storage space in the ROB, and stores the execution result of the SUB instruction. In the second storage space in the ROB, the execution result of the XOR instruction is stored in the fourth storage space in the ROB, and the execution result of the LSR instruction is stored in the sixth storage space in the ROB.

Step 205: Write, according to the target register number of the plurality of instructions, the execution result of the plurality of instructions into the corresponding target register according to the instruction sequence.

Since the execution result of each instruction is stored in the storage space included in the processor, after the execution of the plurality of to-be-executed instructions ends, the processor may sequentially follow the instruction sequence of the plurality of to-be-executed instructions. The execution result in the storage space corresponding to each to-be-executed instruction in the to-be-executed instruction is written to the target register corresponding to each instruction to be executed. Specifically, the processor may obtain an execution result of each to-be-executed instruction from a storage space corresponding to the plurality of to-be-executed instructions; and perform an execution result according to the target register number of the plurality of to-be-executed instructions. Write to the corresponding destination register.

It should be noted that, when the processor writes the execution result of the multiple to-be-executed instructions into the corresponding target register according to the instruction sequence, if the current pending execution instruction has not obtained the execution result, even if the current pending execution instruction is to be executed The execution instruction obtains the execution result, and then the execution result of the to-be-executed instruction after the current to-be-executed instruction cannot be written to the corresponding target register across the current to-be-executed instruction, and can only wait until the current to-be-executed instruction obtains the execution result, and the After the execution result is written into the corresponding target register, the execution result of the instruction to be executed after the current instruction to be executed can be submitted to the corresponding target register.

In addition, after the processor writes the execution result of the instruction to be executed into the corresponding target register, the storage number corresponding to the instruction to be executed may be released, and the corresponding storage space is released.

In summary, the process of processing an instruction may be represented by a process as shown in FIG. 3 below, that is, the processor needs to first fetch a plurality of to-be-executed instructions from the instruction cache. Thereafter, the plurality of to-be-executed instructions are decoded, and the long-delay instruction among the plurality of to-be-executed instructions is identified based on the configuration information in the decoding stage, the configuration information including a key type library or a key address library. Re-naming each instruction to be executed, that is, allocating a storage space for each instruction to be executed, then starting to execute the plurality of instructions to be executed, and storing the execution result of the plurality of instructions to be executed in Corresponding storage space. Afterwards, the processor can also store each key instruction identifier in the instruction cache to facilitate the next instruction fetching and improve the instruction processing efficiency.

In the embodiment of the present invention, a plurality of to-be-executed instructions may be fetched from the instruction cache according to an instruction sequence, and at least one executable instruction is obtained from the plurality of to-be-executed instructions, and when the at least one executable instruction is executed The key instruction in the at least one executable instruction may be preferentially executed. Since the key instruction includes a long delay instruction, the key instruction in the at least one executable instruction is preferentially executed, and the execution time of the instruction may be delayed in advance, and During the execution of a long delay instruction, it is guaranteed that there are enough irrelevant instructions to execute, thereby reducing the waiting time of the processor, thereby improving the processing performance of the processor.

Embodiments of the present invention provide a computing device readable medium, including a computing device executing instructions, when the processor of the computing device executes the computing device to execute an instruction, the computing device may perform the instruction processing method described above.

Referring to FIG. 4, an embodiment of the present invention provides an instruction processing device, which includes: a processor 401, a memory 402, a bus 403, and a communication interface 404;

The memory 402 is used to store computer execution instructions 4021 through which the processor 401 and the memory 402 are connected. When the data storage device is in operation, the processor 401 executes the memory 402. The computer executes the instructions to cause the instruction processing device to perform the instruction processing method described above.

FIG. 5 is a schematic structural diagram of an instruction processing apparatus according to an embodiment of the present invention. Referring to Figure 5, the device includes:

The determining module 501 is configured to determine a key instruction in the at least one executable instruction, where the key instruction refers to a long delay instruction or an instruction located on a key instruction chain, where the key instruction chain includes an N-th order instruction, wherein the N-th order instruction The i-th order instruction is a producer instruction of the i+1th order instruction, and the producer instruction means that the target register of the i-th order instruction is a source register of the i+1th order instruction, and the Nth order of the key instruction chain The instruction is a long delay instruction, N is a positive integer greater than 1, and i is a positive integer greater than 0 and less than N;

The execution module 502 is configured to preferentially execute the key instructions in the at least one executable instruction.

Optionally, referring to FIG. 6, the device further includes:

The fetch module 503 is configured to fetch a plurality of to-be-executed instructions from the instruction cache.

The determining module 501 is further configured to determine at least one executable instruction from the plurality of to-be-executed instructions.

Optionally, the determining module 401 is configured to determine key instructions in the at least one executable instruction, including:

For any executable instruction of the at least one executable instruction, the determining module 401 is configured to determine whether the key instruction identifier of the any executable instruction is valid or whether the any executable instruction is a long delay instruction; When the key instruction identifier of the executable instruction is valid or the executable instruction is a long delay instruction, it is also used to determine that the executable instruction is a key instruction.

Optionally, the device further includes:

The first setting module is configured to set a key instruction identifier of the producer instruction of the key instruction to be valid when the manufacturer instruction is present in the key instruction, and the producer instruction of the key instruction is not marked as the key instruction.

Optionally, the device further includes:

The second setting module is configured to set the key instruction identifier of the long delay instruction to be valid when the key instruction identifier of the key instruction is invalid and the key instruction is a long delay instruction.

Optionally, the device further includes:

The first write module is configured to write the identifier of the critical instruction into the instruction cache every time the critical instruction identifier of an instruction is set to be valid.

Optionally, the determining module 501 is configured to determine whether the any executable instruction is a long delay instruction, including:

a determining module 501, configured to decode the executable instruction to obtain an instruction type of the executable instruction;

And used to determine whether the stored key type library contains the instruction type of any executable instruction;

If the key type library contains an instruction type of any of the executable instructions, it is also used to determine that any of the executable instructions is a long delay instruction.

a determining module 501, configured to determine whether the stored key address library includes an instruction address of the executable instruction;

If the key address library contains the instruction address of any of the executable instructions, it is used to determine that any of the executable instructions is a long delay instruction.

Optionally, the device further includes:

An allocation module, configured to respectively allocate a storage space for each of the plurality of to-be-executed instructions, where each storage space is used to store an execution result of each to-be-executed instruction;

Accordingly, the device further includes:

a second write module, configured to write an execution result of the to-be-executed instruction into a corresponding storage space every time an execution result of the to-be-executed instruction is obtained; and, after the execution of the plurality of to-be-executed instructions ends, follow The instruction sequence of the plurality of to-be-executed instructions sequentially writes the execution result in the storage space corresponding to each of the plurality of to-be-executed instructions to the target register corresponding to each instruction to be executed.

In an embodiment of the present invention, determining a key instruction in the at least one executable instruction while performing the When at least one executable instruction is executed, the key instruction in the at least one executable instruction may be preferentially executed. Since the key instruction includes a long delay instruction, the key instruction in the at least one executable instruction is preferentially executed, and the instruction may be delayed in advance. Execution time, and during the execution of the long delay instruction, it can be ensured that there are enough irrelevant instructions to be executed, thereby reducing the waiting time of the processor, thereby improving the processing performance of the processor.

A person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium. The storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalents, improvements, etc., which are within the spirit and scope of the present invention, should be included in the protection of the present invention. Within the scope.

Claims

An instruction processing method, characterized in that the method comprises:

Determining a key instruction in at least one executable instruction, the key instruction being a long delay instruction or an instruction located on a critical instruction chain, the key instruction chain comprising an Nth order instruction, wherein the ith of the Nth order instructions The order instruction is a producer instruction of the i+1th order instruction, and the producer instruction means that the target register of the i th order instruction is a source register of the i+1th order instruction, and the Nth of the key instruction chain The order instruction is a long delay instruction, N is a positive integer greater than 1, and i is a positive integer greater than 0 and less than N;

The key instructions of the at least one executable instruction are preferentially executed.
The method of claim 1, wherein before the determining the key instructions in the at least one executable instruction, the method further comprises:

Extracting a plurality of to-be-executed instructions from the instruction cache;

From the plurality of to-be-executed instructions, at least one executable instruction is determined.
The method of claim 1 wherein said determining a key instruction in the at least one executable instruction comprises:

Determining, for any executable instruction of the at least one executable instruction, whether the key instruction identifier of the any executable instruction is valid or whether the any executable instruction is a long delay instruction;

When the critical instruction identification of any of the executable instructions is valid or the any executable instruction is a long delay instruction, it is determined that the any executable instruction is a key instruction.
The method according to any one of claims 1 to 3, wherein the method further comprises:

When there is a producer instruction in the key instruction, and the producer instruction of the key instruction is not marked as a key instruction, the key instruction identifier of the producer instruction of the key instruction is set to be valid.
The method according to any one of claims 1 to 4, wherein the method further comprises:

When the key instruction identifier of the key instruction is invalid and the key instruction is a long delay instruction, the key instruction identifier of the long delay instruction is set to be valid.
The method according to claim 4 or 5, wherein the method further comprises:

The identity of the critical instruction is written into the instruction cache each time a critical instruction identification of an instruction is set to be valid.
The method according to claim 3, wherein the determining whether the any executable instruction is a long delay instruction comprises:

Decoding any of the executable instructions to obtain an instruction type of any of the executable instructions;

Determining whether the stored key type library contains the instruction type of any of the executable instructions;

If the key type library contains an instruction type of any of the executable instructions, it is determined that the any executable instruction is a long delay instruction.
The method according to claim 3, wherein the determining whether the any executable instruction is a long delay instruction comprises:

Determining whether the stored key address library contains the instruction address of any of the executable instructions;

If the key address library contains an instruction address of any of the executable instructions, it is determined that the any executable instruction is a long delay instruction.
The method according to any one of claims 1-8, wherein after the fetching a plurality of to-be-executed instructions from the instruction cache, the method further comprises:

Allocating a storage space for each of the plurality of to-be-executed instructions, where each storage space is used to store an execution result of each of the to-be-executed instructions;

Correspondingly, the method further comprises:

When the execution result of the instruction to be executed is obtained, the execution result of the instruction to be executed is written into the corresponding storage space;

After the execution of the plurality of to-be-executed instructions is ended, the execution results in the storage space corresponding to each of the plurality of to-be-executed instructions are sequentially written in accordance with the instruction sequence of the plurality of to-be-executed instructions. The target register corresponding to each instruction to be executed is described.
A computing device readable medium, comprising: a computing device executing instructions, when the processor of the computing device executes the computing device to execute an instruction, the computing device performing the method of any one of claims 1-9 .
An instruction processing device, characterized in that the device comprises: a processor, a memory, a bus and a communication interface;

The memory is configured to store a computer execution instruction, the processor is coupled to the memory via the bus, and when the data storage device is in operation, the processor executes the computer-executed instruction stored in the memory to The instruction processing device is caused to perform the method of any of claims 1-9.
An instruction processing device, characterized in that the device comprises:

Determining a module for determining a key instruction in the at least one executable instruction, the key instruction being a long delay instruction or an instruction located on a key instruction chain, the key instruction chain comprising an Nth order instruction, wherein the Nth order The i-th order instruction in the instruction is a producer instruction of the (i+1)th instruction, and the producer instruction is that the target register of the i-th order instruction is a source register of the (i+1)th instruction, the key instruction The Nth order instruction on the chain is a long delay instruction, N is a positive integer greater than 1, and i is a positive integer greater than 0 and less than N;

And an execution module, configured to preferentially execute the key instruction in the at least one executable instruction.
The device according to claim 12, wherein the device further comprises an instruction fetching module,

The fetching module is configured to fetch a plurality of to-be-executed instructions from the instruction cache;

The determining module is further configured to determine at least one executable instruction from the plurality of to-be-executed instructions.
The device according to claim 12, wherein the determining module is configured to determine key instructions in the at least one executable instruction, including:

For any executable instruction of the at least one executable instruction, the determining module is configured to determine whether the key instruction identifier of the any executable instruction is valid or whether the any executable instruction is a long delay instruction; When the key instruction identifier of any of the executable instructions is valid or the any executable instruction is a long delay instruction, it is further used to determine that the any executable instruction is a key instruction.
The device according to any one of claims 12 to 14, wherein the device further comprises:

a first setting module, configured to have a producer instruction in the key instruction, and the key instruction When the producer instruction is not marked as a critical instruction, the key instruction identifier of the producer instruction of the key instruction is set to be valid.
The device according to any one of claims 12-15, wherein the device further comprises:

And a second setting module, configured to: when the key instruction identifier of the critical instruction is invalid and the key instruction is a long delay instruction, set a key instruction identifier of the long delay instruction to be valid.
The device according to claim 15 or 16, wherein the device further comprises:

The first write module is configured to write an identifier of the key instruction into the instruction cache every time a key instruction identifier of an instruction is set to be valid.
The device according to claim 14, wherein the determining module is configured to determine whether the any executable instruction is a long delay instruction, including:

The determining module is configured to decode any one of the executable instructions to obtain an instruction type of the any executable instruction;

And used to determine whether the stored key type library contains the instruction type of any of the executable instructions;

If the key type library contains the instruction type of any of the executable instructions, it is further used to determine that the any executable instruction is a long delay instruction.
The device according to claim 14, wherein the determining module is configured to determine whether the any executable instruction is a long delay instruction, including:

The determining module is configured to determine whether the stored key address library includes an instruction address of the any executable instruction;

If the key address library contains an instruction address of any of the executable instructions, it is used to determine that any of the executable instructions is a long delay instruction.
The device according to any one of claims 12 to 19, wherein the device further comprises:

An allocation module, configured to respectively allocate a storage space for each of the plurality of to-be-executed instructions, where each storage space is used to store an execution result of each of the to-be-executed instructions;

Correspondingly, the device further includes:

a second write module, configured to write an execution result of the to-be-executed instruction into a corresponding storage space every time an execution result of an instruction to be executed is obtained; and to be used after the execution of the plurality of to-be-executed instructions ends And executing, in an instruction sequence of the plurality of to-be-executed instructions, an execution result in a storage space corresponding to each of the plurality of to-be-executed instructions in a target register corresponding to each to-be-executed instruction.