CN102799419B - Register writing conflict detection method and device, and processor - Google Patents
Register writing conflict detection method and device, and processor Download PDFInfo
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- CN102799419B CN102799419B CN201210325334.7A CN201210325334A CN102799419B CN 102799419 B CN102799419 B CN 102799419B CN 201210325334 A CN201210325334 A CN 201210325334A CN 102799419 B CN102799419 B CN 102799419B
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Abstract
The invention provides a register writing conflict detection method, a register writing conflict detection device and a processor. The register writing conflict detection method comprises the following steps of: initially resetting a writing effective queue; acquiring an instruction execution delay of an instruction; reading a writing effective bit value of a queue position with same duration as the instruction execution delay of the instruction in an instruction ready-transmitting state from the writing effective queue; judging the writing effective bit value read from the writing effective queue; allowing to transmit the instruction in the instruction ready-transmitting state when judging that the read value expresses the allowance of instruction transmission; setting a writing effective bit value for disallowing instruction transmission in the position with the same duration as the instruction execution delay of the instruction in the instruction ready-transmitting state in the writing effective queue; and disallowing to transmit the instruction in the instruction ready-transmitting state when judging that the read value expresses the disallowance of instruction transmission. The invention provides the detection method based on register writing conflict, so that the out-of-order transmission of the instructions can be realized by using less hardware complexity, therefore the efficiency of instruction flow line is improved.
Description
Technical field
The present invention relates to field of computer technology, more particularly, the present invention relates to a kind of register write conflict detection method for instruction issue and register write conflict pick-up unit, in addition, the invention still further relates to a kind of this register write conflict detection method for instruction issue or processor of device of having adopted.
Background technology
Modern processors generally adopts pipelining to improve the processing speed of processor.Pipelining refers to that when program is carried out a kind of accurate parallel processing that many effects of overlappings operate realizes technology.More particularly, pipelining is divided into a plurality of stages by an execution process instruction, wherein in different phase, carries out different instruction, thereby realizes the parallel of instruction, can improve thus the processing speed of processor.
Existing processor pipeline emission mechanism, mainly contains two kinds of out of order transmitting and sequential firing.
On the one hand, common out of order emission mechanism is mainly in order to improve the performance of instruction pipelining.More particularly, the in the situation that of out of order emission mechanism, as long as instruction is ready, just can firing order, when instruction executes, write physical register file.But the problem of this out of order transmitting is, due to the opportunity of not considering that instruction completes, therefore exist many instructions to write the possibility of physical register file simultaneously, need to realize a plurality of write ports, thereby increase the complicacy of physical register file.
On the other hand, common sequential firing mechanism is mainly in order to reduce the complicacy of instruction pipelining.More particularly, in sequential firing mechanism, after instruction is ready, after executing, the instruction of having launched before waiting could continue transmitting.Although sequential firing has reduced the complicacy of physical register file, as long as realize a write port, also reduced the efficiency of instruction pipelining.
Therefore, hope can provide a kind of out of order transmitting that utilizes less hardware complexity to realize instruction to improve the technical scheme of the efficiency of instruction pipelining.
Summary of the invention
Technical matters to be solved by this invention is for there being above-mentioned defect in prior art, the register write conflict detection method for instruction issue of the efficiency that a kind of out of order transmitting that utilizes less hardware complexity to realize instruction improves instruction pipelining is provided and has adopted this processor for the register write conflict detection method of instruction issue.
According to a first aspect of the invention, a kind of register write conflict detection method for instruction issue is provided, it comprises: first step, for initially to resetting with effect queue so that by with effect the Data Position in queue all reset to represent to allow firing order with effect place value; Second step, for obtaining the instruction execution delay of the instruction in instruction launch standby; Third step, for read with the queue position of effect queue and the durations such as instruction execution delay of the described instruction in instruction launch standby with effect place value, describedly with effect place value, represent to allow firing order or represent not allow firing order; The 4th step, for judge read with effect queue, read with effect place value, represent to allow firing order still not allow firing order; The 5th step, allows the described instruction in instruction launch standby of transmitting while allowing firing order for the value representation reading in described the 4th step judgement; The 6th step, for after the 5th step, in the position with effect queue and the durations such as instruction execution delay of instruction in instruction launch standby, arrange do not allow firing order with effect place value; And the 7th step, for the value that reads in described the 4th step judgement, do not allow the described instruction in instruction launch standby of transmitting when not allowing firing order.
Preferably, according to the register write conflict detection method for instruction issue described in first aspect present invention, also comprise: the 8th step, it carries out after described the 6th step or described the 7th step, be used for making described with effect queue to one of queue heads logical shift, and in the position of the described rear of queue with effect queue, arrange one represent to allow firing order with effect place value.
Preferably, according to the register write conflict detection method for instruction issue described in first aspect present invention, described register write conflict detection method is got back to described second step after executing described the 8th step.
Preferably, according to the register write conflict detection method for instruction issue described in first aspect present invention, numerical value " 0 " represent to allow firing order with effect place value, and numerical value " 1 " represent not allow firing order with effect place value.
According to a second aspect of the invention, providing a kind of has adopted according to the processor of the register write conflict detection method for instruction issue described in first aspect present invention.
According to a third aspect of the invention we, provide a kind of register write conflict pick-up unit for instruction issue, it comprises: storage unit, wherein stored the longest instruction execution delay of and instruction isometric with effect queue; And control module, for carrying out following operation: initially to resetting with effect queue so that by with effect the Data Position in queue all reset to represent to allow firing order with effect place value; Obtain the instruction execution delay of the instruction in instruction launch standby; Read with in effect queue with the queue position of the durations such as instruction execution delay of the described instruction in instruction launch standby with effect place value, describedly with effect place value, represent to allow firing order or represent not allow firing order; Judgement read with effect queue read with effect place value represent to allow firing order still not allow firing order; When the value representation reading in judgement allows firing order, allow the described instruction in instruction launch standby of transmitting, and in effect queue with the position of the durations such as instruction execution delay of instruction in instruction launch standby arrange do not allow firing order with effect place value; And the value reading in judgement is while not allowing firing order, not allow the described instruction in instruction launch standby of transmitting.
Preferably, according to the register write conflict pick-up unit for instruction issue described in third aspect present invention, described control module is not also for after allowing the described instruction or the described instruction in instruction launch standby of permission transmitting in instruction launch standby of transmitting, make described with effect queue to one of queue heads logical shift, and described with effect queue to the position of rear of queue arrange one represent to allow firing order with effect place value.
Preferably, according to the register write conflict pick-up unit for instruction issue described in third aspect present invention, described storage unit is to realize by the register setting of processor.
Preferably, according to the register write conflict pick-up unit for instruction issue described in third aspect present invention, described control module is that the CPU (central processing unit) by processor realizes.
According to a forth aspect of the invention, providing a kind of has configured according to the processor of the register write conflict pick-up unit for instruction issue described in third party of the present invention.
According to the present invention, by using unified judging with the displacement of effect queue logic and conflict, allow the out of order register file of writing of instruction, thereby improve the efficiency of instruction issue.More particularly, instruction issue scheme of the present invention is by judging writing the conflict of register file, use less hardware spending, allow short delay instruction to surmount long delay instruction and first write register file, realize the out of order register file of writing, make full use of the write port of register file, thereby improve instruction issue efficiency.Thus, the invention provides a kind of detection method and device based on register write conflict, this detection method and device can utilize less hardware complexity to realize the out of order transmitting of instruction, to improve the efficiency of instruction pipelining.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily to the present invention, there is more complete understanding and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows according to the preferred embodiment of the invention the process flow diagram for the register write conflict detection method of instruction issue.
Fig. 2 schematically shows according to the preferred embodiment of the invention with the example of imitating queue.
Fig. 3 schematically shows according to the preferred embodiment of the invention the block diagram for the register write conflict pick-up unit of instruction issue.
It should be noted that, accompanying drawing is used for illustrating the present invention, and unrestricted the present invention.Note, the accompanying drawing that represents structure may not be to draw in proportion.And in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
< the first embodiment >
Fig. 1 schematically shows according to the preferred embodiment of the invention the process flow diagram for the register write conflict detection method of instruction issue.It should be noted that, the term in this instructions " detection of register write conflict ", for " the write conflict detection " that be " physical register file ", detects referred to as register write conflict ".
As shown in Figure 1, for the register write conflict detection method of instruction issue, comprise according to the preferred embodiment of the invention:
First step 1, for initially, (for example, when processor starts) to resetting with effect queue so that by with effect the Data Position in queue all reset to represent to allow firing order with effect place value; For example, as shown in Figure 1, can when initial, make with effect queue zero clearing, that is, making with the Data Position of imitating in queue is all zero (in the present embodiment, adopted value " 0 " represents to allow firing order).
Second step 2, when instruction is during in " instruction prepare transmitting " state, obtains the instruction execution delay of this instruction.That is, at second step 2, obtain the instruction execution delay of the instruction in " transmitting is prepared in instruction " state.
Specifically, above-mentioned term " instruction prepare transmitting " refers to such state: the source operand of instruction is ready to, and this instruction and launched that not exist truth to close between the instruction of execution relevant with output, and this instruction is just etc. to be launched.Term " instruction execution delay " is an attribute of instruction, and it just produced before instruction enters launching phase; Specifically, " instruction execution delay " refers to that an instruction, from being transmitted into execution, also having prepared to write the needed beat number of physical register file, really writes physical register file next beat after this beat number conventionally.Wherein, physical register file (in this area, be sometimes called for short " register file "), refers to for reading command and carries out action required number, and a kind of storer of the execution result that is used for holding instruction.
Third step 3, read with in effect queue with the queue position of the durations such as instruction execution delay of the instruction (that is, the instruction in " transmitting is prepared in instruction " state) of this preparations transmitting with imitating place value.Wherein, with effect place value or expression permission firing order, or represent not allow firing order.In other words, follow-up by by read with in effect queue with the queue position of the durations such as instruction execution delay of the instruction of this preparations transmitting with imitating place value, judge whether to launch this instruction.
It should be noted that, term " waits the queue position of duration " and refers in effect queue team and postpones (for example instruction execution delay) arrival with the position of effect queue queue heads through corresponding.
The 4th step 4, judgement read with effect queue read with effect place value.Specifically, judgement read with effect queue read with effect place value represent that " permission firing order " still " do not allow firing order ".
The 5th step 5, if the value that reads of judgement, for " 0 " (represent in the present embodiment allow firing order with effect place value), allows this instruction of transmitting in the 4th step 4.
The 6th step 6, it carries out after the 5th step 5, for carrying out the position set that delays wait duration (represent in the present embodiment do not allow firing order with imitating place value) with effect queue and this firing order.Thus, can arrange for the instruction execution delay of all instructions long instruction in an and instruction carry out postpone isometric with effect queue." the long instruction of and instruction carry out postpone isometric " refers to, and when carrying out through long instruction while postponing, with the data of the rear of queue of effect queue, is just in time displaced to queue heads.
With effect queue, when passing through an operating cycle of described register write conflict detection method, along queue sense of displacement X-direction queue heads B direction, carry out the logical shift (as shown in Figure 2) of one.
By in conjunction with the 5th step 5 and the 6th step 6, can find out, when the queue heads B position with effect queue with effect place value while being " 1 ", show that current beat has result to prepare to write back register file (, in the 5th step 5, allow the instruction of transmitting will write physical register file after corresponding instruction execution delay, and now, " 1 " arranging in the 6th step 6 is just in time in the queue heads B position with effect queue), correspondingly, should not allow firing order.
The 7th step 7, if the value that reads of judgement, for " 1 " (represent in the present embodiment do not allow firing order with effect place value), does not allow to launch this instruction in the 4th step 4.Thus, can guarantee can not to have in the state of a plurality of instructions of writing same register file entry in register is operated (avoiding register write conflict).
The 8th step 8, it carries out after described the 6th step 6 or described the 7th step 7, for making, with effect queue to queue heads B logical shift, moves 1.Concrete, in the 8th step 8, due to queue heads B displacement, in the position of rear of queue A, arrange one represent to allow firing order with effect place value (being numerical value " 0 " in the present embodiment).
After the 8th step 8, get back to second step 2.After this, repeat second step 2 to the operating cycle of the 8th step 8.
In above-mentioned register write conflict detection method, by using unified judging with the displacement of effect queue logic and conflict, allow the out of order register file of writing of instruction, thereby improve the efficiency of instruction issue.More particularly, the disclosed instruction issue method of the above embodiment of the present invention is by judging writing the conflict of register file, use less hardware spending, allow short delay instruction to surmount long delay instruction and first write register file, realize the out of order register file of writing, make full use of the write port of register file, thereby improve instruction issue efficiency.
Thus, the above embodiment of the present invention provides a kind of detection method based on register write conflict, and this detection method can utilize less hardware complexity to realize the out of order transmitting of instruction, to improve the efficiency of instruction pipelining.
It should be noted that, although above-described embodiment with numerical value " 0 " represent to allow firing order with effect place value, and with numerical value " 1 " represent not allow firing order with effect place value; But, represent conversely it is also feasible, that is to say, in another embodiment, can with numerical value " 1 " represent to allow firing order with effect place value, and with numerical value " 0 " represent not allow firing order with effect place value.
According to another preferred embodiment of the invention, the present invention also provides a kind of processor that has adopted the above-mentioned register write conflict detection method for instruction issue, for example microprocessor.
< the second embodiment >
Fig. 3 schematically shows according to the preferred embodiment of the invention the block diagram for the register write conflict pick-up unit of instruction issue.
As shown in Figure 2, for the register write conflict pick-up unit 100 of instruction issue, comprise according to the preferred embodiment of the invention:
Storage unit 1, wherein stored the longest instruction execution delay of and instruction isometric with effect queue 11; And
Control module 2, for shown in execution graph 1 according to the preferred embodiment of the invention for the register write conflict detection method of instruction issue.
Wherein, for instruction execution delay be provided with the longest instruction execution delay of an and instruction isometric with effect queue 11, should be with effect queue 11 for carrying out the logical shift of one for per operating cycle of the register write conflict detection method of instruction issue to queue heads B direction (queue sense of displacement X) according to the preferred embodiment of the invention shown in Fig. 1, when queue heads B is when writing significance bit for for example " 1 ", showing have result to prepare to write back register file when clapping.As shown in Figure 2, with effect queue, by rear of queue A, to queue heads B, carry out logical shift, often move one, " 0 " is mended in the position of rear of queue A.
Wherein, storage unit 1 can realize by original register setting of processor, and without increasing extraly storage medium.Control module 2 can be realized by original processing and control element (PCE) of processor, CPU (central processing unit) for example, and without increasing extraly processing and control element (PCE).
More particularly, control module 2 is for carrying out following operation: initially to resetting with effect queue so that by with effect the Data Position in queue all reset to represent to allow firing order with effect place value; Obtain the instruction execution delay of the instruction in instruction launch standby; Read with in effect queue with the queue position of the durations such as instruction execution delay of the described instruction in instruction launch standby with effect place value, describedly with effect place value, represent to allow firing order or represent not allow firing order; Judgement read with effect queue read with effect place value represent to allow firing order still not allow firing order; When the value representation reading in judgement allows firing order, allow the described instruction in instruction launch standby of transmitting, and in effect queue with the position of the durations such as instruction execution delay of instruction in instruction launch standby arrange do not allow firing order with effect place value; And the value reading in judgement is while not allowing firing order, not allow the described instruction in instruction launch standby of transmitting.
Thus, after control module 2 is also used in and does not allow the described instruction or the described instruction in instruction launch standby of permission transmitting in instruction launch standby of transmitting, make with effect queue 11 to one of queue heads logical shift, and described with effect queue to the position of rear of queue arrange one represent to allow firing order with effect place value.
Equally, preferably, with numerical value " 0 " represent to allow firing order with effect place value, and with numerical value " 1 " represent not allow firing order with effect place value; Alternatively, represent conversely it is also feasible, that is to say, in another embodiment, can with numerical value " 1 " represent to allow firing order with effect place value, and with numerical value " 0 " represent not allow firing order with effect place value.
Therefore, similarly, in above-mentioned register write conflict pick-up unit, by using unified judging with the displacement of effect queue logic and conflict, allow the out of order register file of writing of instruction, thereby improve the efficiency of instruction issue.More particularly, the above embodiment of the present invention is by judging writing the conflict of register file, use less hardware spending, allow short delay instruction to surmount long delay instruction and first write register file, realize the out of order register file of writing, make full use of the write port of register file, thereby improve instruction issue efficiency.
Thus, the above embodiment of the present invention provides a kind of pick-up unit based on register write conflict, and this detection method can utilize less hardware complexity to realize the out of order transmitting of instruction, to improve the efficiency of instruction pipelining.
According to another preferred embodiment of the invention, the present invention also provides a kind of processor that disposes the above-mentioned register write conflict pick-up unit for instruction issue, for example microprocessor.
It should be noted that, the descriptions such as the term in instructions " first ", " second ", " the 3rd " are only for distinguishing each assembly, element, step of instructions etc., rather than for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclosure as above, yet above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (7)
1. for a register write conflict detection method for instruction issue, it is characterized in that comprising:
First step, for initially to resetting with effect queue so that by with effect the Data Position in queue all reset to represent to allow firing order with effect place value;
Second step, for obtaining the instruction execution delay of the instruction in instruction launch standby;
Third step, for read with the queue position of effect queue and the durations such as instruction execution delay of the described instruction in instruction launch standby with effect place value, describedly with effect place value, represent to allow firing order or represent not allow firing order;
The 4th step, for judge read with effect queue, read with effect place value, represent to allow firing order still not allow firing order;
The 5th step, allows the described instruction in instruction launch standby of transmitting while allowing firing order for the value representation reading in described the 4th step judgement;
The 6th step, for after the 5th step, in the position with effect queue and the durations such as instruction execution delay of instruction in instruction launch standby, arrange do not allow firing order with effect place value; And
The 7th step is while not allowing firing order, not allow the described instruction in instruction launch standby of transmitting for the value reading in described the 4th step judgement;
The 8th step, it carries out after described the 6th step or described the 7th step, be used for making described with effect queue to one of queue heads logical shift, and described with effect queue to the position of rear of queue arrange one represent to allow firing order with effect place value.
2. the register write conflict detection method for instruction issue according to claim 1, is characterized in that, described register write conflict detection method is got back to described second step after executing described the 8th step.
3. the register write conflict detection method for instruction issue according to claim 1 and 2, is characterized in that, numerical value " 0 " represent to allow firing order with effect place value, and numerical value " 1 " represent not allow firing order with effect place value.
4. for a register write conflict pick-up unit for instruction issue, it is characterized in that comprising:
Storage unit, wherein stored the longest instruction execution delay of and instruction isometric with effect queue; And
Control module, for carrying out following operation: initially to resetting with effect queue, so as by with effect the Data Position in queue all reset to represent to allow firing order with effect place value; Obtain the instruction execution delay of the instruction in instruction launch standby; Read with in effect queue with the queue position of the durations such as instruction execution delay of the described instruction in instruction launch standby with effect place value, describedly with effect place value, represent to allow firing order or represent not allow firing order; Judgement read with effect queue read with effect place value represent to allow firing order still not allow firing order; When the value representation reading in judgement allows firing order, allow the described instruction in instruction launch standby of transmitting, and in effect queue with the position of the durations such as instruction execution delay of instruction in instruction launch standby arrange do not allow firing order with effect place value; And the value reading in judgement is while not allowing firing order, not allow the described instruction in instruction launch standby of transmitting;
Wherein, described control module is not also for after allowing the described instruction or the described instruction in instruction launch standby of permission transmitting in instruction launch standby of transmitting, make described with effect queue to one of queue heads logical shift, and described with effect queue to the position of rear of queue arrange one represent to allow firing order with effect place value.
5. the register write conflict pick-up unit for instruction issue according to claim 4, is characterized in that, described storage unit is to realize by the register setting of processor.
6. according to the register write conflict pick-up unit for instruction issue described in claim 4 or 5, it is characterized in that, described control module is that the CPU (central processing unit) by processor realizes.
7. one kind has configured according to the processor of the register write conflict pick-up unit for instruction issue one of claim 4 to 6 Suo Shu.
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| CN106537331B (en) * | 2015-06-19 | 2019-07-09 | 华为技术有限公司 | Command processing method and equipment |
| CN108519947A (en) * | 2018-04-02 | 2018-09-11 | 郑州云海信息技术有限公司 | The method and tool of read-write register under a kind of Linux |
| CN109885857B (en) * | 2018-12-26 | 2023-09-01 | 上海合芯数字科技有限公司 | Instruction emission control method, instruction execution verification method, system and storage medium |
| CN109933368B (en) * | 2019-03-12 | 2023-07-11 | 北京市合芯数字科技有限公司 | Method and device for transmitting and verifying instruction |
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| US5835745A (en) * | 1992-11-12 | 1998-11-10 | Sager; David J. | Hardware instruction scheduler for short execution unit latencies |
| CN1545026A (en) * | 2003-11-26 | 2004-11-10 | 中国人民解放军国防科学技术大学 | Dynamic VLIW command dispatching method according to determination delay |
| CN101694627A (en) * | 2009-10-23 | 2010-04-14 | 天津大学 | Compiler system based on TCore configurable processor |
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|---|---|---|---|---|
| US5835745A (en) * | 1992-11-12 | 1998-11-10 | Sager; David J. | Hardware instruction scheduler for short execution unit latencies |
| CN1545026A (en) * | 2003-11-26 | 2004-11-10 | 中国人民解放军国防科学技术大学 | Dynamic VLIW command dispatching method according to determination delay |
| CN101694627A (en) * | 2009-10-23 | 2010-04-14 | 天津大学 | Compiler system based on TCore configurable processor |
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