CN102799419A - Register writing conflict detection method and device, and processor - Google Patents
Register writing conflict detection method and device, and processor Download PDFInfo
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- CN102799419A CN102799419A CN2012103253347A CN201210325334A CN102799419A CN 102799419 A CN102799419 A CN 102799419A CN 2012103253347 A CN2012103253347 A CN 2012103253347A CN 201210325334 A CN201210325334 A CN 201210325334A CN 102799419 A CN102799419 A CN 102799419A
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Abstract
The invention provides a register writing conflict detection method, a register writing conflict detection device and a processor. The register writing conflict detection method comprises the following steps of: initially resetting a writing effective queue; acquiring an instruction execution delay of an instruction; reading a writing effective bit value of a queue position with same duration as the instruction execution delay of the instruction in an instruction ready-transmitting state from the writing effective queue; judging the writing effective bit value read from the writing effective queue; allowing to transmit the instruction in the instruction ready-transmitting state when judging that the read value expresses the allowance of instruction transmission; setting a writing effective bit value for disallowing instruction transmission in the position with the same duration as the instruction execution delay of the instruction in the instruction ready-transmitting state in the writing effective queue; and disallowing to transmit the instruction in the instruction ready-transmitting state when judging that the read value expresses the disallowance of instruction transmission. The invention provides the detection method based on register writing conflict, so that the out-of-order transmission of the instructions can be realized by using less hardware complexity, therefore the efficiency of instruction flow line is improved.
Description
Technical field
The present invention relates to field of computer technology; More particularly; The present invention relates to a kind of register write collision detection method and register write collision-detection means that is used for transmitting instructions; In addition, the invention still further relates to a kind of this register write collision detection method that is used for transmitting instructions or processor of device of having adopted.
Background technology
Modern processors generally adopts pipelining to improve the processing speed of processor.Pipelining is meant many overlapping a kind of accurate parallel processing realization technology of operating of instruction when program is carried out.More particularly, pipelining is divided into a plurality of stages with an execution process instruction, wherein carries out different instruction in different phase, thereby realizes the parallel of instruction, can improve the processing speed of processor thus.
Existing processor pipeline emission mechanism mainly contains two kinds of out of order emission and sequential firing.
On the one hand, common out of order emission mechanism mainly is in order to improve the performance of instruction pipelining.More particularly, under the situation of out of order emission mechanism, as long as instruction is ready, just can firing order, when instruction executes, write physical register file.But the problem of this out of order emission is, because consideration is instructed the opportunity of accomplishing, therefore exists many instructions to write the possibility of physical register file simultaneously, needs a plurality of write ports of realization, thereby has increased the complicacy of physical register file.
On the other hand, common sequential firing mechanism mainly is in order to reduce the complicacy of instruction pipelining.More particularly, in sequential firing mechanism, instruct ready after, could continue after the instruction that wait the front to launch executes the emission.Though sequential firing has reduced the complicacy of physical register file,, also reduced the efficient of instruction pipelining as long as realize a write port.
Therefore, hope can provide a kind of less hardware complicacy capable of using to realize that the out of order emission of instruction improves the technical scheme of the efficient of instruction pipelining.
Summary of the invention
Technical matters to be solved by this invention is to having above-mentioned defective in the prior art, provide a kind of less hardware complicacy capable of using realize the out of order emission of instruction improve instruction pipelining efficient the register write collision detection method that is used for transmitting instructions and adopted this to be used for the processor of the register write collision detection method of transmitting instructions.
According to a first aspect of the invention; A kind of register write collision detection method that is used for transmitting instructions is provided; It comprises: first step; Be used for initially resetting with imitating formation, so as will with imitate Data Position in the formation all reset to expression allow firing order with imitating place value; Second step is used to obtain the instruction execution delay of the instruction that is in the instruction launch standby; Third step, be used for reading with the queue position of imitating formation and the durations such as instruction execution delay of the said instruction that is in the instruction launch standby with imitating place value, saidly represent to allow firing order or expression not to allow firing order with imitating place value; The 4th step, be used to judge read represent to allow firing order still not allow firing order with what imitate that formation reads with imitating place value; The 5th step is used for judging that in said the 4th step the value representation that reads allows the said instruction that is in the instruction launch standby of emission when allowing firing order; The 6th step, be used for after the 5th step with imitate the position of formation with the durations such as instruction execution delay of the instruction that is in the instruction launch standby be provided with do not allow firing order with imitating place value; And the 7th step, be used for judging that in said the 4th step the value that reads does not allow to launch the said instruction that is in the instruction launch standby when not allowing firing order.
Preferably; Also comprise according to the described register write collision detection method that is used for transmitting instructions of first aspect present invention: the 8th step; It is carried out after said the 6th step or said the 7th step; Be used to make said with imitating formation to one of queue heads logical shift, and be provided with in said position with the rear of queue of imitating formation an expression allow firing order with imitating place value.
Preferably, according to the described register write collision detection method that is used for transmitting instructions of first aspect present invention, said register write collision detection method is got back to said second step after executing said the 8th step.
Preferably, according to the described register write collision detection method that is used for transmitting instructions of first aspect present invention, numerical value " 0 " expression allow firing order with imitating place value, and numerical value " 1 " expression do not allow firing order with imitating place value.
According to a second aspect of the invention, providing a kind of has adopted according to the described processor that is used for the register write collision detection method of transmitting instructions of first aspect present invention.
According to a third aspect of the invention we, a kind of register write collision-detection means that is used for transmitting instructions is provided, it comprises: storage unit, wherein stored the longest instruction execution delay of and instruction isometric with imitating formation; And control module, be used to carry out following operation: initially to resetting with imitating formation so that will with imitate Data Position in the formation all reset to expression allow firing order with imitating place value; Obtain the instruction execution delay of the instruction that is in the instruction launch standby; Read with imitate in the formation with the queue position of the durations such as instruction execution delay of the said instruction that is in the instruction launch standby with imitating place value, saidly represent to allow firing order or expression not to allow firing order with imitating place value; What judgement was read representes to allow firing order still not allow firing order with what the effect formation was read with imitating place value; When the value representation permission firing order that judgement is read; Allow the said instruction that is in the instruction launch standby of emission, and with imitate in the formation position with the durations such as instruction execution delay of the instruction that is in the instruction launch standby be provided with do not allow firing order with imitating place value; And the value that reads in judgement does not allow to launch the said instruction that is in the instruction launch standby when not allowing firing order.
Preferably; According to the described register write collision-detection means that is used for transmitting instructions of third aspect present invention; Said control module also be used for do not allow to launch said be in the instruction of instruction launch standby or allow the said instruction that is in the instruction launch standby of emission after; Make said with imitating formation to one of queue heads logical shift, and said with imitate formation to the position of rear of queue be provided with an expression allow firing order with imitating place value.
Preferably, according to the described register write collision-detection means that is used for transmitting instructions of third aspect present invention, said storage unit is to realize through the register setting of processor.
Preferably, according to the described register write collision-detection means that is used for transmitting instructions of third aspect present invention, said control module is that the CPU through processor realizes.
According to a forth aspect of the invention, a kind of described processor that is used for the register write collision-detection means of transmitting instructions of third party according to the present invention that disposed is provided.
According to the present invention,, allow the out of order register file of writing of instruction, thereby improve the efficient of transmitting instructions through using unified judging with imitating queue logic displacement and conflict.More particularly; Transmitting instructions scheme of the present invention is through judging the conflict of writing register file; Use the less hardware expense, allow short delay instruction to surmount the long delay instruction and write register file earlier, realize the out of order register file of writing; Make full use of the write port of register file, thereby improve transmitting instructions efficient.Thus, the present invention provides a kind of detection method and device based on the register write conflict, and the out of order emission of this detection method and device less hardware complicacy realization capable of using instruction is to improve the efficient of instruction pipelining.
Description of drawings
In conjunction with accompanying drawing, and, will more easily more complete understanding be arranged and more easily understand its attendant advantages and characteristic the present invention through with reference to following detailed, wherein:
Fig. 1 schematically shows the process flow diagram of the register write collision detection method that is used for transmitting instructions according to the preferred embodiment of the invention.
Fig. 2 schematically shows according to the preferred embodiment of the invention with the example of imitating formation.
Fig. 3 schematically shows the block diagram of the register write collision-detection means that is used for transmitting instructions according to the preferred embodiment of the invention.
Need to prove that accompanying drawing is used to explain the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure possibly not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear more and understandable, content of the present invention is described in detail below in conjunction with specific embodiment and accompanying drawing.
< first embodiment >
Fig. 1 schematically shows the process flow diagram of the register write collision detection method that is used for transmitting instructions according to the preferred embodiment of the invention.Need to prove that the term in this instructions " register write collision detection " abbreviates the register write collision detection as to promptly being " the write conflict detection " of " physical register file " ".
As shown in Figure 1, the register write collision detection method that is used for transmitting instructions according to the preferred embodiment of the invention comprises:
First step 1 is used for initially (for example when processor starts) to resetting with imitating formation, so as will with imitate Data Position in the formation all reset to expression allow firing order with imitating place value; For example, as shown in Figure 1, can when initial, make with imitating the formation zero clearing, that is, making with the Data Position of imitating in the formation all is zero (in the present embodiment, adopted value " 0 " representes to allow firing order).
Second step 2 when instruction is in " emission is prepared in instruction " state, is obtained the instruction execution delay of this instruction.That is, obtain the instruction execution delay of the instruction that is in " emission is prepared in instruction " state in second step 2.
Specifically, above-mentioned term " instruction prepare emission " is meant such state: the source operand of instruction is ready to, and this instruction and launched that not exist truth to close between the instruction of execution relevant with output, and be somebody's turn to do instruct just wait to be launched.Term " instruction execution delay " is an attribute of instruction, and it just produced before instruction gets into launching phase; Specifically, " instruction execution delay " is meant that an instruction is accomplished execution from being transmitted into, also preparation writes the needed beat number of physical register file, really writes physical register file next beat after this beat number usually.Wherein, physical register file (in this area, sometimes be called for short " register file ") is meant that being used for reading command carries out the action required number, and a kind of storer of the execution result that is used for holding instruction.
Third step 3, read with imitate in the formation with the queue position of the durations such as instruction execution delay of the instruction (that is, being in the instruction of " emission is prepared in instruction " state) of this preparations emission with the effect place value.Wherein, with effect place value or expression permission firing order, or expression does not allow firing order.In other words, follow-up will through read with imitate in the formation with the queue position of the durations such as instruction execution delay of the instruction of this preparations emission judge whether to launch this instruction with imitating place value.
Need to prove that term " waits the queue position of duration " and refers to imitating in the formation team and postpones (for example instruction execution delay) arrival with the position of imitating the formation queue heads through corresponding.
The 4th step 4, judge read with imitate that formation reads with imitating place value.What specifically, judgement was read representes that with imitating place value " permission firing order " still is " not allowing firing order " with what the effect formation was read.
The 5th step 5, if in the 4th step 4, judge the value read for " 0 " (in the present embodiment expression allow firing order with imitating place value), then allow the emission should instruction.
The 6th step 6, it is carried out after the 5th step 5, be used for imitate formation and this firing order carry out the position set that delays wait duration (in the present embodiment expression do not allow firing order with the effect place value).Thus, can to the instruction execution delay of all instructions be provided with long instruction in the and instruction carry out postpone isometric with imitating formation." the long instruction of and instruction carry out postpone isometric " refers to, and when carrying out through long instruction when postponing, just in time is displaced to queue heads with the data of the rear of queue of imitating formation.
When passing through operating cycle of said register write collision detection method, carry out one logical shift (as shown in Figure 2) to queue heads B direction with imitating formation along formation sense of displacement X.
Through combining the 5th step 5 and the 6th step 6, can find out, when with the queue heads B position of imitating formation with imitating place value when being " 1 "; Show that current beat has the result to prepare to write back register file (promptly; Allow the instruction of emission after corresponding instruction is carried out delay, will write physical register file in the 5th step 5, and this moment, " 1 " that in the 6th step 6, is provided with just in time is in the queue heads B position of imitating formation); Correspondingly, should not allow firing order.
The 7th step 7, if in the 4th step 4, judge the value read for " 1 " (in the present embodiment expression do not allow firing order with imitating place value), do not allow this instruction of emission.Thus, can guarantee can not have a plurality of instructions of writing same register file clauses and subclauses to be in the state that register is operated and (avoid the register write conflict).
The 8th step 8, it is carried out after said the 6th step 6 or said the 7th step 7, is used for making with imitating formation to queue heads B logical shift, moves 1.Concrete, in the 8th step 8 because to queue heads B displacement, be provided with in the position of rear of queue A an expression allow firing order with imitating place value (being numerical value " 0 " in the present embodiment).
After the 8th step 8, get back to second step 2.After this, repeat the operating cycle of second step 2 to the 8th step 8.
In above-mentioned register write collision detection method,, allow the out of order register file of writing of instruction, thereby improve the efficient of transmitting instructions through using unified judging with imitating queue logic displacement and conflict.More particularly; The disclosed transmitting instructions method of the above embodiment of the present invention is through judging the conflict of writing register file; Use the less hardware expense, allow short delay instruction to surmount the long delay instruction and write register file earlier, realize the out of order register file of writing; Make full use of the write port of register file, thereby improve transmitting instructions efficient.
Thus, the above embodiment of the present invention provides a kind of detection method based on the register write conflict, and this detection method less hardware complicacy capable of using realizes the out of order emission of instruction, to improve the efficient of instruction pipelining.
Need to prove, though the foregoing description with numerical value " 0 " expression allow firing order with imitating place value, and with numerical value " 1 " expression do not allow firing order with imitating place value; But, represent it also is feasible conversely, that is to say, in another embodiment, can with numerical value " 1 " expression allow firing order with imitating place value, and with numerical value " 0 " expression do not allow firing order with imitating place value.
According to another preferred embodiment of the invention, the present invention also provides a kind of above-mentioned processor that is used for the register write collision detection method of transmitting instructions, for example microprocessor of having adopted.
< second embodiment >
Fig. 3 schematically shows the block diagram of the register write collision-detection means that is used for transmitting instructions according to the preferred embodiment of the invention.
As shown in Figure 2, the register write collision-detection means 100 that is used for transmitting instructions according to the preferred embodiment of the invention comprises:
Storage unit 1, wherein stored the longest instruction execution delay of and instruction isometric with imitating formation 11; And
Control module 2 is used to carry out the register write collision detection method that is used for transmitting instructions according to the preferred embodiment of the invention shown in Figure 1.
Wherein, To instruction execution delay be provided with the longest instruction execution delay of an and instruction isometric with imitating formation 11; Should carry out one logical shift to per operating cycle of the register write collision detection method that is used for transmitting instructions according to the preferred embodiment of the invention shown in Figure 1 to queue heads B direction (formation sense of displacement X) with imitating formation 11; When queue heads B when writing significance bit for for example " 1 ", showing when clapping have the result to prepare to write back register file.As shown in Figure 2, carry out logical shift by rear of queue A to queue heads B with imitating formation, whenever move one, " 0 " is mended in the position of rear of queue A.
Wherein, storage unit 1 can realize through original register setting of processor, and need not to increase extraly storage medium.Control module 2 can realize through original processing and control element (PCE) of processor, CPU for example, and need not to increase extraly processing and control element (PCE).
More particularly, control module 2 is used to carry out following operation: initially to resetting with imitating formation so that will with imitate Data Position in the formation all reset to expression allow firing order with imitating place value; Obtain the instruction execution delay of the instruction that is in the instruction launch standby; Read with imitate in the formation with the queue position of the durations such as instruction execution delay of the said instruction that is in the instruction launch standby with imitating place value, saidly represent to allow firing order or expression not to allow firing order with imitating place value; What judgement was read representes to allow firing order still not allow firing order with what the effect formation was read with imitating place value; When the value representation permission firing order that judgement is read; Allow the said instruction that is in the instruction launch standby of emission, and with imitate in the formation position with the durations such as instruction execution delay of the instruction that is in the instruction launch standby be provided with do not allow firing order with imitating place value; And the value that reads in judgement does not allow to launch the said instruction that is in the instruction launch standby when not allowing firing order.
Thus; Control module 2 also is used in not allow to launch and saidly is in the instruction of instruction launch standby or allows after the said instruction that is in the instruction launch standby of emission; Make with imitating formation 11 to one of queue heads logical shift, and said with imitate formation to the position of rear of queue be provided with an expression allow firing order with imitating place value.
Equally, preferably, with numerical value " 0 " expression allow firing order with imitating place value, and with numerical value " 1 " expression do not allow firing order with imitating place value; Replacedly, represent it also is feasible conversely, that is to say, in another embodiment, can with numerical value " 1 " expression allow firing order with imitating place value, and with numerical value " 0 " expression do not allow firing order with imitating place value.
Therefore, similarly, in above-mentioned register write collision-detection means,, allow the out of order register file of writing of instruction, thereby improve the efficient of transmitting instructions through using unified judging with imitating queue logic displacement and conflict.More particularly; The above embodiment of the present invention is through judging the conflict of writing register file; Use the less hardware expense, allow short delay instruction to surmount the long delay instruction and write register file earlier, realize the out of order register file of writing; Make full use of the write port of register file, thereby improve transmitting instructions efficient.
Thus, the above embodiment of the present invention provides a kind of pick-up unit based on the register write conflict, and this detection method less hardware complicacy capable of using realizes the out of order emission of instruction, to improve the efficient of instruction pipelining.
According to another preferred embodiment of the invention, the present invention also provides a kind of above-mentioned processor that is used for the register write collision-detection means of transmitting instructions, for example microprocessor of disposing.
Need to prove; Descriptions such as the term in the instructions " first ", " second ", " the 3rd " only are used for distinguishing each assembly, element, step of instructions etc., rather than are used to represent logical relation or ordinal relation between each assembly, element, the step etc.
It is understandable that though the present invention with the preferred embodiment disclosure as above, yet the foregoing description is not in order to limit the present invention.For any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the technology contents of above-mentioned announcement capable of using is made many possible changes and modification to technical scheme of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (10)
1. register write collision detection method that is used for transmitting instructions is characterized in that comprising:
First step is used for initially resetting with imitating formation, so as will with imitate Data Position in the formation all reset to expression allow firing order with imitating place value;
Second step is used to obtain the instruction execution delay of the instruction that is in the instruction launch standby;
Third step, be used for reading with the queue position of imitating formation and the durations such as instruction execution delay of the said instruction that is in the instruction launch standby with imitating place value, saidly represent to allow firing order or expression not to allow firing order with imitating place value;
The 4th step, be used to judge read represent to allow firing order still not allow firing order with what imitate that formation reads with imitating place value;
The 5th step is used for judging that in said the 4th step the value representation that reads allows the said instruction that is in the instruction launch standby of emission when allowing firing order;
The 6th step, be used for after the 5th step with imitate the position of formation with the durations such as instruction execution delay of the instruction that is in the instruction launch standby be provided with do not allow firing order with imitating place value; And
The 7th step is used for judging that in said the 4th step the value that reads is not allow to launch the said instruction that is in the instruction launch standby when not allowing firing order.
2. the register write collision detection method that is used for transmitting instructions according to claim 1 is characterized in that also comprising:
The 8th step; It is carried out after said the 6th step or said the 7th step; Be used to make said with imitating formation to one of queue heads logical shift, and said with imitate formation to the position of rear of queue be provided with an expression allow firing order with imitating place value.
3. the register write collision detection method that is used for transmitting instructions according to claim 1 and 2 is characterized in that, said register write collision detection method is got back to said second step after executing said the 8th step.
4. the register write collision detection method that is used for transmitting instructions according to claim 1 and 2 is characterized in that, numerical value " 0 " expression allow firing order with imitating place value, and numerical value " 1 " expression do not allow firing order with imitating place value.
5. one kind has been adopted according to the described processor that is used for the register write collision detection method of transmitting instructions of one of claim 1 to 4.
6. register write collision-detection means that is used for transmitting instructions is characterized in that comprising:
Storage unit, wherein stored the longest instruction execution delay of and instruction isometric with imitating formation; And
Control module is used to carry out following operation: initially to resetting with imitating formation so that will with imitate Data Position in the formation all reset to expression allow firing order with imitating place value; Obtain the instruction execution delay of the instruction that is in the instruction launch standby; Read with imitate in the formation with the queue position of the durations such as instruction execution delay of the said instruction that is in the instruction launch standby with imitating place value, saidly represent to allow firing order or expression not to allow firing order with imitating place value; What judgement was read representes to allow firing order still not allow firing order with what the effect formation was read with imitating place value; When the value representation permission firing order that judgement is read; Allow the said instruction that is in the instruction launch standby of emission, and with imitate in the formation position with the durations such as instruction execution delay of the instruction that is in the instruction launch standby be provided with do not allow firing order with imitating place value; And the value that reads in judgement does not allow to launch the said instruction that is in the instruction launch standby when not allowing firing order.
7. the register write collision-detection means that is used for transmitting instructions according to claim 6; It is characterized in that; Said control module also be used for do not allow to launch said be in the instruction of instruction launch standby or allow the said instruction that is in the instruction launch standby of emission after; Make said with imitating formation to one of queue heads logical shift, and said with imitate formation to the position of rear of queue be provided with an expression allow firing order with imitating place value.
8. according to claim 6 or the 7 described register write collision-detection means that are used for transmitting instructions, it is characterized in that said storage unit is to realize through the register setting of processor.
9. according to claim 6 or the 7 described register write collision-detection means that are used for transmitting instructions, it is characterized in that said control module is that the CPU through processor realizes.
10. one kind has been disposed according to the described processor that is used for the register write collision-detection means of transmitting instructions of one of claim 6 to 9.
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| CN106537331A (en) * | 2015-06-19 | 2017-03-22 | 华为技术有限公司 | Instruction processing method and device |
| CN108519947A (en) * | 2018-04-02 | 2018-09-11 | 郑州云海信息技术有限公司 | The method and tool of read-write register under a kind of Linux |
| CN109885857A (en) * | 2018-12-26 | 2019-06-14 | 苏州中晟宏芯信息科技有限公司 | Instruction issue control method, instruction execution verification method, system and storage medium |
| CN109933368A (en) * | 2019-03-12 | 2019-06-25 | 苏州中晟宏芯信息科技有限公司 | A kind of transmitting of instruction and verification method and device |
| CN114047955A (en) * | 2021-11-29 | 2022-02-15 | 上海阵量智能科技有限公司 | Instruction transmitting apparatus, method, chip, computer device, and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106537331A (en) * | 2015-06-19 | 2017-03-22 | 华为技术有限公司 | Instruction processing method and device |
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