CN101566942B - Flying scoreboard device for controlling out-order transmission in superscale microprocessor - Google Patents
Flying scoreboard device for controlling out-order transmission in superscale microprocessor Download PDFInfo
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- CN101566942B CN101566942B CN2009100573676A CN200910057367A CN101566942B CN 101566942 B CN101566942 B CN 101566942B CN 2009100573676 A CN2009100573676 A CN 2009100573676A CN 200910057367 A CN200910057367 A CN 200910057367A CN 101566942 B CN101566942 B CN 101566942B
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Abstract
The invention discloses a flying scoreboard device for controlling out-order transmission in a superscale microprocessor, comprising a flying scoreboard mapping table, a flying scoreboard recovering list and a flying scoreboard state table. For an effective command of a target register, the device tracks the state of the command target register dynamically; for an effective command of a source register, the device provides information whether the command source register is readable in real time to judge whether the command can be transmitted to an executive component. The device solves read-after-write relevance caused by use of a register between commands through less hardware resources, ensures accuracy of out-order transmission and execution of commands, and improves the energy consumption ratio of the microprocessor.
Description
Technical field
The present invention relates to the instruction pipelining design of superscalar microprocessor.
Background technology
Instruction pipelining is the core of microprocessor, and the height of its performance is most important.Current superscalar microprocessor instruction pipelining is all supported out of order emission and out of order execution; Instruction pipelining generally includes several basic streamline platforms such as get finger, decoding, register renaming, emission, read register, carry out, withdraw from; Wherein register renaming is again that technology content is the highest on the instruction streamline with the emission platform; The part that area and power consumption account for the largest percentage directly influences the ability loss-rate of instruction pipelining.
What use in the instruction is logic register, and same logic register is write in two instructions in front and back, representes to exist between these two instructions write after write relevant; Last a logic register is read in instruction, and same logic register is write in a back instruction, representes to exist between these two instructions writeafterread relevant; Last a logic register is write in instruction, and same logic register is read in a back instruction, representes to exist between these two instructions read-after-write relevant.In order to realize out of order emission, the register renaming platform need complement each other with the emission platform, and it is relevant relevant with writeafterread to remove write after write, and it is relevant to keep read-after-write.The quantity of the logic register that software is visible very limited (supposing that quantity is n); Exist the relevant situation relevant of write after write very frequent between the instruction with writeafterread; For this reason the superscalar microprocessor set inside a large amount of physical registers (supposing that quantity is m), be used to instruct the temporary and Data transmission of run duration.
The device of traditional out of order emission of control is at the register renaming platform physical register mapping table to be set; Record logic register and the nearest mapping relations of physical register; Simultaneously; Physical register also is set recovers tabulation, recover physical register mapping table when being used for the branch prediction failure and instructing generation unusual.At the emission platform physical register state table is set, writes down the state of each physical register.
When initial, n logic register fixedly is mapped to n physical register, m-n idle physical register of residue.When a destination register effectively instructs entering register renaming platform, obtain the idle physical register that really can write.When this instruction got into the emission platform, it was blockage that the physical register of writing is set.When instruction is about to when complete, remove the blockage of the physical register of writing.When a source-register effectively instructs entering register renaming platform, obtain real readable physical register.When emission was prepared in this instruction, whether inquiry institute reading matter reason register was blocked, if block, representes that then source-register does not also have up-to-date value, and instruction can not be launched into the execution platform; If do not block, then represent existing up-to-date value in the source-register, instruction can be launched into the execution platform.
Passed through register renaming, but the instruction of also not withdrawing from is called the instruction of flight, leaves in the reorder buffer.Receive the restriction of register renaming mechanism, the effective instruction number of the destination register of flight equals maximum idle physical register number (m-n) at most, and the read-after-write that the emission platform only need be controlled between these flight directives is relevant, m-n position scoreboard promptly is set in theory gets final product.Traditional out of order control device is provided with m position scoreboard; Each corresponding physical register in any moment, all has at least n position scoreboard not play a role; There is waste in the expense that this means area and power consumption, and the delay of visit physical register state table is also very long.
Summary of the invention
The technical matters that the present invention will solve is how under the prerequisite that does not influence microprocessor performance, and minimum scoreboard figure place is set, and the read-after-write that solves between the instruction because of using register to cause is relevant, guarantees the correctness of out of order emission of instruction and out of order execution.
For solving the problems of the technologies described above; Flight scoreboard device of the present invention adopts following technical scheme to realize: this device comprises a flight scoreboard mapping table, a flight scoreboard recovering and a flight scoreboard state table; Wherein: described each logic register of flight scoreboard mapping table record and the nearest mapping relations of the trade mark of keeping the score of flying; Described flight scoreboard recovering has write down the target logic register and the last mapping relations of the trade mark of keeping the score of flying of all flight directives; Recover the flight scoreboard mapping table and the scoreboard state table that flies when being used for the transfer instruction prediction of failure and instructing generation unusual; Described flight scoreboard state table has write down the target physical buffer status of flight directive, and whether the instruction that this physical register is read in control allows to be launched into execution unit; When a destination register effectively instructs when this device, obtain flight trade mark of keeping the score by the order that arrives, and be set to blockage, be about to complete last bat in instruction, remove the blockage of the corresponding scoreboard that flies; When a source-register effectively instructs through this device, whether need check flight scoreboard state when judging this transmitting instructions, if do not need inspection, the flight scoreboard that maybe need check is not blocked, then instruction allows to be launched into execution unit; When branch prediction failure or instruction exception took place, will fly through the scoreboard recovering of reading to fly, the scoreboard device returned to transfer instruction or exceptional instructions is carried out state before.
Adopt flight scoreboard device of the present invention; The scoreboard figure place that is used for the out of order emission of steering order equals maximum idle physical register number; Scoreboard device compared with traditional has reduced area and power consumption, and it is short to have shortened critical path delay; Under the prerequisite that does not influence microprocessor performance, improved the ability loss-rate of chip.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is the position view of flight scoreboard device on whole instruction pipelining among the present invention.
Fig. 2 is the flight scoreboard mapping table and flight scoreboard recovering structural representation that is provided with in the register renaming platform among the present invention.
Fig. 3 is the flight scoreboard state table structural representation that is provided with in the emission platform among the present invention.
Embodiment
As shown in Figure 1, device of the present invention need be provided with a flight scoreboard mapping table and a flight scoreboard recovering at the register renaming platform, at the emission platform flight scoreboard state table is set.
As shown in Figure 2; Flight scoreboard mapping table has write down logic register and the nearest mapping relations of flight scoreboard, and entry number equals logic register number (n), and each clauses and subclauses comprises significance bit and the flight trade mark of keeping the score; Significance bit is used 1 bit representation, and the flight trade mark of keeping the score is used log
2(m-n) bit representation.Significance bit is " 0 ", and the source-register of presentation directives is ready to already, and instruction need not be inquired about flight scoreboard state table when emission; Significance bit is " 1 ", and the source-register of presentation directives possibly also be not ready for, and instruction need be inquired about flight scoreboard state table when emission.
As shown in Figure 2; The flight scoreboard recovering has write down the target logic register and the last mapping relations of the trade mark of keeping the score of flying of all flight directives; Recover the flight scoreboard mapping table and the scoreboard state table that flies when being used for the transfer instruction prediction of failure and instructing generation unusual; Entry number equals maximum idle physical register number (m-n), and each clauses and subclauses is deposited logic register number, significance bit and the flight trade mark of keeping the score.Logic register number is used log
2(n) bit representation, significance bit are used 1 bit representation, and the flight trade mark of keeping the score is used log
2(m-n) bit representation.The flight scoreboard recovering is provided with the recovery head pointer respectively and manages with the recovery tail pointer as the round-robin queue of first in first out, and pointer is all used log
2(m-n) bit representation recovers the clauses and subclauses that head pointer indicates formation, recovers the clauses and subclauses that tail pointer is indicated into formation.
As shown in Figure 3; Flight scoreboard state table has write down the physical register state of flight directive; Entry number equals maximum idle physical register number (m-n), and each clauses and subclauses comprises blocks sign and remove the blockade counter, blocks sign and uses a bit representation; The maximum cycle number that the figure place and instruction of counter of lifting a blockade is carried out is relevant, and the maximal value that the counter of lifting a blockade can be represented equals to instruct the maximum cycle number of execution.Locking bit is " 0 ", and expression is read the keep the score instruction of the trade mark of this flight and can be launched; Blockade is masked as " 1 ", and expression is read the keep the score instruction of the trade mark of this flight and cannot be launched.When the counter of lifting a blockade for " 0 ", when also be not maximal value, every bat is carried out and is subtracted " 1 " and operates, when lifting a blockade counter when " 1 " is kept to " 0 ", the blockade of putting these clauses and subclauses is masked as " 0 ".
When initial, the significance bit of all clauses and subclauses is " 0 " in the flight scoreboard mapping table, and recovering head pointer all is " 0 " with recovering tail pointer, and all clauses and subclauses are blocked and are masked as " 0 " in the flight scoreboard state table, and the value of the counter of lifting a blockade is " 0 ".
When a destination register effectively instructs arrival register renaming platform; The value of recovering tail pointer is distributed to the destination register of instruction as the flight trade mark of keeping the score; Earlier with the newly assigned flight trade mark complete association inquiry scoreboard mapping table that flies of keeping the score; If find flight in certain clauses and subclauses trade mark and the newly assigned flight trade mark of keeping the score of keeping the score identical, the significance bit of then putting clauses and subclauses is " 0 ".Then with destination register index flight scoreboard mapping table; Earlier the keep the score trade mark and destination register of significance bit original in the clauses and subclauses, flight number write in the flight scoreboard recovering together; And will recover tail pointer and add " 1 "; The flight that will obtain the then trade mark of keeping the score writes in the flight scoreboard mapping table clauses and subclauses, puts significance bit and is " 1 ".When this instruction arrived emission platform, with the flight that the obtains trade mark index flight scoreboard state table of keeping the score, the blockade that clauses and subclauses are set was masked as " 1 ".When this transmitting instructions; If this instruction is non-memory-reference instruction; Then the performance period with instruction writes in the counter of lifting a blockade of clauses and subclauses after subtracting " 1 ", and later counter automatically performs and subtracts " 1 " operation, and is about to remove when complete the flight scoreboard in instruction; If this instruction is an access instruction, then maximal value is write in the counter of lifting a blockade of clauses and subclauses, counter is not carried out and is subtracted " 1 " operation, is being about to remove the flight scoreboard when complete by the memory access parts.When this instruction is withdrawed from, will recover head pointer and add " 1 ".
When a source-register effectively instructs when arriving the register renaming platform, with source-register index flight scoreboard mapping table, the significance bit in the clauses and subclauses and the flight trade mark of keeping the score is sent to the emission platform with instructing, deposit the emission formation in.When emission was prepared in this instruction, if significance bit is " 0 ", then this instruction can be launched; If significance bit is " 1 ", use the flight of the being read trade mark index flight scoreboard state table of keeping the score, be masked as " 0 " if block, then this instruction can be launched; If block and be masked as " 1 ", then this instruction cannot be launched, and will continue in the emission formation, to wait for.
In superscalar microprocessor, when the branch prediction failure takes place, the state that requirement has just executed recovering states all on the streamline to transfer instruction immediately, and need not wait until that transfer instruction withdraws from.Infer after the transfer instruction and carried out a lot of bar instructions, these instructions have produced destruction to flight scoreboard device, and flight scoreboard device must recover before new instruction arrives.During every transfer instruction process register renaming platform, all carried recovery tail pointer value at that time.When the branch prediction failure takes place, need all mapping relations between the recovery tail pointer that current recovery tail pointer of rollback and transfer instruction carry.Restoration methods is; Begin to read the scoreboard recovering of flying from current recovery tail pointer,, significance bit in the clauses and subclauses and the flight trade mark of keeping the score is write in the scoreboard mapping table that flies with the logic register index in clauses and subclauses flight scoreboard mapping table; And notice flight scoreboard state table; Put corresponding the blockade and be masked as " 0 ", then current recovery tail pointer is subtracted " 1 ", till the value of current recovery tail pointer equals recovery tail pointer value that transfer instruction carries.
Occur when withdrawing from unusually if instruct, also require recovering states all on the streamline is carried out state before to this instruction, need all mapping relations between current recovery tail pointer of rollback and the current recovery head pointer, the similar branch prediction failure of restoration methods.
The difference of the flight scoreboard device among the present invention and traditional out of order emitter of control is: in the out of order emitter of traditional control; The scoreboard figure place equals physical register number (m); During directly with physical register index physical register state table, all instructions of writing same physical register are provided with the same memorial tablet of keeping the score.In the flight scoreboard device among the present invention, the scoreboard figure place equals idle physical register number (m-n), the trade mark index flight scoreboard state table of keeping the score with flying.Flight is kept the score the trade mark by instructing the order that arrives the register renaming platform to distribute successively, and all instructions of writing same physical register not necessarily are provided with the same memorial tablet of keeping the score.
Claims (5)
1. the flight scoreboard device of the out of order emission of control in the superscalar microprocessor; It is characterized in that: the register renaming platform that this device is included in described superscalar microprocessor is provided with a flight scoreboard mapping table and a flight scoreboard recovering; At the emission platform flight scoreboard state table is set, described each logic register of flight scoreboard mapping table record and the nearest mapping relations of the trade mark of keeping the score of flying; Described flight scoreboard recovering has write down the target logic register and the last mapping relations of the trade mark of keeping the score of flying of all flight directives; Recover the flight scoreboard mapping table and the scoreboard state table that flies when being used for the transfer instruction prediction of failure and instructing generation unusual; The entry number of flight scoreboard recovering equals the quantity of maximum idle physical register; Each clauses and subclauses comprises a logic register number, a significance bit and flight trade mark of keeping the score; Described flight scoreboard state table has write down the target physical buffer status of flight directive; Whether the instruction that this physical register is read in control allows to be launched into execution unit; The entry number of flight scoreboard state table equals the quantity of maximum idle physical register, and each clauses and subclauses comprises one and blocks sign and the counter of lifting a blockade.
2. flight scoreboard device as claimed in claim 1; It is characterized in that: the entry number of described flight scoreboard mapping table equals the quantity of logic register; Each clauses and subclauses comprises a significance bit and flight trade mark of keeping the score, and significance bit is " 0 ", during the presentation directives emission without check flight scoreboard state table; Significance bit is " 1 "; Presentation directives's emission the time needs check flight scoreboard state table, and the flight maximal value that the trade mark can represent of keeping the score adds the quantity that " 1 " equals maximum idle physical register, each flight trade mark correspondence clauses and subclauses in the scoreboard state table of flying of keeping the score.
3. flight scoreboard device as claimed in claim 1; It is characterized in that: when a destination register effectively instructs when arriving the register renaming platform, the value of recovering tail pointer is distributed to this instruction as the flight trade mark of keeping the score, and with the newly assigned flight trade mark complete association inquiry scoreboard mapping table that flies of keeping the score; If find flight in certain clauses and subclauses trade mark and the newly assigned flight trade mark of keeping the score of keeping the score identical; The significance bit of then putting clauses and subclauses is " 0 ", then with destination register index flight scoreboard mapping table, earlier with significance bit original in the clauses and subclauses, the keep the score trade mark and the destination register of flying number write the flight scoreboard recovering together; And will recover tail pointer and add " 1 "; The flight that will obtain the then trade mark of keeping the score writes in the flight scoreboard mapping table clauses and subclauses, puts significance bit and is " 1 ", when instruction arrives the emission platform; With the flight that the obtains trade mark index flight scoreboard state table of keeping the score; The blockade of putting in the entry is masked as " 1 ", when instruction is withdrawed from, recovers the tabulation head pointer and adds " 1 ".
4. flight scoreboard device as claimed in claim 1; It is characterized in that: when a source-register effectively instructs arrival register renaming platform; With source-register index flight scoreboard mapping table, significance bit in the clauses and subclauses and the flight trade mark of keeping the score is sent to the emission platform with instruction, when this instruction prepares to launch; If significance bit is " 0 "; Then should instruction allow emission,, then determine whether allowing emission according to the blockade sign in the correspondence flight scoreboard state table if significance bit is " 1 ".
5. flight scoreboard device as claimed in claim 1; It is characterized in that: during every transfer instruction process register renaming platform; Carry current recovery tail pointer value; When the branch prediction failure takes place when; Read all the flight scoreboard recovering clauses and subclauses between the recovery tail pointer that current recovery tail pointer and transfer instruction carry successively, significance bit and the flight trade mark of keeping the score is write in the flight scoreboard mapping table of the logic register index that is write down, and remove the keep the score blockade of the trade mark of this flight; When the instruction generation is unusual; Read all the flight scoreboard recovering clauses and subclauses between current recovery tail pointer and the current recovery head pointer successively; The significance bit and the flight trade mark of keeping the score are write in the flight scoreboard mapping table of the logic register index that is write down, and remove the keep the score blockade of the trade mark of this flight.
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| US8661230B2 (en) * | 2011-04-15 | 2014-02-25 | International Business Machines Corporation | Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions |
| US9182986B2 (en) * | 2012-12-29 | 2015-11-10 | Intel Corporation | Copy-on-write buffer for restoring program code from a speculative region to a non-speculative region |
| CN104536914B (en) * | 2014-10-15 | 2017-08-11 | 中国航天科技集团公司第九研究院第七七一研究所 | The associated processing device and method marked based on register access |
| US9715390B2 (en) * | 2015-04-19 | 2017-07-25 | Centipede Semi Ltd. | Run-time parallelization of code execution based on an approximate register-access specification |
| US10108417B2 (en) * | 2015-08-14 | 2018-10-23 | Qualcomm Incorporated | Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor |
| CN111290786B (en) * | 2018-12-12 | 2022-05-06 | 展讯通信（上海）有限公司 | Information processing method, device and storage medium |
| CN110297662B (en) * | 2019-07-04 | 2021-11-30 | 中昊芯英(杭州)科技有限公司 | Method for out-of-order execution of instructions, processor and electronic equipment |
| CN110647361B (en) * | 2019-09-09 | 2021-08-27 | 中国人民解放军国防科技大学 | Method and device for acquiring idle physical register |
| CN111857830B (en) * | 2020-06-05 | 2023-09-22 | 上海赛昉科技有限公司 | Method, system and storage medium for designing path for forwarding instruction data in advance |
| CN114327644B (en) * | 2022-03-16 | 2022-06-03 | 广东省新一代通信与网络创新研究院 | Method for realizing processor to predict memory access correlation |
| CN115599445B (en) * | 2022-11-25 | 2023-04-07 | 太初(无锡)电子科技有限公司 | Method for executing out-of-order instructions |
| CN116700792B (en) * | 2023-06-09 | 2024-03-08 | 合芯科技有限公司 | Mapping method, structure, storage medium and chip of instruction stream register |
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