CN105528195B - A kind of flight scoreboard processing method for supporting simultaneous multi-threading to instruct out of order transmitting - Google Patents

A kind of flight scoreboard processing method for supporting simultaneous multi-threading to instruct out of order transmitting Download PDF

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CN105528195B
CN105528195B CN201510883067.9A CN201510883067A CN105528195B CN 105528195 B CN105528195 B CN 105528195B CN 201510883067 A CN201510883067 A CN 201510883067A CN 105528195 B CN105528195 B CN 105528195B
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flight
register
trade mark
scoreboard
free
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CN105528195A (en
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尹飞
胡向东
李俊
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Shanghai Integrated Circuits with Highperformance Center
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Shanghai Integrated Circuits with Highperformance Center
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094Condition code generation, e.g. Carry, Zero flag
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Abstract

The present invention relates to a kind of flight scoreboard processing method for supporting simultaneous multi-threading to instruct out of order transmitting, this method be provided with free physical registers quantity identical flight scoreboard, and the trade mark of scoring of flying is bound with idle physical register number.When instruction carries out register renaming, the flight trade mark of scoring is assigned to the destination register of instruction together with the free physical registers number of binding;Instruct submit when, the flight that currently the distributes trade mark of scoring is unbinding with the physical register number that currently distributes, and flight free physical registers number that the trade mark newly discharges with instruction of scoring are bound again;Instruct retract when, the flight that currently the distributes trade mark of scoring is recovered together with the physical register number currently distributed, and the physical register number that the trade mark is scored in the flight for recovering the last distribution of its destination register and the last time distributes.The present invention is solved in the case of multiple threads while execution and sharing same set of physical register, the out of order transmitting problem of instruction.

Description

A kind of flight scoreboard processing method for supporting simultaneous multi-threading to instruct out of order transmitting
Technical field
The present invention relates to multiple threads technical field, supports simultaneous multi-threading to instruct out of order transmitting more particularly to one kind Flight scoreboard processing method.
Background technology
Instruction in same thread generates correlation because accessing identical logic register.Front and rear two instructions are write Same logic register, represent write after write (WAW) correlation be present between this two instructions;Previous bar instruction is read a logic and posted Same logic register is write in storage, latter bar instruction, represents writeafterread (WAR) correlation be present between this two instructions;It is previous A logic register is write in bar instruction, and same logic register is read in latter bar instruction, represents to exist between this two instructions to write It is related that (RAW) is read afterwards.In order to improve the degree of parallelism that instruction performs, current microprocessor all by register renaming technology, By on a small amount of logic register dynamic mapping to more physical register, read-after-write between reserve statement is related Meanwhile releasing write after write is related related to writeafterread, and out of order transmitting is realized to instruct, and improves microprocessor execution efficiency.
The instruction pipeline of superscalar microprocessor is typically divided into:Fetching, decoding, register renaming, transmitting, reading are posted Register file, execution, submit several streamline platforms.For convenience, all entry instruction streamlines are but without submission Instruction be referred to as flight instruction.
Patent《The flight flying scoreboard device of out of order transmitting is controlled in a kind of superscalar microprocessor》(code name: ZL200910057367.6 the concept of flight scoreboard) is introduced in instruction pipeline design first, by setting and the free time The flight of physical register quantity identical is scored memorial tablet, is represented with the shorter flight of digit trade mark sub reason register number of scoring Read-after-write between instruction is related, realizes and instructs out of order transmitting.For the effective instruction of destination register, launch queue entering When, then it will be arranged to masked state by flight memorial tablet of scoring corresponding to its destination register, it will be write when the instruction performs completion During destination register, the memorial tablet of scoring of flight corresponding to it is arranged to non-shielding state.For the effective instruction of source register, When preparing transmitting, check whether flight scoreboard corresponding to its source register is in masked state, only in non-shielding state Just represent that the value in its source register is readable, the instruction can be transmitted into execution unit execution.
With the development of integrated circuit processing technique, Simultaneous multithreading technology (SMT:Simultaneous Multithreading) arise at the historic moment.The technology makes full use of the Thread-Level Parallelism of program, it is allowed to is sent out within a clock cycle Penetrate and perform a plurality of instruction from different threads, the utilization rate of groove and functional part is launched by improving processor, to show The execution efficiency for improving processor is write, is the key technology of present microprocessor structure design.
In order to improve the utilization rate of hardware resource, it is former to have formulated following design when realizing SMT technologies for instruction pipeline Then:
Different threads has each independent logic register, but shares same set of physical register;
Instruction from different threads can be transmitted into different execution units simultaneously;
When one thread generation branch prediction fails or be abnormal, only retract processor state corresponding to the thread, other lines Cheng Jixu is normally performed.
Each destination register effectively instructs one idle physical register of distribution in register renaming, is carrying An idle physical register is discharged during friendship.Before SMT technologies are supported, all instructions on instruction pipeline both are from together One thread, instruct the order of submission identical with instructing the order of renaming and identical all with instructing order in a program, because This is such as patent《The flight flying scoreboard device of out of order transmitting is controlled in a kind of superscalar microprocessor》Described, the flight of distribution is scored The trade mark is exactly that instruction reaches free physical registers number on the serial number mould of register renaming platform.It is assumed that free physical is deposited Device quantity is n, then the quantity of flight scoreboard is also n, and the flight trade mark of scoring distributes since " 0 ", successively plus " 1 ", is assigned to After " n-1 ", then from " 0 " start the cycle over distribution.Why correct this flight scoreboard distribution method is, and its reason is:Certain Destination register effectively instructs i to be assigned with flight and scored trade mark Fi, and follow-up nth bar destination register effectively instructs n+i to permit When carrying out register renaming perhaps, instruction i has been filed on and releases a free physical registers, the corresponding trade mark of scoring that flies Fi is meaningless, and Fi, which can discharge and be reassigned to new instruction, to be used.
After supporting SMT technologies, same set of physical register, the quantity ratio of physical register are shared in the instruction of different threads Support more before SMT technologies.If by traditional scoreboard processing method, scoreboard is directly used as using physical register number Number, then hardware spending is bigger.Now the flight scoreboard processing method in above-mentioned patent is no longer applicable, and its reason is:Come from When the instruction of different threads staggeredly performs, instruct the order of submission different from the order of command register renaming, certain target Register effectively instructs i to be assigned with flight and scored trade mark Fi, follow-up nth bar destination register effectively instruct n+i allow into During row register renaming, instruction i may also be not carried out completing, and the corresponding flight trade mark Fi that scores also has meaning, and Fi can not Used with discharging and being reassigned to instruction n+i.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of flight for supporting simultaneous multi-threading to instruct out of order transmitting note Distributional processing method, it can be distributed, recovery and the flight that retracts are remembered under conditions of different threads share same set of physical register Brand, and the parallel instructions from multiple threads, out of order transmitting are controlled by flight scoreboard, improve the energy of microprocessor Loss-rate.
The technical solution adopted for the present invention to solve the technical problems is:It is out of order to provide a kind of support simultaneous multi-threading instruction The flight scoreboard processing method of transmitting, register mapping table, thread control list and total are set in register renaming platform Free list;The register mapping table is index with logic register number, and entry number is equal to logic register number;The thread It is round-robin queue's structure to control list, and entry number is equal to free physical registers number, using pointer management end to end, sets full scale Will;Total free list is round-robin queue's structure, and entry number is equal to free physical registers number, using pointer management end to end, Full scale will is set, comprised the following steps:
When initial, all flight trade mark of scoring is tied up one by one with all free physical registers number in any order It is fixed;
When instruction carries out register renaming, the destination register number to instruction distribute free physical registers number and The flight bound therewith is scored the trade mark;
When instruction is submitted, flight that the instruction currently the distributes trade mark of scoring is tied up with the physical register number releasing currently distributed It is fixed, bound again with the physical register number of the last distribution of the instruction;
When instructing rollback, the flight that the instruction currently distributes scores the trade mark together with the physical register number currently distributed It is recovered, and the flight for recovering the last distribution of its destination register is scored the trade mark and the last physical register number distributed.
Each list of entries of the register mapping table includes:Physical register number, for representing corresponding to the entry When logic register last time carries out register renaming, the free physical registers number that are distributed, each list of entries needs The physical register number of initial mapping is set;Flight scoreboard significance bit, the flight for representing this entry score the trade mark whether Effectively, the position is that " 0 " represents invalid, represents effective for " 1 ", when initial, the position is " 0 ";Fly the trade mark of scoring, for representing this The flight of the physical register number binding of entry is scored the trade mark, and when initial, this is meaningless.
When the thread controls list initial, head pointer and tail pointer all point to entry 0, are completely masked as " 0 ", all entries Invalid, each list of entries includes:Flight logic register number, for representing the target logic register number of flight directive;Fly Row physical register number, when the flight logic register for representing this program recording currently carries out register renaming, divide The free physical registers number matched somebody with somebody;Fly the trade mark of scoring, for representing that the flight logic register of this program recording is currently carried out During register renaming, free time for being distributed scores the trade mark;History scoreboard significance bit, for representing the history of this program recording Whether the trade mark of scoring is effective, and the position is that " 0 " represents invalid, represents effective for " 1 ";History is scored the trade mark, for representing this entry The flight logic register of record is last when carrying out register renaming, and the flight distributed is scored the trade mark;History physics is posted Storage number, when the flight logic register last time for representing this program recording carries out renaming, the physics distributed is deposited Device number.
When total free list is initial, head pointer and tail pointer all point to entry 0, are completely masked as " 1 ", and all entries are all Effectively, each list of entries includes:Free physical registers number, posted for representing to be currently at idle condition and can distribute to target The physical register number that storage uses, when initial, each entry deposits all free physical registers number successively;Idle scoreboard Number, for representing to score the trade mark with the free time that the free physical registers number of this entry are bound, when initial, each entry is deposited successively All free time score the trade mark.
Instruction carries out register renaming and comprised the following steps:
(1) obtain free physical registers number from total free list and the free time trade mark of scoring distribute to destination register, And scored the control list tail of the queue of the corresponding thread of trade mark write-in respectively as flight physics register number and flight;
(2) the control list tail of the queue of corresponding thread is write using destination register as flight logic register number;
(3) register mapping table of thread is corresponded to using destination register as search index, it is last to obtain destination register Physical register number, flight scoreboard significance bit and the flight of mapping are scored the trade mark, respectively as history physical register number, are gone through The distributional significance bit of the Records of the Historian and history are scored the control list tail of the queue of the corresponding thread of trade mark write-in;
(4) scored the register mapping table of the corresponding thread of trade mark inquiry with the free time, carry out content and be connected matching, find flight The trade mark of scoring is equal to the entry of the idle trade mark of scoring, and it is " 0 " to put the flight scoreboard significance bit in entry;
(5) register mapping table of thread is corresponded to using destination register as search index, by free physical registers number and The free time trade mark of scoring is scored entry corresponding to trade mark write-in respectively as physical register number and flight, and it is effective to put flight scoreboard Position is " 1 ";
(6) by free physical registers number, free time score the trade mark and control list tail pointer with instruction together with send transmitting Platform;
(7) the head pointer circulation of total free list plus " 1 ", the control list rear pointer of corresponding thread circulates plus " 1 ".
Instruction comprises the following steps when submitting:History physical register number is read from the thread control list of corresponding thread Scored the trade mark with flight, and total free list tail of the queue is written to as free physical registers number and the free time trade mark of scoring, it is total empty Not busy list tail pointer circulation plus " 1 ".
Instruction comprises the following steps when retracting:
(1) from the control list rollback head pointer meaning entry of corresponding thread, flight logic register number, flight are read The score trade mark, history physical register number, history scoreboard significance bit and history of physical register number, flight is scored the trade mark, right Answer the rollback head pointer of the control list of thread to circulate to subtract " 1 ", current tail pointer circulation subtracts " 1 ";
(2) it is the register mapping table that search index corresponds to thread with flight logic register number, history physics is deposited Device number, history scoreboard significance bit and history score the trade mark respectively as physical register number, flight scoreboard significance bit and fly The register mapping table of the capable corresponding thread of trade mark write-in of scoring;
(3) flight physics register number and the flight trade mark of scoring were scored as free physical registers number and free time The trade mark writes total free list tail of the queue, and total free list rear pointer circulation adds " 1 ".
Beneficial effect
As a result of above-mentioned technical scheme, the present invention compared with prior art, has the following advantages that and actively imitated Fruit:
The present invention can realize:If the instruction in same thread has register read-after-write correlation, latter bar is controlled Instruction is launched after previous bar instructs and changes its destination register, it is ensured that reads the value after renewal;If the finger in same thread Order related be not present register read-after-write, or the instruction between different threads, then can arbitrarily out of order transmitting, to obtain the hair of maximum Penetrate efficiency.Flight in the present invention scores the trade mark always with idle physical register number binding, carries out deposit in instruction and thinks highly of During name, the flight trade mark of scoring is assigned to the destination register of instruction together with the free physical registers number of binding;Referring to When order is submitted, the flight that currently the distributes trade mark of scoring is unbinding with the physical register number that currently distributes, the flight scoreboard Number with instructing the free physical registers number that newly discharge to bind again;Instruct retract when, the flight that currently distributes is scored the trade mark It is recovered with together with the physical register number currently distributed, and the flight for recovering the last distribution of its destination register is scored the trade mark With the physical register number of last time distribution.The present invention utilizes less hardware resource, solves in multiple threads while performs And in the case of sharing same set of physical register, the out of order transmitting problem of instruction, improve the observable index of microprocessor.
Brief description of the drawings
Fig. 1 is position view of all kinds of lists on instruction pipeline described in the present invention;
Fig. 2 is original state schematic diagram of all kinds of lists under embodiment in the present invention;
Fig. 3 is view of all kinds of lists under embodiment after register renaming in the present invention;
Fig. 4 is view of all kinds of lists under embodiment after instruction is submitted in the present invention;
Fig. 5 is view of all kinds of lists under embodiment after instruction exception in the present invention.
Embodiment
With reference to specific embodiment, the present invention is expanded on further.It should be understood that these embodiments are merely to illustrate the present invention Rather than limitation the scope of the present invention.In addition, it is to be understood that after the content of the invention lectured has been read, people in the art Member can make various changes or modifications to the present invention, and these equivalent form of values equally fall within the application appended claims and limited Scope.
The flight scoreboard quantity that the present invention is set is still equal to free physical registers quantity, it is assumed that quantity n.Initially When, first the flight trade mark of scoring is bound one by one with all free physical registers number in any order.During register renaming, give The destination register (Rd) of one instruction distributes a free physical registers number (Pdc), while distributes one and the idle thing The flight of reason register number (Pdc) binding is scored the trade mark (Fdci).When instruction is submitted, the last distribution of destination register (Rd) Physical register (Pdh) is converted to the physical register of free time, and it is visible that the physical register currently distributed (Pdc) is converted to software Logic register, the flight currently distributed the trade mark (Fdci) of scoring is unbinding with the physical register (Pdc) that currently distributes, Bound again with the free physical registers (Pdh) newly discharged.Instruct retract when, the flight that currently distributes is scored the trade mark (Fdci) reclaimed with the physical register number (Pdc) currently distributed by together with, recover the last distribution of its destination register (Rd) Flight score the trade mark (Fdhi) and the physical register number (Pdh) of last distribution.
Patent《The flight flying scoreboard device of out of order transmitting is controlled in a kind of superscalar microprocessor》In flight scoreboard Number essence is position of the free physical registers in free list, always by the order of " 0,1,2 ... (n-1), 0 ... " Cycle assignment.And the flight in the present invention is scored, trade mark essence is to establish binding relationship with free physical registers itself, with sky Position of the not busy physical register in free list is unrelated, and the flight really distributed scores the trade mark with carrying out register renaming Instruction stream is closely related.Therefore, the present invention need to set corresponding hardware configuration, and the record-setting flight trade mark of scoring is deposited with free physical Binding relationship between device.
Complete register renaming and the technical scheme of flight scoreboard control are described below, as shown in figure 1, existing first Following several lists that register renaming platform is set:
(1) register mapping table of certain thread:Each thread is independently arranged a table, and the table is to be with logic register number The bivariate table of index, entry number are equal to logic register number, and each list of entries includes:
A) physical register number:When representing that logic register last time carries out register renaming corresponding to the entry, The free physical registers number distributed, each list of entries need to set the physical register number of initial mapping;
B) flight scoreboard significance bit:Represent whether the flight trade mark of scoring of this entry effective, the position be " 0 " indicate without Effect, represent effective for " 1 ".When initial, the position is " 0 ";
C) fly the trade mark of scoring:Represent to score the trade mark with the flight that the physical register number of this entry is bound., should when initial Domain is meaningless.
(2) the control list of certain thread:Each thread is independently arranged a table, the phase for minute book thread flight directive Close information.The table is round-robin queue's structure, and entry number is equal to free physical registers number, using pointer management end to end, is set full Mark.When initial, head pointer and tail pointer all point to entry 0, are completely masked as " 0 ", all entry invalidations.Each list of entries bag Include:
A) flight logic register number:Represent the destination register number of flight directive;
B) flight physics register number:Represent that the flight logic register of this program recording currently carries out register renaming When, the free physical registers number that are distributed;
C) fly the trade mark of scoring:When representing that the flight logic register of this program recording currently carries out register renaming, The flight distributed is scored the trade mark;
D) history scoreboard significance bit:Represent whether the history trade mark of scoring of this program recording is effective, the position is that " 0 " represents It is invalid, represent effective for " 1 ";
E) history is scored the trade mark:Represent that the flight logic register of this program recording is last and carry out register renaming When, the flight that is distributed is scored the trade mark;
F) history physical register number;When representing that the flight logic register last time of this program recording carries out renaming, The free physical registers number that will be discharged after the physical register number distributed, that is, instruction submission.
(3) total free list:All threads share a table, for recording free physical registers information.The table is to follow Ring queue structure, entry number are equal to free physical registers number, using pointer management end to end, set full scale will.When initial, head refers to Pin and tail pointer all point to entry 0, are completely masked as " 1 ", and all entries are all effective.Each list of entries includes:
A) free physical registers number:Expression is currently at idle condition, can distribute to the physics that destination register uses Register number.When initial, each entry deposits all free physical registers number successively;
B) free time scores the trade mark;Represent to score the trade mark with the free time that the free physical registers number of this entry are bound.Initially When, each entry is deposited all free time and scored the trade mark successively.
The flight scoreboard mask bit of n positions is set in instruction issue platform, the position is that " 0 " represents to allow to launch, otherwise table Showing does not allow to launch.
When instruction enters register renaming platform, if the source register (Rs) of instruction is effectively, with logic register Number (Rs) is the register mapping table that index accesses correspond to thread, acquisition physical register number (Ps), flight scoreboard significance bit (Fsiv) scored the trade mark (Fsi) with flight, transmitting platform is entered together with instruction.
If the destination register (Rd) of instruction is effectively, following operation is performed:
(1) obtain free physical registers number (Pdc) from total free list and the free time scores the trade mark (Fdci), distribute to Rd, and scored the control list tail of the queue of the corresponding thread of trade mark write-in respectively as flight physics register number and flight;
(2) the control list tail of the queue of corresponding thread is write using Rd as flight logic register number;
(3) register mapping table of thread is corresponded to using Rd as search index, obtains the distribution of Rd last time registers renaming Physical register number, flight scoreboard significance bit and flight score the trade mark, respectively as history physical register number (Pdh), History scoreboard significance bit (Fdhiv) and history are scored the control list tail of the queue of the corresponding thread of the trade mark (Fdhi) write-in;
(4) register mapping table of corresponding thread is inquired about with Fdci, content is carried out and is connected matching (CAM), find flight and remember Brand is equal to Fdci entry, and it is " 0 " to put the flight scoreboard significance bit in entry;
(5) register mapping table of thread is corresponded to using Rd as search index, using Pdc and Fdci as physical register Number and flight score the trade mark write-in corresponding to entry, juxtaposition flight scoreboard significance bit is " 1 ";
(6) Pdc, Fdci and control list tail pointer are sent to transmitting platform together with instruction;
(7) the head pointer circulation of total free list plus " 1 ", the control list rear pointer of corresponding thread circulates plus " 1 ".
As can be seen here, a source register is effectively instructed after register renaming, will carry source physical register Number (Ps), source flight scoreboard significance bit (Fsiv) and source flight are scored the trade mark (Fsi).If instruction has multiple source registers, Then there are more set above- mentioned informations.One destination register is effectively instructed after register renaming, will be carried target physical and is posted Storage number (Pdc) and target flight are scored the trade mark (Fdci).In addition, instruction also carries this instruction after register renaming Carry out the preoperative control list tail pointer of register renaming.
When instruction enters transmitting platform, if the destination register of instruction is effective, flight scoreboard mask bit is set Fdci positions are " 1 ".
Instruction is when transmitting queue is medium to be launched, if the source flight scoreboard significance bit (Fsiv) carried is " 1 ", The Fsi positions of check flight scoreboard mask bit:If the position is " 0 ", then it represents that the value in source physical register (Pdc) can Read, otherwise represent unreadable, instruction also needs to continue waiting in queue is launched;If the source flight scoreboard significance bit carried (Fsiv) it is " 0 ", does not then need check flight scoreboard mask bit, the value in source physical register (Pdc) is readable.
Instruction issue, when that implementing result will be write target physical register (Pdc), puts flight to after execution unit (Fdci) position of scoreboard mask bit is " 0 ", represents that the value in the physical register (Pdc) is readable.
When instruction is submitted, if destination register is effective, reading history physics is posted from the control list of corresponding thread Storage number (Pdh) and flight are scored the trade mark (Fdci), total idle as the trade mark write-in of scoring of free physical registers number and free time List tail of the queue, total free list tail pointer circulation add " 1 ".If there are multiple threads to submit instruction simultaneously, need parallel reading more The control list of individual thread, and the multiple Pdh and Fdc of reading are write in total free list, the sequencing of write-in will not Ask.
Occur when branch prediction fails, it is necessary to which the instruction after the transfer instruction that retracts is repaiied to above-mentioned various list states Change., it is necessary to retract exceptional instructions itself and modification of the instruction to above-mentioned various list states afterwards when occurring abnormal.When this refers to Order occur branch prediction failure or it is abnormal when, the control list current tail pointer circulation of corresponding thread is subtracted into " 1 " afterwards as rollback Head pointer, the control list tail pointer that branch prediction failure or exceptional instructions are carried as rollback tail pointer, from the beginning to the end according to It is secondary to proceed as follows:
(1) from the control list rollback head pointer meaning entry of corresponding thread, reading flight logic register number (Rd), Flight physics register number (Pdc), the score trade mark (Fdci), history physical register number (Pdh), history scoreboard of flight are effective Position (Fdhiv) and history are scored the trade mark (Fdhi), and the rollback head pointer of the control list of corresponding thread, which circulates, to be subtracted " 1 ", current tail Pointer circulation subtracts " 1 ";
(2) register mapping table of thread is corresponded to using Rd as search index, using Pdh, Fdhiv and Fdhi as physics Register number, flight scoreboard significance bit and flight are scored the register mapping table of the corresponding thread of trade mark write-in;
(3) total free list team is write using Pdc and Fdci as free physical registers number and the free time trade mark of scoring Tail, total free list rear pointer circulation add " 1 ";
(4) the Fdci positions for putting flight scoreboard mask bit in transmitting platform are " 0 ".
Occur simultaneously when branch prediction fails or be abnormal, it is necessary to read the control of multiple threads parallel when there are multiple threads List, and write operation is carried out to total free list simultaneously, the sequencing of write-in does not require.
The present invention is further illustrated by taking integer instructions as an example below.
It is assumed that microprocessor supports two Simultaneous multithreading technologies, each thread can use 42 integer logics to deposit Device, be designated as R0, R1 ..., R41, wherein R0 to R40 can be used as source register and destination register, R41 values are complete " 0 ", only Source register can be used as.The physical register that two threads are used in conjunction be 146, be designated as P0, P1 ..., P145.Initially When, by P0, P1 ..., P40 distribute to thread 0 logic register R0, R1 ..., R40, by P41, P42 ..., P81 point Logic register R0, R1 of dispensing thread 1 ..., R40.Remaining 64 free physical registers, respectively P82, P83、……、P145。
Under these conditions, the renaming mapping table entry of each thread is 42, the control list of entries of each thread For 64, total free list entries are 64, and flight scoreboard mask bit is 64, and the flight trade mark of scoring is represented with 6.Such as Fruit need to set 146 with traditional scoreboard technology, scoreboard mask bit, and the trade mark of scoring needs to be represented with 8.Shorter flies Row scores memorial tablet and flight the is scored trade mark, in specific physics realization, it is meant that shorter access delay and less hardware money Source expense.
The original state of all kinds of lists is as shown in Figure 2.
In the register mapping table of thread 0, physical register number be respectively P0, P1 ..., P41, flight scoreboard is effective Position be " 0 ", and the trade mark of scoring of flying is meaningless.In the register mapping table of thread 1, physical register number respectively P42, P43 ..., P81, flight scoreboard significance bit is " 0 ", and the flight trade mark of scoring is meaningless.
For sky, head pointer and tail pointer all point to entry 0, are completely masked as " 0 " for the list that controls of thread 0.The control of thread 1 List is identical with thread 0.
In total free list, head pointer and tail pointer all point to entry 0, are completely masked as " 1 ".Free physical in entry is posted Storage number is respectively:P82, P83 ..., P145, the free time trade mark of scoring is respectively:F0、F1、……、F63.
It is assumed that an instruction group of thread 0 first reaches register renaming platform, instruction group content is as follows:
Inst0:R8+R9-》R1, represent to read source register R8 and R9, as a result write R1;
Inst1:R1+R9-》R0, represent to read source register R1 and R9, as a result write R0;
Inst2:R0+R8-》R1, represent to read source register R0 and R8, as a result write R1;
Inst3:R0-》Mem, represent to read source register R0, as a result write-in hosts, and the instruction target register is invalid;
Instruct Inst0 as follows in the operating procedure of register renaming platform:
(1) with the renaming mapping table that source register (R8) is search index thread 0, read what the instruction really to be accessed Physical register number (P8), by the flight scoreboard significance bit in institute's accesses entry is " 0 ", when showing the instruction issue, P8 In value it is readable;With the renaming mapping table of source register (R9) index thread 0, read the instruction physics really to be accessed and post Storage number (P9), by the flight scoreboard significance bit in institute's accesses entry is " 0 ", when showing the instruction issue, the value in P9 It is readable;
(2) obtain free physical registers number (P82) from total free list and the free time scores the trade mark (F0), distribute to mesh Scalar register file (R1);The control row for trade mark write line journey 0 of being scored using P82 and F0 as flight physics register number and flight Table tail of the queue (entry 0);
(3) the control list tail of the queue (entry 0) of corresponding thread is write using R1 as flight logic register number;
(4) the renaming mapping table using R1 as search index thread 0, the physical register of the last distribution of R1 is read (P1) the control list tail of the queue (entry 0) of thread 0, is write using P1 as history physical register number, due to flight corresponding to P1 Scoreboard significance bit is " 0 ", therefore the history scoreboard significance bit controlled in list tail of the queue (entry 0) for putting thread 0 is " 0 ";
(5) register mapping table of thread 0 is inquired about with F0, content is carried out and is connected matching (CAM), do not find flight and score The trade mark is equal to F0 entry;
(6) register mapping table using R1 as search index thread 0, using P82 and F0 as physical register number and Flight score the trade mark write-in corresponding to entry, juxtaposition flight scoreboard significance bit is " 1 ";
(7) tail pointer of R8, R9, P82, F0 and thread 0 (" 0 ") send transmitting platform together with instruction;
(8) the head pointer circulation of total free list plus " 1 ", the control list rear pointer of corresponding thread circulates plus " 1 ".
Inst0 is instructed to develop into P8+P9- after register renaming platform》P82, represent read source register P8 and P9, destination register P82 is as a result write, after the instruction enters transmitting platform, the F0 positions for setting flight scoreboard mask bit are " 1 ", the value in the source register P8 and P9 of the instruction are all ready for, it is not necessary to flight scoreboard mask bit are inquired about, at other Condition can be transmitted directly to execution unit in the case of all meeting.
Subsequent instructions near order Inst0 carries out aforesaid operations successively.
Inst1 is instructed to develop into P82+P9- after register renaming platform》P83, represent to read source register P82 And P9, destination register P83 is as a result write, after the instruction enters transmitting platform, the F1 positions of flight scoreboard mask bit are set For " 1 ", the value in the source register P9 of the instruction is all ready for, but source register P82 needs to inquire about the shielding of flight scoreboard When the instruction Inst0 such as the F0 positions of position, need will write P82, it could allow to instruct Inst1 to be transmitted into execution unit.
Inst2 is instructed to develop into P83+P8- after register renaming platform》P84, represent to read source register P83 And P8, destination register P84 is as a result write, after the instruction enters transmitting platform, the F2 positions of flight scoreboard mask bit are set For " 1 ", the value in the source register P8 of the instruction is all ready for, but source register P83 needs to inquire about the shielding of flight scoreboard When the instruction Inst1 such as the F1 positions of position, need will write P83, it could allow to instruct Inst2 to be transmitted into execution unit.
Inst3 is instructed to develop into P83- after register renaming platform》Mem, represent to read source register P83, knot During fruit write-in hosts.Because the destination register of the instruction is invalid, therefore free physical registers are not distributed, the instruction enters hair After penetrating platform, flight scoreboard mask bit is not provided with.The source register P83 of the instruction needs to inquire about flight scoreboard mask bit When the instruction Inst1 such as F1 positions, need will write P83, it could allow to instruct Inst3 to be transmitted into execution unit.
It is assumed that being subsequently the instruction group arrival register renaming platform of thread 1, instruction group content is as follows:
Inst4:R8+R9-》R1;
Inst5:R1+R9-》R0;
Inst6:R0+R8-》R1;
Inst7:R0+R1-》R2:
Above-mentioned instruction near order Inst0 carries out aforesaid operations successively, accesses and change the register mappings of thread 1 respectively The control list of table and thread 1.
Inst4 is instructed to develop into P49+P50- after register renaming platform》P85, represent to read source register P49 And P50, destination register P85 is as a result write, after the instruction enters transmitting platform, the F3 positions of flight scoreboard mask bit are set For " 1 ", the value in institute the active registers P49 and P50 of the instruction is all ready for, it is not necessary to inquires about the shielding of flight scoreboard Position, execution unit can be transmitted directly in the case where other conditions all meet.
Inst5 is instructed to develop into P85+P50- after register renaming platform》P86, represent to read source register P85 And P50, destination register P86 is as a result write, after the instruction enters transmitting platform, the F4 positions of flight scoreboard mask bit are set For " 1 ", the value in the source register P50 of the instruction is all ready for, but source register P85 needs to inquire about the shielding of flight scoreboard When the instruction Inst4 such as the F3 positions of position, need will write P85, it could allow to instruct Inst5 to be transmitted into execution unit.
Inst6 is instructed to develop into P86+P49- after register renaming platform》P87, represent to read source register P86 And P49, destination register P87 is as a result write, after the instruction enters transmitting platform, the F5 positions of flight scoreboard mask bit are set For " 1 ", the value in the source register P49 of the instruction is all ready for, but source register P86 needs to inquire about the shielding of flight scoreboard When the instruction Inst5 such as the F4 positions of position, need will write P86, it could allow to instruct Inst6 to be transmitted into execution unit.
Inst7 is instructed to develop into P86+P87- after register renaming platform》P88, represent to read source register P86 With source register P87, destination register P88 is as a result write, after the instruction enters transmitting platform, flight scoreboard mask bit is set F6 positions be " 1 ", the source register P86 and P87 of the instruction are required for inquiring about the F4 and F5 of flight scoreboard mask bit When position, the instruction Inst4 such as needing will write or write P86, and instructing the Inst5 will to write or write P87, it could allow to instruct Inst6 is transmitted into execution unit.
When instruction 7 is after register renaming platform, each table status is as shown in Figure 3.
It is assumed that instruction Inst4~Inst6 of thread 1 is first submitted, then related operation is as follows successively:
(1)Inst4:P49+P50-》P85 is submitted;From the control list of thread 1 in head pointer (entry 0), reading is gone through History physical register P42 and flight are scored trade mark F3, total free list tail of the queue (entry 0) are write, in the control list of thread 1 Head pointer circulation plus " 1 ", total free list rear pointer circulation add " 1 ";
(2)Inst5:P85+P50-》P86 is submitted;From the control list of thread 1 in head pointer (entry 1), reading is gone through History physical register P41 and flight are scored trade mark F4, total free list tail of the queue (entry 1) are write, in the control list of thread 1 Head pointer circulation plus " 1 ", total free list rear pointer circulation add " 1 ";
(3)Inst6:P86+P49-》P87 is submitted;From the control list of thread 1 in head pointer (entry 2), reading is gone through History physical register P85 and flight are scored trade mark F5, are written to total free list tail of the queue (entry 2), the control list of thread 1 Middle head pointer circulation plus " 1 ", total free list rear pointer circulation add " 1 ";
After instruction Inst4~Inst6 of thread 1 is submitted, the state of each table is as shown in Figure 4.
It is assumed that exception occurs for the instruction Inst1 of thread 0, now instruct Inst0 not submit also, need to continue executing with, instruct Inst1~Inst3 is required for retracting.The rollback head pointer of thread 0 points to entry 2, and rollback tail pointer points to entry 1.
Instruction Inst3 destination register is invalid, and each table does not need any rollback operation;
Back-off instruction Inst2 operation is as follows:
(1) from the control list rollback head pointer meaning entry (entry 2) of thread 0, flight logic register number is read R1, flight physics register number P84, trade mark F2, history physical register P82, the history scoreboard significance bit " 1 " of scoring of flying Scored trade mark F0 with history, the rollback head pointer circulation of the control list of thread 0 subtracts " 1 ", and current tail pointer circulation subtracts " 1 ";
(2) register mapping table using R1 as search index thread 0, P1 is write into physical register domain, F0 is write Flight is scored trade mark domain, and it is " 1 " to put flight scoreboard significance bit;
(3) P84 and F2 is write into total free list tail of the queue (entry 3), total free list rear pointer circulation adds " 1 ";
(4) the F2 positions for putting flight scoreboard mask bit in transmitting platform are " 0 ".
Back-off instruction Inst1 operation is as follows:
(5) from the control list rollback head pointer meaning entry (entry 1) of thread 0, flight logic register number is read R0, flight physics register number P83, trade mark F1, history physical register P0, the history scoreboard significance bit " 0 " of scoring of flying, The rollback head pointer circulation of the control list of thread 0 subtracts " 1 ", and current tail pointer circulation subtracts " 1 ";
(6) register mapping table using R0 as search index thread 0, P0 is write into physical register domain, puts flight note Distributional significance bit is " 0 ";
(7) P83 and F1 is write into total free list tail of the queue (entry 4), total free list rear pointer circulation adds " 1 ";
(8) the F1 positions for putting flight scoreboard mask bit in transmitting platform are " 0 ".
The state that instruction Inst1 rollbacks terminate rear each table is as shown in Figure 5.

Claims (6)

1. a kind of flight scoreboard processing method for supporting simultaneous multi-threading to instruct out of order transmitting, it is characterised in that in register Renaming platform sets register mapping table, thread control list and total free list;The register mapping table is posted with logic Storage number is index, and entry number is equal to logic register number;It is round-robin queue's structure that the thread, which controls list, and entry number is equal to Free physical registers number, using pointer management end to end, full scale will is set;Total free list is round-robin queue's structure, bar Mesh number is equal to free physical registers number, using pointer management end to end, sets full scale will, comprises the following steps:
When initial, all flight trade mark of scoring is bound one by one with all free physical registers number in any order;
When instruction carries out register renaming, the destination register number to instruction distributes free physical registers number and therewith The flight of binding is scored the trade mark;It is specific as follows:
Obtain free physical registers number from total free list and the free time trade mark of scoring distributes to destination register, and make respectively Scored the control list tail of the queue of the corresponding thread of trade mark write-in for flight physics register number and flight;
The control list tail of the queue of corresponding thread is write using destination register as flight logic register number;
The register mapping table of thread is corresponded to using destination register as search index, obtains the thing of the last mapping of destination register Reason register number, flight scoreboard significance bit and flight are scored the trade mark, respectively as history physical register number, history scoreboard Significance bit and history are scored the control list tail of the queue of the corresponding thread of trade mark write-in;
Scored the register mapping table of the corresponding thread of trade mark inquiry with the free time, carry out content and be connected matching, find flight scoreboard Number being equal to the free time scores the entry of the trade mark, and it is " 0 " to put the flight scoreboard significance bit in entry;
The register mapping table of thread is corresponded to using destination register as search index, free physical registers number and free time are scored The trade mark is scored entry corresponding to trade mark write-in respectively as physical register number and flight, and it is " 1 " to put flight scoreboard significance bit;
By free physical registers number, free time score the trade mark and control list tail pointer with instruction together with send transmitting platform;
The head pointer circulation of total free list plus " 1 ", the control list rear pointer of corresponding thread circulates plus " 1 ";
When instruction is submitted, flight that the instruction currently the distributes trade mark of scoring is unbinding with the physical register number that currently distributes, Bound again with the physical register number of the last distribution of the instruction;
Instruct retract when, flight that the instruction currently the distributes trade mark of scoring is returned together with the physical register number currently distributed Receive, and the flight for recovering the last distribution of its destination register is scored the trade mark and the last physical register number distributed.
2. the flight scoreboard processing method according to claim 1 for supporting simultaneous multi-threading to instruct out of order transmitting, it is special Sign is that each list of entries of the register mapping table includes:Physical register number, for representing to patrol corresponding to the entry When volume register last time carries out register renaming, the free physical registers number that are distributed, each list of entries need to be set Put the physical register number of initial mapping;Whether flight scoreboard significance bit, the trade mark of scoring of the flight for representing this entry have Effect, the position are that " 0 " represents invalid, represent effective for " 1 ", when initial, the position is " 0 ";Fly the trade mark of scoring, for representing this The flight of purpose physics register number binding is scored the trade mark, and when initial, this is meaningless.
3. the flight scoreboard processing method according to claim 1 for supporting simultaneous multi-threading to instruct out of order transmitting, it is special Sign is that when the thread controls list initial, head pointer and tail pointer all point to entry 0, are completely masked as " 0 ", all entries Invalid, each list of entries includes:Flight logic register number, for representing the target logic register number of flight directive;Fly Row physical register number, when the flight logic register for representing this program recording currently carries out register renaming, divide The free physical registers number matched somebody with somebody;Fly the trade mark of scoring, for representing that the flight logic register of this program recording is currently carried out During register renaming, free time for being distributed scores the trade mark;History scoreboard significance bit, for representing the history of this program recording Whether the trade mark of scoring is effective, and the position is that " 0 " represents invalid, represents effective for " 1 ";History is scored the trade mark, for representing this entry The flight logic register of record is last when carrying out register renaming, and the flight distributed is scored the trade mark;History physics is posted Storage number, when the flight logic register last time for representing this program recording carries out renaming, the physics distributed is deposited Device number.
4. the flight scoreboard processing method according to claim 1 for supporting simultaneous multi-threading to instruct out of order transmitting, it is special Sign is, when the total free list is initial, head pointer and tail pointer all point to entry 0, are completely masked as " 1 ", and all entries are all Effectively, each list of entries includes:Free physical registers number, posted for representing to be currently at idle condition and can distribute to target The physical register number that storage uses, when initial, each entry deposits all free physical registers number successively;Idle scoreboard Number, for representing to score the trade mark with the free time that the free physical registers number of this entry are bound, when initial, each entry is deposited successively All free time score the trade mark.
5. the flight scoreboard processing method according to claim 1 for supporting simultaneous multi-threading to instruct out of order transmitting, it is special Sign is that instruction comprises the following steps when submitting:History physical register number is read from the thread control list of corresponding thread Scored the trade mark with flight, and total free list tail of the queue is written to as free physical registers number and the free time trade mark of scoring, it is total empty Not busy list tail pointer circulation plus " 1 ".
6. the flight scoreboard processing method according to claim 1 for supporting simultaneous multi-threading to instruct out of order transmitting, it is special Sign is that instruction comprises the following steps when retracting:
(1) from the control list rollback head pointer meaning entry of corresponding thread, flight logic register number, flight physics are read The score trade mark, history physical register number, history scoreboard significance bit and history of register number, flight is scored the trade mark, corresponding line The rollback head pointer circulation of the control list of journey subtracts " 1 ", and current tail pointer circulation subtracts " 1 ";
(2) be that search index corresponds to the register mapping table of thread with flight logic register number, by history physical register number, History scoreboard significance bit and the history trade mark of scoring are scored respectively as physical register number, flight scoreboard significance bit and flight The register mapping table of the corresponding thread of trade mark write-in;
(3) flight physics register number and the flight trade mark of scoring were scored the trade mark as free physical registers number and free time Total free list tail of the queue is write, total free list rear pointer circulation adds " 1 ".
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