CN103207776A - Out-of-order gene issuing processor core - Google Patents
Out-of-order gene issuing processor core Download PDFInfo
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- CN103207776A CN103207776A CN2013100765808A CN201310076580A CN103207776A CN 103207776 A CN103207776 A CN 103207776A CN 2013100765808 A CN2013100765808 A CN 2013100765808A CN 201310076580 A CN201310076580 A CN 201310076580A CN 103207776 A CN103207776 A CN 103207776A
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Abstract
The invention discloses an out-of order gene issuing processor core. The out-of-order gene issuing processor core comprises a decode control module and a write-back control module which correspond to the decoding stage and the write-back stage of a processor pipeline. The decode control module comprises an instruction stream control module, an instruction issuing control module, a data bypass control module, a register access module, a write-back permission module and an instruction issuing module. The write-back control module comprises a write-back result registration module and a write-back output module. According to the out-of-order gene issuing processor core and by means of the integratedly-controlled decode control module and write-back control module, high-efficiency out-of-order issuing of processor instructions can be achieved, the instruction-stage parallelism of the processor can be exploited to the largest extent, a large amount of physical registers in a register renaming technology can be avoided, and a large amount of consumption of hardware resources in a reservation station technology can be saved.
Description
Technical field
The present invention relates to a kind of processor cores, the out of order emission processor cores of especially a kind of gene.
Background technology
The scoreboard mechanism that adopts among the CDC6600 is satisfying the out of order execution of permission instruction under the relevant situation of data.Every instruction in the processor all will be passed through scoreboard, and checks data dependence here, and scoreboard determines that by the implementation status that detects wherein every instruction certain bar instruction when can read operation number and execution.The instruction that conflict has been removed in the scoreboard can out of orderly be launched, and enters execution level.Simultaneously, scoreboard also steering order writes back the operation of destination register, and all collision detection and the releasing work of instruction all depend on scoreboard in the middle of the processor.Every instruction process four-stage:
Emission: if instruct employed functional part idle, and do not rob with other instruction of activity and use same destination register, scoreboard is launched this instruction, and is somebody's turn to do the state of instruction in the scoreboard, to be used for the collision detection of other instruction to be launched.Use same destination register by guaranteeing that firing order is not robbed with movable instruction, solved and write write conflict.Therefore, at launching phase, the write conflict of writing on structural hazard and the data is solved.
Read operation number: the available situation of scoreboard surveillance source operand, if the register that the active instruction of not launched will be write this operand or deposit this operand is write by certain functional part this moment, then operand can be used, and can carry out the work of read operation number.By this method, solved and write read conflict.
Carry out: refer to that operand enters functional part and carries out.
Write back: in case instruct completely, just detect whether read/write conflict is arranged, if do not have read/write conflict then instruction write-back.
Scoreboard is playing the correlativity that detects between instruction in the middle of the processor, adopted the mode of waiting for when finding correlativity, and this has limited the degree of parallelism between instruction to a great extent.In fact, the read-write between the processor instruction is correlated with and is write relevant because the register another name causes, and is not the restriction of data stream, adopt the architecture of optimizing, can eliminate these and be correlated with, make the degree of parallelism of call instruction only be subjected to the relevant restriction of write-read, reach the data stream limit.Register renaming, reservation station and reset technology such as order buffer memory and solved this problem, but a large amount of physical register of register renaming Technology Need; For the reservation station technology, distributed reservation station need be set up the reservation station formation for each functional unit, and the quantity of reservation station then can cause pause because reservation station is not enough very little, and is too many then can cause waste on a large amount of hardware; Resetting the order caching technology then holds instruction except a large amount of register of needs and also needs quite complicated controlling mechanism the state.These technology design high performance processor and have great role for developing degree of parallelism to greatest extent, but seem too complicated for the design of the single core in the middle of the multinuclear design, and its hardware spending also is difficult to bear.Therefore, the compromise of a kind of performance and expense can be arranged preferably, exceed at hardware complexity under the situation of increase and develop degree of parallelism to greatest extent.
Summary of the invention
The purpose of this invention is to provide a kind of instruction and develop the instruction degree of parallelism to greatest extent, and hardware spending and the complexity out of order lift-off technology of a kind of processor within the acceptable range, its performance is better than scoreboard technology, and hardware spending and complicacy are then than register renaming, reservation station with to reset the order buffer memory little.
The present invention proposes a kind of new out of order emission mechanism, be applicable to the design of the single core in the polycaryon processor that adopts pipelining, the out of order emission of instruction in the processing, out of order writing back under the situation of conditions permit improved the degree of parallelism of instruction to greatest extent.
The structure that the present invention proposes comprises following two modules: encoded control module and write back control module, and corresponding to the decode stage in the middle of the processor pipeline with write back level.
Described encoded control module comprises: instruction stream control module, instruction emission control module, data bypass control module, register access module, write back and allow module, instruction sending module.
Described instruction stream control module is responsible for receiving the M instruction that will launch, and the implementation status of recording instruction information, detection instruction is used for other module.Allow the emission situation of signal and the instruction of current M bar to decide any bar instruction to launch according to emission, and this signal is sent, use for other module.Finish signal according to writing back writing back that control module sends here, deletion has write back the instruction of finishing, and reads in new instruction.Described M is the natural number greater than 1.
Described instruction issuing module is finished signal according to the command information in the middle of the instruction stream control module and data bypass, determines the conflict of central which the bar instruction of M bar instruction to solve, and produces the signal that emission allows, for other module use.
Described data bypass control module receives and writes back the bypass data that control module is sent back to, is redirected to the instruction that needs these data, produces the signal that this data bypass of indication is finished then, uses for other module.
Described register access module is carried out the visit of register according to the command information of instruction stream control module, and the result that will visit sends, and uses for other module.
Described writing back allows module according to the information in the middle of the instruction stream control module, whether the register that decides every instruction to upgrade has read is finished, when register read finish after, send and write back the permission signal, the data that show this instruction can be upgraded register, and this signal sent, use for other module.
The information that described instruction sending module according to which bar instruction can be launched is selected the instruction that will launch from the instruction of M bar, select the up-to-date operand of this instruction in the middle of the data of returning from register file memory access result and bypass, and the up-to-date operand of the instruction that will launch and instruction is sent.
The described control module that writes back comprises: write back the result and deposit module, write back output module.
The described result of writing back deposits module and is responsible for receiving the M bar instruction that will write back, and the result that will write back, the information such as destination register that will write back note, allow signal to decide any bar instruction to write back according to writing back of sending here of instruction stream control module, generation writes back finishes signal, uses for other module.
The described output module that writes back writes back to the current result that will write back in the middle of the register according to writing back the information that the result deposits in the middle of the module, finishes data and writes back.
The present invention uses the encoded control module of lump control and writes back control module, realized the efficient out of order emission of processor instruction, developed the instruction level parallelism degree of processor to greatest extent, avoided the huge physical register of number in the register renaming technology, saved the consumption of hardware resources a large amount of in the middle of the reservation station technology, simultaneously, proportion sequencing buffer memory is simple again on the complexity of control, be the realization of the out of order emission control structure of processor high-efficiency and economic, be suitable for very much the design of the central single core of polycaryon processor.
Description of drawings
Fig. 1 is system construction drawing of the present invention;
Fig. 2 is the structured flowchart of encoded control module;
Fig. 3 is the structural drawing of instruction flow control module;
Fig. 4 is the structural drawing of instruction sending module;
Fig. 5 is the structured flowchart that writes back control module;
Fig. 6 writes back the structural drawing that the result deposits module.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.
Fig. 1 has shown structural drawing of the present invention, comprises two modules in the structure: encoded control module and write back control module, and the encoded control module is equivalent to the decode stage in the middle of the streamline, and the conflict between the instruction here obtains detecting and dissolving; Write back control module and be responsible for writing back of instruction execution result, be equivalent to the level that writes back in the middle of the streamline.Between two modules, the encoded control module is given and is write back control module and write back the permission signal, the writing back of steering order execution result; Writing back control module then will write back and finish signal and give the encoded control module, the renewal of command information in the middle of the control encoded control module.
The structural drawing of encoded control module as shown in Figure 2, wherein the instruction stream control module receives and flows into instruction, it is a structure that is similar to shift register, record has also been stored the information that flows into instruction, and command information offered instruction emission control module, the data bypass module, the register access module, instruction sending module and write back the permission module, it will allow signal according to the emission that instruction emission control module is sent here, write back writing back that control module sends here and finish the renewal that signal is finished instruction entry, after an instruction emission is finished, current instruction entry is just deleted, in order to flow into new instruction.
The data bypass module receives the bypass data that transmits, and finish signal and bypass data useful signal according to producing data bypass from the command information of instruction stream control module, data bypass is finished signal and is delivered to instruction emission control module, as instructing one of condition of emission, the bypass data useful signal is then delivered to instruction sending module, is used for determining that using bypass data still is that register is read data as real operand.
Instruction emission control module produces the instruction emission and allows signal according to from the command information of instruction control module, from the conflict between the data bypass information decision instruction of data bypass module.
The register access module is carried out register access according to command information, reads the value in the middle of the corresponding registers, as one of chosen candidate value of operand.
Instruction sending module produces information and the operand of the instruction of final emission according to from the information of wanting firing order of instruction stream control register, from register access result and the outside bypass data of register access module through judgement.
The structure of instruction stream control module is (be example with M=4) as shown in Figure 3, the instruction numbering cycle is for distinguishing the unique number of every instruction, and its value is 0,1,2,3, whenever there being an instruction write-back to finish, corresponding order number just reclaims, and assignment is given the new instruction that flows into.For example suppose that the four instructions numbering from front to back in the middle of the present instruction flow control module is respectively 0,1,2,3, and being numbered 2 instruction write-back finishes, then numbered for 2 free time, when new instruction flows into, its numbering just is assigned 2, and then the four instructions in the middle of the instruction stream control module is respectively 0,1,3,2 from front to back; Finish if then be numbered 1 instruction write-back, then numbered for 1 free time, four instructions numbering from front to back becomes 0,3,2,1 when new instruction flows into.Order number flows in the middle of streamline along with instructing, and is used for the position that sign is in instruction correspondence in the middle of the instruction stream control module of central other grade of streamline.
Whether the emission complement mark is used to indicate current instruction and launches, and it is as one of controlled condition of instruction emission, is used for preventing that the instruction of having launched from launching again.
Instruction enters module in the mode of displacement at first, equally, the movement of instruction in the middle of module also carried out according to the mode of displacement, finish as an instruction write-back, be that writing back of the correspondence sent here of instruction write-back control module finished signal when effective, its corresponding command information is deleted in the middle of module, the command information of every instruction of this instruction back is mobile clauses and subclauses forward, the blank that deleted command information stays is filled up by the instruction of back, and the clauses and subclauses that backmost are available are used for receiving the new instruction that flows into.
Simultaneously, the module emission complement mark that allows signal and command information to work as according to the emission instruction of selecting next bar to launch.Its selective rule is: have only all instructions before this instruction all launch to finish and the emission permission signal of this instruction could be launched this instruction effective the time.
The data that instruction issuing module is then sent here according to the command information in the instruction stream control module and data bypass module are finished signal and are determined that instruction can launch, and its Rule of judgment is as follows:
1. the functional unit free time that will use of this instruction.
2. though the data that will write back of each bar instruction before this instruction are not the data that have this instruction to read in the middle of this instruction data that will read or the instruction before this instruction data that will write back, these these data bypasses are finished.Whether detect when this instruction each bar before instructs the data data whether this instruction will be read that will write back only needs the destination register of relatively this instruction all instructions before identical with the source-register of this instruction, when the destination register of all instructions of the source-register of this instruction and its front was inequality, this condition satisfied.Whether data bypass is finished and is then needed to finish signal according to the data bypass that the data bypass module is sent here and effectively judge.
3. the instruction of current emission or instruction before are not memory reference instructions.
The reason of adding the 3rd be in this module the conflict between the data according to register identical realization the whether, can not the detection of stored device data collision of visit, the data collision of detection of stored device visit needs the value in the middle of the register can carry out after reading.For fear of between the memory reference instruction and the conflict between memory reference instruction and other instruction, need to add the 3rd Rule of judgment.
The register access module is then carried out register access according to the command information of instruction stream control module, and the result of visit is delivered to instruction sending module, as one of chosen candidate value of the operand of final output.
The data bypass module then is redirected to certain bar instruction in the middle of the instruction stream control module according to the command information in the middle of the instruction control module with bypass data, produce this director data bypass and finish signal and bypass useful signal data, give instruction emission control module and instruction sending module respectively.The source of bypass data has: functional unit is carried out and is finished the data that produce and write back control module data medium to be write back, the numbering cycle of this bypass data instruction of source-register, destination register and generation in the middle of the command information that bypass control module is sent here according to the instruction stream control module decides needs that bypass data is redirected to instruct for which bar, and then produces corresponding data bypass and finish signal and bypass data useful signal.
Write back and allow module to produce according to the command information in the middle of the instruction stream control module to write back the permission signal, in the middle of the instruction of indicator flow control module, which bar instruction can write back, and this signal given writes back control module.Write back and allow module to detect the read/write conflict in the middle of the instruction and write write conflict, it detects also is by the source-register between the comparison order and destination register identical realization the whether.Write back and allow the effective Rule of judgment of signal to be: though the destination register of this instruction is all inequality or its destination register is identical with the source-register of its front bar instruction with the destination register of any instruction of its front and source-register, this instruction is launched.
The structure of instruction sending module as shown in Figure 4, instruction sending module is selected the final operand as firing order in the middle of register access result and the bypass data according to the bypass data useful signal, and output.The command information of the firing order that the instruction stream control module is sent is sent to instruction sending module, is also sent by instruction sending module.
Write back the structural drawing of control module as shown in Figure 5:
Write back the command information of instruction and write back and allow signal to be sent to write back the result to deposit module, write back the result and deposit module command information is deposited, output module uses for writing back as a result, and allows signal to judge that current which bar instruction can write back according to writing back.Write back the destination register that writing back information of instruction comprise instruction numbering cycle, instruction, the value that instruction will write back, write back structure that the result deposits module as shown in Figure 6.
The writing back useful signal and show whether the content in the current clauses and subclauses needs to write back of instruction, if the content in the current clauses and subclauses has write back to register or be not the content that need write back register, then this useful signal is invalid; The information that writes back instruction comprises the destination address of the instruction that current needs write back, the value of writing back of instruction etc.It is corresponding with each clauses and subclauses in the middle of the encoded control module to write back each clauses and subclauses that the result deposits in the module, and its correspondence equates to realize that whether each clauses and subclauses can write back according to following conditions is judged by the numbering cycle that makes call instruction:
1. the instruction write-back useful signal is high.
2. corresponding instruction write-back permission signal is high.
3. the condition that writes back is not all satisfied in all instructions of this instruction front.
Three conditions the time, the content of corresponding clauses and subclauses is sent to and writes back output module as a result above satisfying, and writes back in the middle of the register, simultaneously, writes back the result and deposits module and produce to write back and finish signal.
In the middle of total system, the encoded control module is the control center of instruction emission, be the control center that writes back of instruction and write back control module, whole out of order emission kernel is divided into these two modules to be realized, two modules cooperate to finish the out of order execution of instruction mutually.
The above only is the specific embodiment of the present invention, not in order to limiting the present invention, and those of skill in the art under any the present invention, in the technical scope that the present invention discloses, the modification of doing or replacement all should be encompassed within protection scope of the present invention.
Claims (1)
1. out of order emission processor cores of gene comprises the encoded control module and writes back control module, corresponding to the decode stage in the middle of the processor pipeline with write back level, it is characterized in that:
Described encoded control module comprises: instruction stream control module, instruction emission control module, data bypass control module, register access module, write back and allow module and instruction sending module;
Described instruction stream control module is responsible for receiving the M instruction that will launch, and the implementation status of recording instruction information, detection instruction is used for other module; Allow the emission situation of signal and the instruction of current M bar to decide any bar instruction to launch according to emission, and this signal is sent, use for other module; Finish signal according to writing back writing back that control module sends here, deletion has write back the instruction of finishing, and reads in new instruction; Described M is the natural number greater than 1;
Described instruction issuing module is finished signal according to the command information in the middle of the instruction stream control module and data bypass, determines the conflict of central which the bar instruction of M bar instruction to solve, and produces the signal that emission allows, for other module use;
Described data bypass control module receives and writes back the bypass data that control module is sent back to, is redirected to the instruction that needs these data, produces the signal that this data bypass of indication is finished then, uses for other module;
Described register access module is carried out the visit of register according to the command information of instruction stream control module, and the result that will visit sends, and uses for other module;
Described writing back allows module according to the information in the middle of the instruction stream control module, whether the register that decides every instruction to upgrade has read is finished, when register read finish after, send and write back the permission signal, the data that show this instruction can be upgraded register, and this signal sent, use for other module;
The information that described instruction sending module according to which bar instruction can be launched is selected the instruction that will launch from the instruction of M bar, select the up-to-date operand of this instruction in the middle of the data of returning from register file memory access result and bypass, and the up-to-date operand of the instruction that will launch and instruction is sent;
The described control module that writes back comprises: write back the result and deposit module and write back output module;
The described result of writing back deposits module and is responsible for receiving the M bar instruction that will write back, and the result that will write back, the information such as destination register that will write back note, allow signal to decide any bar instruction to write back according to writing back of sending here of instruction stream control module, generation writes back finishes signal, uses for other module;
The described output module that writes back writes back to the current result that will write back in the middle of the register according to writing back the information that the result deposits in the middle of the module, finishes data and writes back.
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| CN201310076580.8A CN103207776B (en) | 2013-03-11 | 2013-03-11 | Out-of-order gene issuing processor core |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110007966A (en) * | 2019-04-10 | 2019-07-12 | 龚伟峰 | A method of it reducing memory and reads random ordering |
| CN110297662A (en) * | 2019-07-04 | 2019-10-01 | 深圳芯英科技有限公司 | Instruct method, processor and the electronic equipment of Out-of-order execution |
| CN111930427A (en) * | 2020-08-17 | 2020-11-13 | 北京百度网讯科技有限公司 | Instruction transmitting method, instruction transmitting device, electronic equipment and storage medium |
| CN112581351A (en) * | 2020-12-05 | 2021-03-30 | 西安翔腾微电子科技有限公司 | Write-back unit structure of dual-emission SIMT dyeing processing unit and write-back channel conflict detection method |
| CN117667223A (en) * | 2024-02-01 | 2024-03-08 | 上海登临科技有限公司 | Data adventure solving method, computing engine, processor and electronic equipment |
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Cited By (8)
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| CN110007966A (en) * | 2019-04-10 | 2019-07-12 | 龚伟峰 | A method of it reducing memory and reads random ordering |
| CN110297662A (en) * | 2019-07-04 | 2019-10-01 | 深圳芯英科技有限公司 | Instruct method, processor and the electronic equipment of Out-of-order execution |
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| CN117667223B (en) * | 2024-02-01 | 2024-04-12 | 上海登临科技有限公司 | Data adventure solving method, computing engine, processor and electronic equipment |
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