CN101866281A - Multi-cycle instruction execution method and device - Google Patents
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Abstract
The invention puts forward a multi-cycle instruction execution method, which includes the following steps: initializing instruction codes, and storing initialized instruction information; according to all the initialized effective instruction information, judging whether a next instruction entering a pipeline is a normal pipeline instruction or a bubble instruction, and generating an indication signal; according to the instruction information, judging whether to buffer, directly register or buffer and write an execution result into a register, and providing the execution result for a subsequent instruction entering the pipeline; and according to the indication signal and the execution result, judging the instruction information in order to update the instruction information. The multi-cycle instruction execution method ensures the validity of executed instructions after the instruction execution cycle is changed.
Description
Technical field
The present invention relates to digital processing device, electronic equipment and disposal system technical field, particularly a kind of multi-cycle instruction execution method and device.
Background technology
Microprocessor is a SIC (semiconductor integrated circuit) that is integrated on a slice, comprises control and execution to a series of arithmetical logic operations.One of basic task of design processor is the time that will shorten interpretive order, promptly improves the speed that the processor instruction is carried out.Usually the approach that improves instruction execution speed has following three kinds:
1, improves the work dominant frequency of processor;
2, adopt better algorithm and design better functional part;
3, many executing instructions are called instruction level concurrent technique.
Nearest 2 years, therefore the more high-performance of processor proposed the strategy of various raising performances owing to can not be resolved from traditional structure.Wherein improve clock frequency and the functional unit performance is seemingly limited, the best way is to improve concurrency, and the principal feature of current high performance processor structure has adopted various parallel processing techniques exactly.Improve the operation concurrency, have two approach to realize: improve the quantity of the operation of every instruction execution, or improve the quantity that executes instruction in each instruction cycle.The method that improves execution command quantity has two kinds: superscale and very long instruction word (VLIW).
But the vliw architecture microprocessor is arranged in the operation of executed in parallel on each instruction segment in the very long instruction word statically by optimizing compiler.Article one, long instruction comprises a plurality of can parallel work-flow the instruction, and each elementary instruction can be carried out a plurality of simple instructions by the relevant hardware complete operation in the clock period.
For a specific VLIW structure, instruction fetch word and instruction distribution can be one or more levels flowing water, and every instruction enters that the streamline of process is identical before the functional unit, enter functional unit after, the execution cycle number difference of different instruction, pipeline series difference.
Vliw microprocessor is simple and have the great potential of exploitation instruction-level parallelism and be celebrated with its hardware controls, and this potentiality are as cost with the static scheduling of the repetition of resource and instruction.In order to make VLIW instruction concurrency maximizing efficiency, compiler must be found enough instruction codes of filling, and for fear of the relevant problem of data occurring, compiler must determine that instruction execution cycle number under the current hardware configuration is to finish scheduling.Therefore when HardwareUpgring, the instruction execution cycle number may change, and the binary code of legacy version might execution error on new hardware.At the streamline of simple function unit the elongated and execution cycle number of the execution cycle number two kinds of situations that shorten are arranged.Therefore under the situation of not taking any measure, when execution cycle number changed, the result after instruction is carried out can change, and produces error result.
Summary of the invention
The present invention is intended to one of solve the problems of the technologies described above at least, particularly solves at hardware to change and instruction execution cycle changes the binary code compatibling problem brought.
For achieving the above object, one aspect of the present invention has proposed a kind of multi-cycle instruction execution method, wherein, carry out described multi-cycle instruction execution method under the binary compatible pattern opening, described multi-cycle instruction execution method may further comprise the steps: order code is carried out initialization and initialized command information is finished in preservation; To adjudicate instruction that next bar enters streamline be normal instruction pipeline or cavity instruction and produce indicator signal to finish initialized effective instruction information according to all; Judge whether execution result is carried out buffer memory, directly deposits or buffer memory writes register according to described command information, and provide described execution result for the follow-up instruction that enters streamline; According to described indicator signal and described execution result described command information is judged to upgrade described command information.
In one embodiment of the invention, described command information emphasis comprises: current: current hardware version allows the instruction number of following, and its value equals described current hardware version instruction execution cycle number and subtracts 1; Previous: before hardware version allow the instruction number of following, its value equal described before hardware version instruction execution cycle number subtract 1; Exist: actual instruction number of following described instruction; Valid: actual described instruction and the effective instruction number of following, for following the quantity of the described normal instruction pipeline after present instruction; With the Information sign position.
In one embodiment of the invention, described order code begins initialization to put the exist=0 of described order code after entering the decoding stage, and valid=0 obtains the value of the current and the previous of described order code, and the control bit signal of being correlated with.
In one embodiment of the invention, finishing initialized effective instruction information according to all, to adjudicate the instruction that next bar enters streamline be that normal instruction pipeline or cavity instruction comprise: send the Instruction Selection signal to described streamline, described Instruction Selection signal is used to control the instruction that enters decode stage and is normal instruction or cavity instruction; Preposition streamline to described streamline when the instruction that enters decode stage in described Instruction Selection signal controlling is the cavity instruction sends the signal that stops a performance period; Provide described streamline to add the indicator signal of normal instruction or cavity instruction for upgrading described command information; When described indicator signal provides the message unit of described command information number to upgrade described command information for the renewal of described command information during for the indicator signal of described cavity instruction.
In one embodiment of the invention, the condition of described command information adding cavity instruction is: current＞previous; Exist＞=previous; Exist＜current; Current-previous-(exist-valid)＞0.
In one embodiment of the invention, the renewal of described command information comprises: the unit information significance bit that reads all command informations is the value of all message units of 1; Judge that the exist of each described message unit and current upgrade described command information with foundation judged result and described indicator signal and described execution result.
In one embodiment of the invention, judge with the foundation judged result according to the value of previous, current, exist and the valid of described effective instruction information described execution result is carried out buffer memory, directly deposits or buffer memory writes register.
Also proposed a kind of multi-cycle instructions actuating unit in another aspect of this invention, having comprised: the command information decoder module is used for order code is carried out initialization; The command information memory module is used for preserving and finishes initialized command information; The streamline control module, to adjudicate instruction that next bar enters streamline be normal instruction pipeline or cavity instruction and produce indicator signal to be used for finishing initialized effective instruction information according to all; The buffer memory control module, described buffer memory control module judges whether execution result is carried out buffer memory, directly deposits or buffer memory writes register according to described command information, and provides described execution result for the follow-up instruction that enters streamline; With the command information update module, described command information update module is judged to upgrade described command information described command information according to described indicator signal and described execution result.
In one embodiment of the invention, described streamline controlling sub at first sends the Instruction Selection signal to described streamline, and described Instruction Selection signal is used to control the instruction that enters decode stage and is normal instruction or cavity instruction; Preposition streamline to described streamline when secondly the instruction that enters decode stage in described Instruction Selection signal controlling is the cavity instruction sends the signal that stops a performance period; Renewal for described command information provides described streamline to add the indicator signal of normal instruction or cavity instruction then; Provide the message unit of described command information number to upgrade described command information for the renewal of described command information during for the indicator signal of described cavity instruction when described indicator signal at last.
In one embodiment of the invention, to be used to control the instruction that enters decode stage be that the condition of cavity instruction is: current＞previous to described Instruction Selection signal; Exist＞=previous; Exist＜current; Current-previous-(exist-valid)＞0.
In one embodiment of the invention, described command information update module at first reads the value that the unit information significance bit of all command informations is all message units of 1; Judge that then the exist of each described message unit and current upgrade described command information with foundation judged result and described indicator signal and described execution result; The described command information that renewal is finished is saved in the command information memory module at last.
In one embodiment of the invention, described buffer memory control module is judged with the foundation judged result according to the value of previous, current, exist and the valid of described effective instruction information described execution result is carried out buffer memory, directly deposits or buffer memory writes register.
Multi-cycle instruction execution method according to the embodiment of the invention, guaranteed the correctness of the data relationship between instruction, thereby guaranteed the instruction binary code under equally can correct execution legacy version hardware environment under the new hardware environment, further solve the binary code compatibling problem of the instruction cycles change that brings owing to HardwareUpgring, guaranteed the correctness of subsequent instructions execution result.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the streamline synoptic diagram of very long instruction word (VLIW) framework of the embodiment of the invention;
Fig. 2 is the multi-cycle instruction execution method process flow diagram of the embodiment of the invention;
Fig. 3 is the multi-cycle instruction execution method synoptic diagram of the embodiment of the invention;
Fig. 4 is the connection diagram of the multi-cycle instruction execution method and the streamline of the embodiment of the invention;
Fig. 5 is the multi-cycle instructions actuating unit structural drawing of the embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.
Notion and the corresponding multi-cycle instruction execution method of the present invention by introducing the binary code execution pattern, guaranteed the correctness of the data relationship between instruction, thereby guaranteed the instruction binary code under equally can correct execution legacy version hardware environment under the new hardware environment, further solve the binary code compatibling problem of the instruction cycles change that brings owing to HardwareUpgring, guaranteed the correctness of subsequent instructions execution result.The present invention be directed to because the instruction execution result that the hardware environment change is caused is inconsistent, and a kind of multi-cycle instruction execution method that proposes, this method can be by guaranteeing the consistance that subsequent instructions is carried out on the streamline inserting cavity instruction and buffer memory instruction execution result dual mode on the streamline under the new and old edition hardware environment, thereby guaranteed in the instruction execution cycle correctness that the back executes instruction that changes.
Below with reference to the multi-cycle instruction execution method of accompanying drawing description according to the embodiment of the invention.
In order clearer understanding to be arranged to embodiments of the invention, the multi-cycle instruction execution method that the present invention proposes is to implement at the streamline of very long instruction word (VLIW) framework, so, below the streamline of very long instruction word (VLIW) framework that just embodiment of the invention proposed do simple introduction, as shown in Figure 1, streamline synoptic diagram for very long instruction word (VLIW) framework of the embodiment of the invention, from Fig. 1, can obviously find out, article one, very long instruction word (among the figure for instruction fetch word stage) comprises a plurality of instructions that can parallel work-flow, and each elementary instruction is by the corresponding functional unit complete operation.VLIW framework for the present embodiment proposition, instruction fetch word and instruction distribution can be one or more levels flowing water, the streamline of process is identical before the functional unit and every elementary instruction enters, yet after elementary instruction enters functional unit, the execution cycle number of different elementary instructions is not quite similar, so pipeline series is also different.
As shown in Figure 2, be the multi-cycle instruction execution method process flow diagram of the embodiment of the invention, simultaneously with reference to figure 3, Fig. 4.This multi-cycle instruction execution method may further comprise the steps:
Step S101 carries out initialization and initialized command information is finished in preservation to order code.Particularly, described order code is the binary code of elementary instruction, and from the pipeline register before the functional unit decode stage, can obviously see functional unit decode stage pipeline register before from Fig. 4.In Fig. 3, can find out, order code is carried out initialization in the command information decoder module, and the command information that initialization is finished is stored in the command information memory module, this command information is made up of 9 values, be respectively: the unit information significance bit, the command information significance bit, old edition allows to trail instruction number: previous, new edition allows to trail instruction number: current, the actual instruction number of trailing: exist, actual trailing and effective instruction number: vaild, wherein vaild is the quantity of trailing the described normal instruction pipeline after present instruction, the cavity instruction that if the instruction of trailing is other command requests to add, then be not counted in the value of vaild, in an embodiment of the present invention, the cavity instruction is the nop instruction, certainly, also can replace the nop instruction, write the buffer memory indicating bit with other forms of instruction, the register number that is buffered, data in buffer.Wherein, unit information significance bit and the initialization of command information significance bit are put 1, obtain the actual value of current and previous by the instruction decode of actual processor, the value of exist and vaild is put 0, write buffer memory indicating positions 0, it is invalid that register number that is buffered and data in buffer are put, and finishes this command information initialization.
Step S102, to adjudicate instruction that next bar enters streamline be normal instruction pipeline or cavity instruction and produce indicator signal to finish initialized effective instruction information according to all.Particularly, simultaneously with reference to figure 3, it is that normal instruction pipeline or cavity instruct that the streamline control module is adjudicated the instruction that next bar enters streamline by the value of more described command information, more specifically, with reference to figure 4, have only value to satisfy condition simultaneously when described command information:
current＞previous；
exist＞＝previous；
exist＜current；
current-previous-(exist-valid)＞0。
It is that nop instructs to streamline with the instruction of controlling next bar and entering streamline that this streamline control module sends Instruction Selection signal, send streamline stall signal simultaneously and in streamline, be used to stop performance period of corresponding streamline, it should be noted that this streamline stall signal finished before instruction enters the pipeline decoding level.Opposite, if when described command information does not satisfy condition, the instruction that control enters streamline is normal instruction pipeline.In one embodiment of the invention, with reference to figure 3 and Fig. 4, the streamline control module also is used for sending indicator signal to the command information update module in each performance period process, this command information update module is upgraded the value of the command information in the current performance period according to indicator signal, for streamline control module and buffer memory control module in the next performance period provide the value of right instructions information, so that corresponding operation is made in instruction.
Step S103 judges whether execution result is carried out buffer memory, directly deposits or buffer memory writes register according to described command information, and provides described execution result for the follow-up instruction that enters streamline.Particularly, with reference to figure 3, in one embodiment of the invention, the value of the exist of this command information and current at first relatively, have only when exist=current, this buffer memory control module obtains the execution result and the execution result register number of this instruction from streamline, when command information satisfies condition:
Write the buffer memory indicating bit: 1;
exist＝current；
previous-current+(exist-valid)＞0。
Execution result and result register number are stored in the command information memory module, when subsequent instructions needs described execution result, again this execution result is transferred to the pipeline register from the command information memory module and used for subsequent instructions.
In one embodiment of the invention, when satisfying condition:
exist＝current；
previous-current+(exist-valid)＝0；
Write the buffer memory indicating bit: 0.
This buffer memory control module directly stores the instruction execution result of obtaining from streamline the pipeline register into and uses for subsequent instructions.
Simultaneously, the buffer memory control module sends to information updating module to execution result, and information updating module is upgraded the value of the command information in the current performance period according to this execution result.
Step S104 judges to upgrade described command information described command information according to described indicator signal and described execution result.Particularly, from Fig. 3, can find out, in one embodiment of the invention, this command information update module is obtained the indicator signal of streamline control module transmission and the execution result that the buffer memory control module sends, compare the exist of each message unit and the value of current, when it satisfies following condition:
| Condition | Condition | Update mode |
| ??exist＝current | ??previous-current+ | Unit information significance bit: 0 |
| ??(exist-valid)＝0 | Other values are no longer safeguarded |
| Condition | Condition | Update mode |
| ??exist＝current | ??previous-current+??(exist-valid)＞0 | Unit information significance bit: 1 command information significance bit: 0 current: keep previous: keep exist: keep vaild: according to the value of " streamline indicator signal " and " message unit number ", judgement adds 1 or keep and write the buffer memory indicating bit: 1 register number that is buffered: from the buffer memory control value of obtaining data in buffer: from the buffer memory control value of obtaining |
| ??exist＜current | Unit information significance bit: keep the command information significance bit: keep current: keep previous: keep exist: add 1 vaild: according to the value of " streamline indicator signal " and " message unit number ", judgement adds 1 or keep and write the buffer memory indicating bit: keep the register number that is buffered: keep data in buffer: keep |
According to above-mentioned condition update instruction information, thereby upgrade in each performance period the value of the corresponding instruction information in the instruction information storage module, and the command information that renewal finishes is offered streamline control module and buffer memory control module for next performance period use.
For the embodiment of the invention there being more deep understanding, below the mode of just specifically giving an example the present invention is described in detail.Simultaneously with reference to figure 3 and Fig. 4, begin explanation after entering pipeline decoding level circuit with instruction in one embodiment of the invention, in this example, instruction sequence comprises:
Instruction O:current=0, previous=0, an one-cycle instruction;
Instruction A, current=2, previous=1;
Instruction B, current=3, previous=3.
When instruction cycles elongated, instruction sequence OOA (the advanced pipeline decoding of the instruction on the right, A at first enters streamline and deciphers) when legacy version is carried out second instruction O reads is the execution result of A, and the multi-cycle instruction execution method that adopts proposition of the present invention in redaction has guaranteed the correctness of execution result, below with regard to the specific implementation process of above-mentioned this method of instruction.
Periodicity 1:
Streamline control module: normal flowing water;
Buffer memory control module: do not have operation;
Information storage module: the information initializing to instruction A comprises unit information active position 1, command information active position 1, and current puts 2, previous puts 1, and exist puts 0, and vaild puts 0, hold and write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and data in buffer is put invalid.
Periodicity 2:
Streamline control module: read the information of A, because exist＜previous does not satisfy the nop condition that adds, so normal flowing water;
Buffer memory control module: because exist is not equal to previous, so there is not operation;
Information storage module: the information of instruction A: exist＜current, normal flowing water, the unit information significance bit: 1, command information active position 1, current puts 2, previous puts 1, exist puts 1, and vaild puts 1, holds to write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and data in buffer is put invalid;
Information initializing to first O comprises unit information active position 1, command information active position 1, and current puts 0, previous puts 0, and exist puts 0, and vaild puts 0, write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and data in buffer is put invalid.
Periodicity 3:
The streamline control module: read the information of A, previous is satisfied to add the nop condition owing to exist equals, so add the nop instruction.Read the information of first O, because exist=previous does not satisfy the nop condition that adds, so normal flowing water;
The buffer memory control module: read the information of A, because exist＜current, so there is not operation;
Read the information of first O, judge exist=current, previous-current+ (exist-valid)=0 writes the buffer memory indicating bit: 0, and satisfy and directly write register;
Information storage module: the information of instruction A: exist＜current, oneself requires to add nop, unit information active position 1, command information active position 1, current puts 2, previous puts 1, exist puts 2, and vaild puts 2, holds to write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and data in buffer is put invalid;
The information of first O: because exist=current, so that information is put is invalid.
Periodicity 4:
Streamline control module: read the information of A, because exist greater than previous, does not satisfy the nop condition that adds, so normal flowing water;
The buffer memory control module: read the information of A, exist=current, previous-current+ (exist-valid)=0 writes the buffer memory indicating bit: 0, satisfy and directly write register;
Information storage module: the information of instruction A: exist=current, information is put invalid, and the information of nop is carried out initialization.
Carrying out sequence as can be seen by this example is O, Nop, O, A, owing in redaction, Duoed a performance period,, guaranteed that A can read the execution result of A at back second the instruction O that be finished so in redaction, inserted a nop instruction than the performance period of A in the legacy version.
Below just with above-mentioned A, B, O instruction is example, when instruction occurs when nested, what instruction sequence OOAB (the right instruct advanced streamline) second instruction O when legacy version is carried out read is the execution result of A, that second instruction O reads is the preceding result of execution of B.So under situation about changing in the redaction performance period, below illustrate the implementation of this method with regard to the present invention.
Because the implementation in the implementation of periodicity 1,2,3 and above-mentioned the giving an example is basic identical, in order to prevent redundancy, does not do too much explanation at this.
Periodicity 1: advance to instruct B
Periodicity 2: advance to instruct A
Periodicity 3: advance first instruction O
Periodicity 4:
The streamline control module: read the information of B, because exist＜previous, so do not add nop;
Read the information of A, exist＞=previous satisfies and to add the nop condition, adds nop;
Read the information of first O, exist=previous does not satisfy the nop condition that adds;
The buffer memory control module: read the information of B, because exist＜current, so there is not operation;
Read the information of A, exist＜current does not have operation;
Read the information of first O, exist=current, previous-current+ (exist-valid)=0 writes the buffer memory indicating bit: 0, satisfy and directly write register;
Information storage module: the information of instruction B: exist＜current, other command requests add nop, unit information active position 1, command information active position 1, current puts 3, previous puts 3, exist puts 3, and vaild puts 2, holds to write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and data in buffer is put invalid; The information of instruction A: exist＜current, oneself requires to add nop, unit information active position 1, command information active position 1, current puts 2, previous puts 1, exist puts 2, and vaild puts 2, holds to write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and data in buffer is put invalid; The information of first O: exist=currnt, information is put invalid.
Periodicity 5:
Streamline control module: read the information of B, do not satisfy the nop condition that adds;
Read the information of A, do not satisfy the nop condition that adds;
The buffer memory control module: read the information of B, exist=current, previous-current+ (exist-valid)＞0 writes buffer memory, for the command information memory module provides execution result, result register number, writing buffer memory prompting position is 1; Read the information of A, register writes direct; Read the information of first O, exist=current, previous-current+ (exist-valid)=0 writes the buffer memory indicating bit: 0, satisfy and directly write register;
Information storage module:
The information of instruction B: exist＜current, other command requests add nop, unit information active position 1, command information active position 1, current puts 3, previous puts 3, exist puts 3, and vaild puts 3, holds to write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and data in buffer is put invalid; The information of instruction A: information is put invalid; The information of second O: initialization.
Periodicity 6:
Streamline control module: normal flowing water;
The buffer memory control module: read the information of B, exist=current, previous-current+ (exist-valid)=0, writing buffer memory prompting position is 1, carries from the command information memory module and reads execution result, result register number writes register;
Information storage module: it is invalid that the B command information is put; The information of new instruction: initialization.
Obtaining carrying out sequence by this routine manner of execution is O, Nop, O, A, B, because inserted a nop instruction,, obtained elimination by buffer memory for the influence of instruction B and insert the nop order tape so second instruction O can read correct value, so second also correct B that read of instruction O carries out preceding value, after buffer memory write register, the value that follow-up instruction can reading command B be finished had guaranteed that the redaction execution result satisfies the execution requirement of legacy version equally.
The present invention has also proposed a kind of corresponding multi-cycle instructions actuating unit on the other hand, be illustrated in figure 5 as the multi-cycle instructions actuating unit one-piece construction figure of the embodiment of the invention, this multi-cycle instructions actuating unit 100 comprises command information decoder module 110, command information memory module 120, streamline control module 130, command information update module 140 and buffer memory control module 150.Wherein, command information decoder module 110 is used for order code is carried out initialization.Command information memory module 120 is used for preserving and finishes initialized command information.Streamline control module 130, to adjudicate instruction that next bar enters streamline be normal instruction pipeline or cavity instruction and produce indicator signal to be used for finishing initialized effective instruction information according to all.Buffer memory control module 140, described buffer memory control module 140 judges whether execution result is carried out buffer memory, directly deposits or buffer memory writes register according to described command information, and provides described execution result for the follow-up instruction that enters streamline.Command information update module 150, described command information update module 150 is judged to upgrade described command information described command information according to described indicator signal and described execution result.
In one embodiment of the invention, described streamline control module 130 at first sends the Instruction Selection signal to described streamline, described Instruction Selection signal is used to control the instruction that enters decode stage and is normal instruction or cavity instruction, preposition streamline to described streamline when secondly the instruction that enters decode stage in described Instruction Selection signal controlling is the cavity instruction sends the signal that stops a performance period, the indicator signal that provides described streamline to add normal instruction or cavity instruction for the renewal of described command information then provides the message unit of described command information number to upgrade described command information for the renewal of described command information when indicator signal that described indicator signal is instructed for described cavity at last.Wherein, to be used to control the instruction that enters decode stage be that the condition of cavity instruction is: current＞previous, exist＞=previous, exist＜current to described Instruction Selection signal; Current-previous-(exist-valid)＞0.
In one embodiment of the invention, the slow 140 data cached conditions of described buffer memory control module are: exist=current, and previous-current+ (exist-valid)＞0.And sending execution result after satisfying the buffer memory condition is used for described buffer memory indicating positions 1 to information updating module 150.
In one embodiment of the invention, the described unit information significance bit that described command information update module 150 at first reads described command information is the value of all message units of 1, the indicator signal that the value of judging the described exist of each described message unit and described current then sends with foundation judged result and streamline control module 130 is upgraded described command information with the execution result of buffer memory control module 140 transmissions, and the described command information that renewal is finished is saved in the command information memory module 120 at last.
Multi-cycle instruction execution method by embodiment of the invention proposition, guaranteed the correctness of the data relationship between instruction, thereby guaranteed the instruction binary code under equally can correct execution legacy version hardware environment under the new hardware environment, further solve the binary code compatibling problem of the instruction cycles change that brings owing to HardwareUpgring, guaranteed the correctness of subsequent instructions execution result.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification that scope of the present invention is by claims and be equal to and limit to these embodiment.
Claims (12)
1. a multi-cycle instruction execution method is characterized in that, is opening the described multi-cycle instruction execution method of execution under the binary compatible pattern, and wherein, multi-cycle instruction execution method may further comprise the steps:
Order code is carried out initialization and initialized command information is finished in preservation;
To adjudicate instruction that next bar enters streamline be normal instruction pipeline or cavity instruction and produce indicator signal to finish initialized effective instruction information according to all;
Judge whether execution result is carried out buffer memory, directly deposits or buffer memory writes register according to described command information, and provide described execution result for the follow-up instruction that enters streamline;
According to described indicator signal and described execution result described command information is judged to upgrade described command information.
2. multi-cycle instruction execution method as claimed in claim 1 is characterized in that, described command information emphasis comprises:
Current: current hardware version allows the instruction number of following, and its value equals described current hardware version instruction execution cycle number and subtracts 1;
Previous: before hardware version allow the instruction number of following, its value equal described before hardware version instruction execution cycle number subtract 1;
Exist: actual instruction number of following described instruction;
Valid: actual described instruction and the effective instruction number of following, for following the quantity of the described normal instruction pipeline after present instruction; With
The Information sign position.
3. multi-cycle instruction execution method as claimed in claim 2, it is characterized in that described order code begins initialization to put the exist=0 of described order code, valid=0 after entering the decoding stage, obtain the value of the current and the previous of described order code, and relevant control bit signal.
4. multi-cycle instruction execution method as claimed in claim 1 is characterized in that, finishing initialized effective instruction information according to all, to adjudicate the instruction that next bar enters streamline be that normal instruction pipeline or cavity instruction comprise:
Send the Instruction Selection signal to described streamline, described Instruction Selection signal is used to control the instruction that enters decode stage and is normal instruction or cavity instruction;
Preposition streamline to described streamline when the instruction that enters decode stage in described Instruction Selection signal controlling is the cavity instruction sends the signal that stops a performance period;
Provide described streamline to add the indicator signal of normal instruction or cavity instruction for upgrading described command information;
When described indicator signal provides the message unit of described command information number to upgrade described command information for the renewal of described command information during for the indicator signal of described cavity instruction.
5. multi-cycle instruction execution method as claimed in claim 4 is characterized in that, the condition that described command information adds the cavity instruction is:
current＞previous；
exist＞＝previous；
exist＜current；
current-previous-(exist-valid)＞0。
6. multi-cycle instruction execution method as claimed in claim 4 is characterized in that, the renewal of described command information comprises:
The unit information significance bit that reads all command informations is the value of all message units of 1;
Judge that the exist of each described message unit and current upgrade described command information with foundation judged result and described indicator signal and described execution result.
7. multi-cycle instruction execution method as claimed in claim 6, it is characterized in that, judge with the foundation judged result according to the value of previous, current, exist and the valid of described effective instruction information described execution result is carried out buffer memory, directly deposits or buffer memory writes register.
8. a multi-cycle instructions actuating unit is characterized in that, comprising:
The command information decoder module is used for order code is carried out initialization;
The command information memory module is used for preserving and finishes initialized command information;
The streamline control module, to adjudicate instruction that next bar enters streamline be normal instruction pipeline or cavity instruction and produce indicator signal to be used for finishing initialized effective instruction information according to all;
The buffer memory control module, described buffer memory control module judges whether execution result is carried out buffer memory, directly deposits or buffer memory writes register according to described command information, and provides described execution result for the follow-up instruction that enters streamline; With
The command information update module, described command information update module is judged to upgrade described command information described command information according to described indicator signal and described execution result.
9. multi-cycle instructions actuating unit as claimed in claim 8, it is characterized in that, described streamline controlling sub at first sends the Instruction Selection signal to described streamline, and described Instruction Selection signal is used to control the instruction that enters decode stage and is normal instruction or cavity instruction; Preposition streamline to described streamline when secondly the instruction that enters decode stage in described Instruction Selection signal controlling is the cavity instruction sends the signal that stops a performance period; Renewal for described command information provides described streamline to add the indicator signal of normal instruction or cavity instruction then; Provide the message unit of described command information number to upgrade described command information for the renewal of described command information during for the indicator signal of described cavity instruction when described indicator signal at last.
10. multi-cycle instructions actuating unit as claimed in claim 9 is characterized in that, it is that the condition that cavity instructs is that described Instruction Selection signal is used to control the instruction that enters decode stage:
current＞previous；
exist＞＝previous；
exist＜current；
current-previous-(exist-valid)＞0。
11. multi-cycle instructions actuating unit as claimed in claim 10 is characterized in that, the unit information significance bit that described command information update module at first reads all command informations is the value of all message units of 1; Judge that then the exist of each described message unit and current upgrade described command information with foundation judged result and described indicator signal and described execution result; The described command information that renewal is finished is saved in the command information memory module at last.
12. multi-cycle instructions actuating unit as claimed in claim 11, it is characterized in that described buffer memory control module is judged with the foundation judged result according to the value of previous, current, exist and the valid of described effective instruction information described execution result is carried out buffer memory, directly deposits or buffer memory writes register.
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