CN101866281B - Multi-cycle instruction execution method and device - Google Patents
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Abstract
The invention puts forward a multi-cycle instruction execution method, which includes the following steps: initializing instruction codes, and storing initialized instruction information; according to all the initialized effective instruction information, judging whether a next instruction entering a pipeline is a normal pipeline instruction or a bubble instruction, and generating an indication signal; according to the instruction information, judging whether to buffer, directly register or buffer and write an execution result into a register, and providing the execution result for a subsequent instruction entering the pipeline; and according to the indication signal and the execution result, judging the instruction information in order to update the instruction information. The multi-cycle instruction execution method ensures the validity of executed instructions after the instruction execution cycle is changed.
Description
Technical field
The present invention relates to digital processing device, electronic equipment and disposal system technical field, particularly a kind of multi-cycle instruction execution method and device.
Background technology
Microprocessor is a SIC (semiconductor integrated circuit) that is integrated on a slice, comprises control and execution to a series of arithmetical logic operations.One of basic task of design processor is the time that will shorten interpretive order, namely improves the speed that the processor instruction is carried out.Usually the approach that improves instruction execution speed has following three kinds:
1, improve the work dominant frequency of processor;
2, adopt better algorithm and design better functional part;
3, many executing instructions, be called instruction level concurrent technique.
Nearest 2 years, therefore the more high-performance of processor proposed the various high performance strategies of carrying owing to not being resolved from traditional structure.Wherein improve clock frequency and the functional unit performance is seemingly limited, the best way is to improve concurrency, and the principal feature of current high performance processor structure has adopted various parallel processing techniques exactly.Improve the operation concurrency, have two approach to realize: improve the quantity of the operation of every instruction execution, or improve the quantity of carrying out instruction in each instruction cycle.Improve the method for carrying out instruction number and have two kinds: superscale and very long instruction word (VLIW).
But the vliw architecture microprocessor is arranged in the operation of executed in parallel on each instruction segment in a very long instruction word statically by Optimizing Compiler.Article one, long instruction comprise a plurality of can the parallel work-flow instruction, each elementary instruction can be carried out a plurality of simple instructions by corresponding hardware complete operation in the clock period.
For a specific VLIW structure, instruction fetch word and instruction distribution can be one or more levels flowing water, and before every instruction entered function unit, the streamline of process is identical, and behind the entered function unit, the execution cycle number of different instruction is different, the pipeline series difference.
Vliw microprocessor is simple and have the great potential of exploitation instruction-level parallelism and famous with its hardware controls, and this potentiality are as cost with the static scheduling of the repetition of resource and instruction.In order to make VLIW parallel instructions maximizing efficiency, compiler must be found enough instruction codes of filling, and for fear of the relevant problem of data occurring, compiler must determine that instruction execution cycle number under current hardware configuration is to complete scheduling.Therefore when HardwareUpgring, the instruction execution cycle number may change, and the binary code of legacy version might execution error on new hardware.For the streamline of simple function unit, the elongated and execution cycle number of the execution cycle number two kinds of situations that shorten are arranged.Therefore in the situation that do not take any measure, when execution cycle number changed, the result after instruction is carried out can change, and produces error result.
Summary of the invention
The present invention is intended to one of solve the problems of the technologies described above at least, and particularly solving changes at hardware changes with instruction execution cycle the binary code compatibling problem that brings.
For achieving the above object, one aspect of the present invention has proposed a kind of multi-cycle instruction execution method, wherein, carry out described multi-cycle instruction execution method under the binary compatible pattern opening, described multi-cycle instruction execution method comprises the following steps: order code is carried out initialization and initialized command information is completed in preservation; To adjudicate next instruction that enters streamline be normal instruction pipeline or cavity instruction and produce indicator signal to complete initialized effective instruction information according to all; Judge whether execution result is carried out buffer memory, directly deposits or buffer memory writes register according to described command information, and provide described execution result for the follow-up instruction that enters streamline; According to described indicator signal and described execution result, described command information is judged to upgrade described command information.
In one embodiment of the invention, described command information emphasis comprises: current: current hardware version allows the instruction number of following, and its value equals described current hardware version instruction execution cycle number and subtracts 1; Previous: before hardware version allow the instruction number of following, its value equal described before hardware version instruction execution cycle number subtract 1; Exist: actual instruction number of following described instruction; Valid: actual described instruction and the effective instruction number of following, for following the quantity of the described normal instruction pipeline after present instruction; With the Information sign position.
In one embodiment of the invention, described order code begins initialization putting the exist=0 of described order code after entering the decoding stage, and valid=0 obtains the value of current and the previous of described order code, and relevant control position signal.
In one embodiment of the invention, completing initialized effective instruction information according to all, to adjudicate next instruction that enters streamline be that normal instruction pipeline or cavity instruction comprise: send the Instruction Selection signal to described streamline, it is normal instruction or cavity instruction that described Instruction Selection signal is used for controlling the instruction that enters decode stage; Preposition streamline to described streamline when the instruction that enters decode stage in described Instruction Selection signal controlling is the cavity instruction sends the signal that stops a performance period; Provide described streamline to add the indicator signal of normal instruction or cavity instruction for upgrading described command information; When described indicator signal provides the message unit of described command information number to upgrade described command information for the renewal of described command information during for the indicator signal of described cavity instruction.
In one embodiment of the invention, described command information adds the condition of cavity instruction to be: current＞previous; Exist＞=previous; Exist＜current; Current-previous-(exist-valid)＞0.
In one embodiment of the invention, the renewal of described command information comprises: the unit information significance bit that reads all command informations is the value of all message units of 1; Judge that the exist of each described message unit and current upgrade described command information with foundation judged result and described indicator signal and described execution result.
In one embodiment of the invention, judge with the foundation judged result according to the value of previous, current, exist and the valid of described effective instruction information described execution result is carried out buffer memory, directly deposits or buffer memory writes register.
Also proposed in another aspect of this invention a kind of multi-cycle instructions actuating unit, having comprised: the command information decoder module is used for order code is carried out initialization; The command information memory module is used for preserving and completes initialized command information; The Pipeline control module, to adjudicate next instruction that enters streamline be normal instruction pipeline or cavity instruction and produce indicator signal to be used for completing initialized effective instruction information according to all; The buffer control module, described buffer control module judges whether execution result is carried out buffer memory, directly deposits or buffer memory writes register according to described command information, and provides described execution result for the follow-up instruction that enters streamline; With the command information update module, described command information update module judges to upgrade described command information according to described indicator signal and described execution result to described command information.
In one embodiment of the invention, at first described Pipeline control submodule sends the Instruction Selection signal to described streamline, and it is normal instruction or cavity instruction that described Instruction Selection signal is used for controlling the instruction that enters decode stage; Preposition streamline to described streamline when the instruction that secondly enters decode stage in described Instruction Selection signal controlling is the cavity instruction sends the signal that stops a performance period; Then the renewal for described command information provides described streamline to add the indicator signal of normal instruction or cavity instruction; Provide the message unit of described command information number to upgrade described command information for the renewal of described command information during for the indicator signal of described cavity instruction when described indicator signal at last.
In one embodiment of the invention, be used for to control the instruction that enters decode stage be that the condition of cavity instruction is: current＞previous to described Instruction Selection signal; Exist＞=previous; Exist＜current; Current-previous-(exist-valid)＞0.
In one embodiment of the invention, at first described command information update module reads the value that the unit information significance bit of all command informations is all message units of 1; Then judge that the exist of each described message unit and current upgrade described command information with foundation judged result and described indicator signal and described execution result; The described command information of at last renewal being completed is saved in the command information memory module.
In one embodiment of the invention, described buffer control module judges with the foundation judged result according to the value of previous, current, exist and the valid of described effective instruction information described execution result is carried out buffer memory, directly deposits or buffer memory writes register.
Multi-cycle instruction execution method according to the embodiment of the present invention, guaranteed the correctness of the data relationship between instruction, thereby guaranteed correctly to carry out equally the instruction binary code under the legacy version hardware environment under new hardware environment, further solve the binary code compatibling problem of the instruction cycles change that brings due to HardwareUpgring, guaranteed the correctness of subsequent instructions execution result.
The aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or the additional aspect of the present invention and advantage will become from the following description of the accompanying drawings of embodiments and obviously and easily understand, wherein:
Fig. 1 is the streamline schematic diagram of very long instruction word (VLIW) framework of the embodiment of the present invention;
Fig. 2 is the multi-cycle instruction execution method process flow diagram of the embodiment of the present invention;
Fig. 3 is the multi-cycle instruction execution method schematic diagram of the embodiment of the present invention;
Fig. 4 is the connection diagram of multi-cycle instruction execution method and the streamline of the embodiment of the present invention;
Fig. 5 is the multi-cycle instructions actuating unit structural drawing of the embodiment of the present invention.
Embodiment
The below describes embodiments of the invention in detail, and the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the present invention, and can not be interpreted as limitation of the present invention.
Concept and the corresponding multi-cycle instruction execution method of the present invention by introducing the binary code execution pattern, guaranteed the correctness of the data relationship between instruction, thereby guaranteed correctly to carry out equally the instruction binary code under the legacy version hardware environment under new hardware environment, further solve the binary code compatibling problem of the instruction cycles change that brings due to HardwareUpgring, guaranteed the correctness of subsequent instructions execution result.The present invention be directed to the instruction execution result that causes due to the hardware environment change inconsistent, and a kind of multi-cycle instruction execution method that proposes, the method can be by in the consistance of inserting cavity instruction and buffer memory instruction execution result dual mode on streamline guarantee that on streamline, subsequent instructions is carried out under the new and old edition hardware environment, thereby has guaranteed to carry out the correctness of instruction after instruction execution cycle changes.
Below with reference to the multi-cycle instruction execution method of accompanying drawing description according to the embodiment of the present invention.
in order clearer understanding to be arranged to embodiments of the invention, the multi-cycle instruction execution method that the present invention proposes is to implement for the streamline of very long instruction word (VLIW) framework, so, below the streamline of very long instruction word (VLIW) framework that just embodiment of the present invention proposed do simple introduction, as shown in Figure 1, streamline schematic diagram for very long instruction word (VLIW) framework of the embodiment of the present invention, can obviously find out from Fig. 1, article one, very long instruction word (in figure for instruction fetch word stage) comprises a plurality of instructions that can parallel work-flow, each elementary instruction is by the corresponding functional unit complete operation.VLIW framework for the present embodiment proposition, instruction fetch word and instruction distribution can be one or more levels flowing water, and before every elementary instruction entered function unit, the streamline of process is identical, yet behind elementary instruction entered function unit, the execution cycle number of different elementary instructions is not quite similar, so pipeline series is also different.
As shown in Figure 2, be the multi-cycle instruction execution method process flow diagram of the embodiment of the present invention, simultaneously with reference to figure 3, Fig. 4.This multi-cycle instruction execution method comprises the following steps:
Step S101 carries out initialization and initialized command information is completed in preservation to order code.Particularly, described order code is the binary code of elementary instruction, and from the pipeline register before the functional unit decode stage, can obviously see functional unit decode stage pipeline register before from Fig. 4.can find out in Fig. 3, order code is carried out initialization in the command information decoder module, and the command information that initialization is completed is stored in the command information memory module, this command information is comprised of 9 values, be respectively: the unit information significance bit, the command information significance bit, old edition allows to trail instruction number: previous, new edition allows to trail instruction number: current, the actual instruction number of trailing: exist, actual trailing and effective instruction number: vaild, wherein vaild is the quantity of trailing the described normal instruction pipeline after present instruction, the cavity instruction that if the instruction of trailing is other command requests to add, be not counted in the value of vaild, in an embodiment of the present invention, the cavity instruction is the nop instruction, certainly, also can replace the nop instruction with other forms of instruction, write the buffer memory indicating bit, the register number that is buffered, the data of buffer memory.Wherein, unit information significance bit and the initialization of command information significance bit are put 1, obtain the actual value of current and previous by the Instruction decoding of actual processor, the value of exist and vaild is set to 0, write buffer memory indicating positions 0, it is invalid that the register number that is buffered and the data of buffer memory are put, and completes this command information initialization.
Step S102, to adjudicate next instruction that enters streamline be normal instruction pipeline or cavity instruction and produce indicator signal to complete initialized effective instruction information according to all.Particularly, with reference to figure 3, it is normal instruction pipeline or cavity instruction that the Pipeline control module is adjudicated next instruction that enters streamline by the value of more described command information, more specifically simultaneously, with reference to figure 4, only have the value when described command information to satisfy condition simultaneously:
current＞previous；
exist＞＝previous；
exist＜current；
current-previous-(exist-valid)＞0。
This Pipeline control module sends the Instruction Selection signal to streamline to control next instruction that enters streamline as the nop instruction, send simultaneously streamline stall signal and be used in the streamline stopping performance period of corresponding streamline, it should be noted that this streamline stall signal completed before instruction enters the pipeline decoding level.Opposite, if when described command information does not satisfy condition, controlling the instruction that enters streamline is normal instruction pipeline.In one embodiment of the invention, with reference to figure 3 and Fig. 4, the Pipeline control module also is used for sending indicator signal to the command information update module in each performance period process, this command information update module is upgraded the value of the command information in the current performance period according to indicator signal, for Pipeline control module and buffer memory control module in the next performance period provide the value of right instructions information, in order to corresponding operation is made in instruction.
Step S103 judges whether execution result is carried out buffer memory, directly deposits or buffer memory writes register according to described command information, and provides described execution result for the follow-up instruction that enters streamline.Particularly, with reference to figure 3, in one embodiment of the invention, at first relatively the value of the exist of this command information and current, only have when exist=current, this buffer control module obtains execution result and the execution result register number of this instruction from streamline, when command information satisfies condition:
Write the buffer memory indicating bit: 1;
exist＝current；
previous-current+(exist-valid)＞0。
Execution result and result register number are stored in the command information memory module, transfer to this execution result pipeline register for subsequent instructions from the command information memory module again when subsequent instructions needs described execution result.
In one embodiment of the invention, when satisfying condition:
exist＝current；
previous-current+(exist-valid)＝0；
Write the buffer memory indicating bit: 0.
This buffer control module directly stores the instruction execution result of obtaining from streamline pipeline register into for subsequent instructions.
Simultaneously, the buffer control module sends to information updating module to execution result, and information updating module is upgraded the value of the command information in the current performance period according to this execution result.
Step S104 judges to upgrade described command information according to described indicator signal and described execution result to described command information.Particularly, can find out from Fig. 3, in one embodiment of the invention, this command information update module is obtained the indicator signal of Pipeline control module transmission and the execution result that the buffer memory control module sends, compare the exist of each message unit and the value of current, when it satisfies following condition:
| Condition | Condition | Update mode |
| exist＝current | previous-current+ | Unit information significance bit: 0 |
| (exist-valid)＝0 | Other values are no longer safeguarded | |
| exist＝current | previous-current+ (exist-valid)＞0 | Unit information significance bit: 1 command information significance bit: 0 current: keep previous: keep exist: keep vaild: according to the value of " streamline indicator signal " and " message unit number ", judgement adds 1 or keep and write the buffer memory indicating bit: 1 register number that is buffered: from the data of the buffer control value of obtaining buffer memory: from the buffer control value |
| exist＜current | Unit information significance bit: keep the command information significance bit: keep current: keep previous: keep exist: add 1 vaild: according to the value of " streamline indicator signal " and " message unit number ", judgement adds 1 or keep and write the buffer memory indicating bit: keep the register number that is buffered: the data of keeping buffer memory: keep |
According to above-mentioned condition update instruction information, thereby upgrade the value of the corresponding command information in the instruction information storage module in each performance period, and offer Pipeline control module and buffer memory control module for the next one performance period upgrading a complete command information.
For the embodiment of the present invention there being more deep understanding, below with regard to the mode of concrete example, the present invention is described in detail.Simultaneously with reference to figure 3 and Fig. 4, begin explanation after entering pipeline decoding level circuit with instruction in one embodiment of the invention, in this example, instruction sequence comprises:
Instruction O:current=0, previous=0, an one-cycle instruction;
Instruction A, current=2, previous=1;
Instruction B, current=3, previous=3.
When instruction cycles elongated, instruction sequence OOA (the advanced pipeline decoding of the instruction on the right, at first A enters streamline and carries out decoding) second instruction O reads when legacy version is carried out is the execution result of A, and the multi-cycle instruction execution method that adopts proposition of the present invention in redaction has guaranteed the correctness of execution result, below with regard to the specific implementation process of above-mentioned instruction the method.
Periodicity 1:
Pipeline control module: positive perennial draingage;
Buffer control module: without operation;
Information storage module: the information initializing to instruction A comprises unit information active position 1, command information active position 1, and current puts 2, previous puts 1, exist and sets to 0, and vaild sets to 0, hold and write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and it is invalid that the data of buffer memory are put.
Periodicity 2:
Pipeline control module: read the information of A, due to exist＜previous, do not satisfy the nop condition that adds, so positive perennial draingage;
Buffer control module: because exist is not equal to previous, so without operation;
Information storage module: the information of instruction A: exist＜current, positive perennial draingage, the unit information significance bit: 1, command information active position 1, current puts 2, previous puts 1, exist puts 1, vaild and puts 1, holds to write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and it is invalid that the data of buffer memory are put;
Information initializing to first O comprises unit information active position 1, command information active position 1, and current sets to 0, previous sets to 0, and exist sets to 0, and vaild sets to 0, write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and it is invalid that the data of buffer memory are put.
Periodicity 3:
The Pipeline control module: read the information of A, previous is satisfied adds the nop condition because exist equals, so add the nop instruction.Read the information of first O, due to exist=previous, do not satisfy the nop condition that adds, so positive perennial draingage;
Buffer control module: read the information of A, due to exist＜current, so without operation;
Read the information of first O, judgement exist=current, previous-current+ (exist-valid)=0 writes the buffer memory indicating bit: 0, satisfy and directly write register;
Information storage module: the information of instruction A: exist＜current, oneself requires to add nop, unit information active position 1, command information active position 1, current puts 2, previous puts 1, exist puts 2, vaild and puts 2, holds to write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and it is invalid that the data of buffer memory are put;
The information of first O: due to exist=current, so that information is put is invalid.
Periodicity 4:
Pipeline control module: read the information of A, greater than previous, do not satisfy the nop condition that adds due to exist, so positive perennial draingage;
The buffer control module: read the information of A, exist=current, previous-current+ (exist-valid)=0 writes the buffer memory indicating bit: 0, satisfy and directly write register;
Information storage module: the information of instruction A: exist=current, information is put invalid, and the information of nop is carried out initialization.
Can find out that by this example carrying out sequence is O, Nop, O, A, owing to having Duoed a performance period than the performance period of A in legacy version, so inserted a nop instruction in redaction, guaranteed that A second instruction O after being finished can read the execution result of A in redaction.
Below just with above-mentioned A, B, the O instruction is example, when the instruction appearance is nested, what instruction sequence OOAB (the right instruction advanced streamline) second instruction O when legacy version is carried out read is the execution result of A, and what second instruction O read is the front result of execution of B.So when in the situation that the redaction performance period changes, below illustrate the implementation of the method with regard to the present invention.
Due to periodicity 1,2,3 implementation and above-mentioned implementation in for example basic identical, in order to prevent redundancy, do not do too much explanation at this.
Periodicity 1: advance instruction B
Periodicity 2: advance instruction A
Periodicity 3: advance first instruction O
Periodicity 4:
Pipeline control module: read the information of B, due to exist＜previous, so do not add nop;
Read the information of A, exist＞=previous satisfies and to add the nop condition, adds nop;
Read the information of first O, exist=previous does not satisfy the nop condition that adds;
Buffer control module: read the information of B, due to exist＜current, so without operation;
Read the information of A, exist＜current is without operation;
Read the information of first O, exist=current, previous-current+ (exist-valid)=0 writes the buffer memory indicating bit: 0, satisfy and directly write register;
Information storage module: the information of instruction B: exist＜current, other command requests add nop, unit information active position 1, command information active position 1, current puts 3, previous puts 3, exist puts 3, vaild and puts 2, holds to write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and it is invalid that the data of buffer memory are put; The information of instruction A: exist＜current, oneself requires to add nop, unit information active position 1, command information active position 1, current puts 2, previous puts 1, exist puts 2, vaild and puts 2, holds to write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and it is invalid that the data of buffer memory are put; The information of first O: exist=currnt, information is put invalid.
Periodicity 5:
Pipeline control module: read the information of B, do not satisfy the nop condition that adds;
Read the information of A, do not satisfy the nop condition that adds;
The buffer control module: read the information of B, exist=current, previous-current+ (exist-valid)＞0 writes buffer memory, for the command information memory module provides execution result, result register number, writing buffer memory prompting position is 1; Read the information of A, register writes direct; Read the information of first O, exist=current, previous-current+ (exist-valid)=0 writes the buffer memory indicating bit: 0, satisfy and directly write register;
Information storage module:
The information of instruction B: exist＜current, other command requests add nop, unit information active position 1, command information active position 1, current puts 3, previous puts 3, exist puts 3, vaild and puts 3, holds to write buffer memory indicating positions 0, it is invalid that the register number that is buffered is put, and it is invalid that the data of buffer memory are put; The information of instruction A: information is put invalid; The information of second O: initialization.
Periodicity 6:
Pipeline control module: positive perennial draingage;
The buffer control module: read the information of B, exist=current, previous-current+ (exist-valid)=0, writing buffer memory prompting position is 1, carries from the command information memory module and reads execution result, result register number writes register;
Information storage module: it is invalid that the B command information is put; The information of new instruction: initialization.
Obtaining carrying out sequence by this routine manner of execution is O, Nop, O, A, B, because inserted a nop instruction, so second instruction O can read correct value, obtained elimination to the impact of instruction B by buffer memory and insert the nop order tape, so second instruction O be the correct value that has read before B carries out also, after buffer memory write register, the value that follow-up instruction can reading command B be finished had guaranteed that the redaction execution result satisfies the execution requirements of legacy version equally.
The present invention has also proposed a kind of corresponding multi-cycle instructions actuating unit on the other hand, be illustrated in figure 5 as the multi-cycle instructions actuating unit one-piece construction figure of the embodiment of the present invention, this multi-cycle instructions actuating unit 100 comprises command information decoder module 110, command information memory module 120, Pipeline control module 130, command information update module 140 and buffer memory control module 150.Wherein, command information decoder module 110 is used for order code is carried out initialization.Command information memory module 120 is used for preserving and completes initialized command information.Pipeline control module 130, to adjudicate next instruction that enters streamline be normal instruction pipeline or cavity instruction and produce indicator signal to be used for completing initialized effective instruction information according to all.Buffer control module 140, described buffer control module 140 judges whether execution result is carried out buffer memory, directly deposits or buffer memory writes register according to described command information, and provides described execution result for the follow-up instruction that enters streamline.Command information update module 150, described command information update module 150 judges to upgrade described command information according to described indicator signal and described execution result to described command information.
in one embodiment of the invention, at first described Pipeline control module 130 sends the Instruction Selection signal to described streamline, it is normal instruction or cavity instruction that described Instruction Selection signal is used for controlling the instruction that enters decode stage, preposition streamline to described streamline when the instruction that secondly enters decode stage in described Instruction Selection signal controlling is the cavity instruction sends the signal that stops a performance period, then the renewal for described command information provides described streamline to add the indicator signal of normal instruction or cavity instruction, provide the message unit of described command information number to upgrade described command information for the renewal of described command information during for the indicator signal of described cavity instruction when described indicator signal at last.Wherein, be used for to control the instruction that enters decode stage be that the condition of cavity instruction is: current＞previous, exist＞=previous, exist＜current to described Instruction Selection signal; Current-previous-(exist-valid)＞0.
In one embodiment of the invention, the slow 140 data cached conditions of described buffer control module are: exist=current, and previous-current+ (exist-valid)＞0.And sending execution result after satisfying the buffer memory condition is used for described buffer memory indicating positions 1 to information updating module 150.
In one embodiment of the invention, the described unit information significance bit that at first described command information update module 150 reads described command information is the value of all message units of 1, then the indicator signal that the value that judges the described exist of each described message unit and described current sends with foundation judged result and Pipeline control module 130 is upgraded described command information with the execution result of buffer control module 140 transmissions, and the described command information of at last renewal being completed is saved in command information memory module 120.
The multi-cycle instruction execution method that proposes by the embodiment of the present invention, guaranteed the correctness of the data relationship between instruction, thereby guaranteed correctly to carry out equally the instruction binary code under the legacy version hardware environment under new hardware environment, further solve the binary code compatibling problem of the instruction cycles change that brings due to HardwareUpgring, guaranteed the correctness of subsequent instructions execution result.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is by claims and be equal to and limit.
Claims (11)
1. a multi-cycle instruction execution method, is characterized in that, opening the described multi-cycle instruction execution method of execution under the binary compatible pattern, and wherein, multi-cycle instruction execution method comprises the following steps:
Order code is carried out initialization and initialized command information is completed in preservation, and wherein, described command information comprises: current: current hardware version allows the instruction number of following, and its value equals described current hardware version instruction execution cycle number and subtracts 1; Previous: before hardware version allow the instruction number of following, its value equal described before hardware version instruction execution cycle number subtract 1; Exist: actual instruction number of following described instruction; Valid: actual described instruction and the effective instruction number of following, for following the quantity of the normal instruction pipeline after present instruction; With the Information sign position;
To adjudicate next instruction that enters streamline be normal instruction pipeline or cavity instruction and produce indicator signal to complete initialized command information according to all;
Judge whether execution result is carried out buffer memory, directly deposits or buffer memory writes register according to described command information, and provide described execution result for the follow-up instruction that enters streamline;
According to described indicator signal and described execution result, described command information is judged to upgrade described command information.
2. multi-cycle instruction execution method as claimed in claim 1, it is characterized in that, described order code begins initialization to put the exist=0 of described order code, valid=0 after entering the decoding stage, obtain the value of current and the previous of described order code, and the control bit signal.
3. multi-cycle instruction execution method as claimed in claim 1, is characterized in that, completing initialized command information according to all, to adjudicate next instruction that enters streamline be that normal instruction pipeline or cavity instruction comprise:
Send the Instruction Selection signal to described streamline, it is normal instruction pipeline or cavity instruction that described Instruction Selection signal is used for controlling the instruction that enters decode stage;
Preposition streamline to described streamline when the instruction that enters decode stage in described Instruction Selection signal controlling is the cavity instruction sends the signal that stops a performance period;
Provide described streamline to add the indicator signal of normal instruction pipeline or cavity instruction for upgrading described command information;
When described indicator signal provides the message unit of described command information number to upgrade described command information for the renewal of described command information during for the indicator signal of described cavity instruction.
4. multi-cycle instruction execution method as claimed in claim 3, is characterized in that, described command information adds the condition of cavity instruction to be:
current＞preyious；
exist＞＝preyious；
exist＜current；
current-preyious-(exist-valid)＞0。
5. multi-cycle instruction execution method as claimed in claim 3, is characterized in that, the renewal of described command information comprises:
The unit information significance bit that reads all command informations is the value of all message units of 1;
Judge that the exist of each described message unit and current upgrade described command information with foundation judged result and described indicator signal and described execution result.
6. multi-cycle instruction execution method as claimed in claim 5, it is characterized in that, judge with the foundation judged result according to the value of preyious, current, exist and the valid of described command information described execution result is carried out buffer memory, directly deposits or buffer memory writes register.
7. a multi-cycle instructions actuating unit, is characterized in that, comprising:
The command information decoder module is used for order code is carried out initialization;
The command information memory module be used for to be preserved and to be completed initialized command information, and wherein, described command information comprises: current: current hardware version allows the instruction number of following, and its value equals described current hardware version instruction execution cycle number and subtracts 1; Preyious: before hardware version allow the instruction number of following, its value equal described before hardware version instruction execution cycle number subtract 1; Exist: actual instruction number of following described instruction; Valid: actual described instruction and the effective instruction number of following, for following the quantity of the normal instruction pipeline after present instruction; With the Information sign position;
The Pipeline control module, to adjudicate next instruction that enters streamline be normal instruction pipeline or cavity instruction and produce indicator signal to be used for completing initialized command information according to all;
The buffer control module, described buffer control module judges whether execution result is carried out buffer memory, directly deposits or buffer memory writes register according to described command information, and provides described execution result for the follow-up instruction that enters streamline; With
The command information update module, described command information update module judges to upgrade described command information according to described indicator signal and described execution result to described command information.
8. multi-cycle instructions actuating unit as claimed in claim 7, it is characterized in that, at first described Pipeline control module sends the Instruction Selection signal to described streamline, and it is normal instruction pipeline or cavity instruction that described Instruction Selection signal is used for controlling the instruction that enters decode stage; Preposition streamline to described streamline when the instruction that secondly enters decode stage in described Instruction Selection signal controlling is the cavity instruction sends the signal that stops a performance period; Then the renewal for described command information provides described streamline to add the indicator signal of normal instruction pipeline or cavity instruction; Provide the message unit of described command information number to upgrade described command information for the renewal of described command information during for the indicator signal of described cavity instruction when described indicator signal at last.
9. multi-cycle instructions actuating unit as claimed in claim 8, is characterized in that, it is that the condition of cavity instruction is that described Instruction Selection signal be used for to be controlled the instruction that enters decode stage:
current＞preyious；
exis t＞＝preyious；
exist＜current；
current-preyious-(exist-valid)＞0。
10. multi-cycle instructions actuating unit as claimed in claim 9, is characterized in that, the unit information significance bit that at first described command information update module reads all command informations is the value of all message units of 1; Then judge that the exist of each described message unit and current upgrade described command information with foundation judged result and described indicator signal and described execution result; The described command information of at last renewal being completed is saved in the command information memory module.
11. multi-cycle instructions actuating unit as claimed in claim 10, it is characterized in that, described buffer control module judges with the foundation judged result according to the value of preyious, current, exist and the valid of described command information carries out buffer memory, directly deposits or buffer memory writes register described execution result.
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| CN111399912B (en) * | 2020-03-26 | 2022-11-22 | 超睿科技(长沙)有限公司 | Instruction scheduling method, system and medium for multi-cycle instruction |
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